!Technologia CMOS i co dalej? Materia y i struktury dla...
Transcript of !Technologia CMOS i co dalej? Materia y i struktury dla...
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Materia!y i struktury dla nanoelektroniki Jacek A. Majewski Instytut Fizyki Teoretycznej, Wydzia! Fizyki Uniwersytet Warszawski
ICM UW, Warszawa, 20 maja, 2013
www.fuw.edu.pl
Materia!y i struktury dla nanoelektroniki
!! Technologia CMOS i co dalej?
!! Wyzwania i modyfikacje CMOS
!! Rozwi"zania niskowymiarowe (druty, nanorurki)
!! Grafen
!! Transport dyfuzyjny i koherentny
Rewolucja informatyczna
Wyk!adniczy wzrost technologii informatycznych
Przetwarzana, zapami#tywana, i transmitowana g#sto$% informacji (liczba bitów na jednostk# pow.) ro$nie wyk!adniczo.
Ten szybki wzrost powoduje zmiany cywilizacyjne wp!ywa silnie na "wiatow# gospodark$ okre"la sposób w jaki pracujemy, bawimy si$, etc.
Moore’s Law
Wyk!adniczy post#p w integracji LLiicczzbbaa ttrraannzzyyssttoorróóww ww pprroocceessoorrzzee ppooddwwaajjaa ssii ccoo ~~22 llaattaa
PRAWO MOORE’a
65nm!
45nm!
32nm!
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Rozwój technologii obwodów scalonych
Pierwsze obwody scalone Texas Instruments
Procesor Pentium
Wielko$% chipu prawie bez zmian
kilka tranzystorów
Kilka milionów tranzystorów
MINIATURYZACJA!!!
JJaacckk KKiillbbyy
& Nagrody Nobla z Fizyki w 2000 r.
Cena tranzystora 10-7 $
Liczba sprzedanych tranzystorów w r. 2002 -- 1018
Przeci#tna cena tranzystora
Technologia CMOS osi"ga skal# nano Nanotechnologia krzemowa Obecnie produkowany procesor Intel’a w technologii 90 nm
Influenza virus
D!udo$% bramki ~ 2000 x mniejsza od $rednicy ludzkiego w!osa
Grubo$% tlenku po bramk" ~1.2 nm (5 atomowych warstw Si)
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Nanotechnologia ma ju' obecnie du'e znaczenie w dziedzinie elektroniki, gdzie utrzymuje si# trend w kierunku miniaturyzacji
Nanoelektronika
1965 - 1970, Integrated Circuits based on bipolar transistors
Since 1980, Integrated Circuits based on CMOS technology dominate,
Field Effect Transistor (FET)
Development of Integrated Circuits Technology
CMOS Technology
CMOS = Complementary Metal Oxide Semiconductor
Metal Oxide
Semiconductor p-Silicon
Depletion
VG = 0
x
Ec
Ev
EF
p-Si
M O S
QM x
SiO2
(Semiconductor = Silicon)
CMOS Technology – Biased Gate
Metal Oxide
Semiconductor p-Silicon
Depletion
VG > 0
x
Ec
Ev
EF
p-Si QM x
Semiconductor p-Silicon
Depletion
Metal Oxide
Inversion
VG >> 0 Ec
Ev
EF
p-Si QM
2DEG
Qn
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S D Gate
VG ( 0
S D Gate
VG >> 0
Current does not flow Current flows
State “0” State “1”
CMOS Technology
Logical circuits (processors) Memories
cutoff mode active mode
Operation of n-MOS FET in enhancement mode
(VG > Vth )
n+ n+ n+ n+
CMOS Technology – “Computational state” and material system
Abakus (~3000BC) Processor based on CMOS
S D Gate
Current
The material system: CMOS transistors
The computational state: position of the beads
The material system: A set of stings in a frame
The computational state: electron current flow
CMOS Technology
n-MOS p-MOS &
electrons in the channel
Complementary
holes in the channel
n+ n+ p+ p+
n well
p-type body
Complementary MOS technology employs MOS transistors of both polarities
CMOS devices are more difficult to fabricate than NMOS, but many more powerful circuits are possible with CMOS configuration
S D Gate
CMOS Technology – Important Parameter
Important parameter – gate length LG determines
stage of integration
switching speed
Nowadays it is necessary to remove ~1000 electrons from the channel
LG
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2D-Electron Gas!
Electron mobility Bulk GaAs at T=300 K – 9 000 cm2 V-1 s-1
2DEG at T=300 K in HEMT – 10 000-12 000 cm2 V-1 s-1
Electron mobility in 2DEG at low temperatures ( < 1 K) can reach 20 000 000 cm2 V-1 s-1 !!!
EF
z M AlGaAs GaAs
2DEG Ec
EF
z AlGaAs GaAs
2DEG Ec
Gated AlGaAs/GaAs heterostructure AlGaAS/GaAs heterostructure
Classical in-plane transport
Ballistic, Coherent Quantum Transport
Source
Gate Drain
GaAs - substrate
AlGaAs 2DEG
Mesoscopic devices – macroscopic with quantum effects present
How far can we push Si CMOS? Is it possible to keep exponential growth?
S. E. Thompson & S. Parthasarathy, materialstoday, June 2006
Si technology industry time line: possible time frame for new device types
WWhhaatt lliieess bbeeyyoonndd??
Ge, III-V channel materials
Carbon nanotubes GRAPHENE
Quantum Electronic Device
Single Electron Transistor
QED SET
spintronics
Nanotechnology Eras
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Ultimate electronics
Gate leakage current
S D Gate
Challenges – Gate Leakage Gate Oxide
Thinner gate oxides produce faster transistors The limit of Gate Oxide (SiO2) has been reached
30 nm transistor has 0.8 nm gate oxide layer Thinner oxides leak more
Gate oxide can get so thin that it no longer acts as a good insulator
High-K Gate insulator
n+ n+
High-K Gate Dielectric
New material replaces SiO2
Thicker physical film but the same capacitance
10 000 lower gate leakage for the same capacitance Alternative gate dielectrics to reduce gate leakage TiO2, HfO2, ZrO2, Ta2O5
Enhanced Hole mobility for Uniaxial Strained-Si
Strain in Si is introduced by Si1-xGex in the source/drain.
Higher hole mobility
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Why Germanium MOS Transistors?
HHiigghheerr ((llooww ffiieelldd)) mmoobbiilliittiieess
Problems with Ge
Heteroepitaxial Growth of Ge on Si
WWiitthh HH22 aannnneeaall,, ddiissllooccaattiioonnss aarree ccoonnffiinneedd ttoo tthhee SSii//GGee iinntteerrffaaccee lleeaavviinngg ddeeffeecctt ffrreeee ttoopp GGee llaayyeerrss..
New Materials for Si- Technology
Moore’s Law increasingly relies on material innovations
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Revolutionary CMOS Nanowires, Nanotubes
Epitaxial Growth of Vertical Nanowires
Controlled Growth and Structures of Molecular-Scale Silicon Nanowires
(a)!TEM images of 3.8-nm SiNWs
grown along the <110> direction
(c) cross-sectional image
(b) & (d) models based on Wulff construction
Yue Wu et al., NANO LETTERS 4, 433 (2004)
High Performance Silicon Nanowire Field Effect Transistors
Yi Cui, et al. NANO LETTERS 3, 149 (2003)
Comparison of SiNW FET transport parameters with those for state-of-the-art planar MOSFETs show that “SiNWs have the potential to exceed substantially conventional devices, and thus could be ideal building blocks for future nanoelectronics.”
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Nanocable device concepts
Gargini-type nanotransistor
High-k gate dielectric, e.g. ZrO2
nanorod, e.g Si/Ge or an alloy
metal gate electrode
possible MOS transistor structure
P. Gargini, (Director - Technology Strategy Intel Fellow) ‘Enlightenment beyond Classical CMOS’ ISS US 2002.
Si NW FETs: Experimental Status: ‘Top Down’
Ge Nanowires Synthesized by Low Temperature CVD
Single crystal Ge nanowires
Ge Nanowire FET with High K Gate Dielectric
KKeeyy CChhaalllleennggee:: CCoonnttrroolllleedd ggrroowwtthh
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Technologia pó!przewodników
Supramolekularna chemia
CZAS
SKALA
10 nm?
2015 ?
Elektronika oparta o nano-struktury pó!przewodnikowe i du'e moleku!y
“Top down”
“Bottom up”
?
?
Czy uda si# utrzyma% wyk!adniczy charakter wzrostu?
Nanorurki w$glowe podstaw# przysz!ych technologii informacyjnych ?
Delft, Tans, et al., Nature 393 (1998)
Harvard, Javel et al., Nano Letters 393 (1998)
Parametry tranzystorów lepsze od 2D FETs stosowanych w obecnych procesorach opartych o technologi# CMOS
Graphene Future of Nanoelectronics?
Nature, Vol. 448833, 15 March 2012
Graphene: !New Star of the Material World !NNoo.. ooff ppuubblliiccaattiioonn oonn ffuulllleerreenneess,, nnaannoottuubbeess,, aanndd GGrraapphheennee ppeerr yyeeaarr
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What is graphene?
2-dimensional hexagonal lattice "
of carbon" sp2 hybridized" carbon atoms" Among strongest bonds in nature
BBaassiiss ffoorr:: CC--6600 ((bbuucckkyy bbaallllss)) nnaannoottuubbeess
ggrraapphhiittee
Nobel Prize in Physics 2010 AAnnddrree GGeeiimm KKoonnssttaannttiinn NNoovvoosseelloovv
The Nobel Prize in Physics 2010 was awarded jointly to Andre Geim and Konstantin Novoselov "for groundbreaking experiments regarding the two-dimensional material ggrraapphheennee""
Graphene beginners kit
[[$$110000..0000]]
Perfect for students & teachers. Graphene Kit includes: 1g of Kish Graphite (grade 50), 25 ml Graphene Oxide (Aqueous Dispersion), 25 ml pristine graphene in solution, 8 small Silicon/ 300 nm Silicon Dioxide wafers (10 mm x10 mm squares), Graphene Scotch tape (1 roll).
Samples of graphene
a) Atomic force microscopy
b) Transmission electron microscopy image c) Scanning electron
microscope image
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‘‘Bottom up’ route to epitaxial graphene!
Also in ITME (Warsaw)"
Home of Epitaxial Graphene – !Georgia Tech Materials Science and Engineering Center "
Graphene in Poland
Nano Lett. (2011) , 11, 1786 Published March 25
PPooIIGG -- PPRROOJJEECCTT
On May 21, 2009,, HRL laboratories said that it had made devices from single-layer graphene on 2 inch diameter 6H-SiC wafers with much-improved performance figures.
Epitaxial graphene based devices
“They have world-record field mobility of approximately 6000 cm2/Vs, which is six to eight times higher than current state-of-the-art silicon n-MOSFETs,”
IEEE Electron Devices Lett. 30, 650-652 (2009)
Graphene Field Effect Transistors HRL Laboratories LLC of Malibu, CA, USA (5 Dec 2008) the first RF graphene FET based on epitaxial graphene, cut-off frequency (fT) of 4GHz
The first milestone to develop a new generation of carbon-based RF integrated circuits for ultra-high-speed, ultra-low-power applications.
For review see e.g. F. Schwierz, Nature Nanotechnology 5, 487 (2010)
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100-GHz Transistors from Wafer-Scale Epitaxial Graphene
Science 5 February 2010, Vol. 327. no. 5966, p. 662
epitaxial graphene synthesized on the silicon face of a silicon carbide wafer
a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers
The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length
Graphene transistors IBM, 5 February 2010 Published in Science Vol. 327 p. 662
These arrays of transistors, printed on silicon carbide wafer, operate at speeds of 100 gigahertz.
SSppeeeeddyy sswwiittcchheess
GGrraapphheennee oonn BBoorroonn NNiittrriiddee
Nano Lett. 1111, 2291 (2011)
SSTTMM mmeeaassuurreemmeennttss EExxttrraaoorrddiinnaarriillyy ffllaatt ggrraapphheennee llaayyeerrss
Roll-to-roll-process for fabrication of large graphene films
A transparent ultra-large-area graphene film transferred on a 35-inch PET sheet
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Roll-to-roll-process for fabrication of large graphene films (an application)
An assembled 3.1-inch graphene/PET touch panel with silver electrodes showing outstanding flexibility
A graphene-based touch-screen panel connected to a computer with control software
Graphene’s advantage:: cut-a-structure
Graphene Nanoribbon FETs (GNR FETs) I-V characteristics for different GNR widths
The schematic sketch of an GNR
Scheme of GNR FET I-V characteristics for n=12 GNRs with charge impurities
http://graphenetimes.com/
TTwwoo--DDiimmeennssiioonnaall NNeewwss aanndd CCoommmmeennttaarryy
(ffeeww ppaappeerrss aa ddaayy))
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Transport in nanostructures Macroscopic structures!! !Diffusive transport is dominant!!Nanostructures!! !Mostly coherent quantum transport regime!!!
!!Mezoscopic structures!!
!Quantum diffusive transport !
Quantum Coherent Transport Theory
Source Drain
Gate
V
VG
µ1
µ2
Channel
Quantum transport – the study of current flow on an atomistic scale
Physics of open systems
Conductance from Transmission!
( , ) ( , )F L F Ff E f E E Vµ = + ( , ) ( , )F R F Ff E f E Eµ =
Device Lead Lead
Contact Contact
L= EF + V L R R= EF
L- electrochemical potential = chemical potential + voltage
V – external bias EF – Fermi energy (chemical potential in the absence of bias)
The Landauer approach – very useful in describing mesoscopic transport The current through a conductor (device) is expressed in terms of probability that an electron can transmit through it !!
Leads are reservoirs of electrons in which energy- and momentum relaxation processes are so effective that the electron system remains in equilibrium even under a given applied voltage bias
1( , )exp[ ( )] 1Ff E
Eµ
! µ"
# +
The electron concentration in the leads is so high that the electrostatic potential in each lead is taken to be constant (as for the case of metal)
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Dzi#kuj# za uwag#!