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Transcript of Chapter 5 FIELD-EFFECT TRANSISTORS (FETs) · PDF file1 Chapter 5 FIELD-EFFECT TRANSISTORS...

  • 1

    Chapter 5

    FIELD-EFFECT TRANSISTORS(FETs)

    Chapter 5 FETs 1

    FETs is also a three terminal devices. For the FET an electric field is established by thecharges present that will control the conduction path of the output circuit without the needfor direct contact between the controlling and controlled quantities.

    DifferencesBJTs FETs

    (i) Current-controlled devices (i) Voltage-controlled devices

    Current I is a direct function Current I is a function of the voltageCurrent IC is a direct functionof the level of IB.

    Current ID is a function of the voltageVGS applied to the input circuit.

    Chapter 5 FETs 2

    (ii) Bipolar device (npn and pnp) (ii) Unipolar device (n-channel and p-channel)Conduction level is a function ofTwo carriers, electrons and holes.

    Conduction level is a function ofone type of carrier, either electrons (n-channel) or holes (p-channel).

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    Types of FETs :

    (i) Junction FETs (JFET) and (ii) Metal-Oxide-Semiconductor FETs (MOSFET)

    MOSFET can be divided to two types: (i) Depletion type and (ii) Enhancement type(ii) Enhancement type.

    The MOSFET transistor has become one of the most important devices used in the designand construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design.

    Chapter 5 FETs 3

    CONSTRUCTION and CHARACTERISTICS of JFETs

    Ex: n-channel JFETs

    The major part of the structure is the n-typematerial that forms the channel betweenthe embedded layers of p-type material.

    The top of the n-type channel is connectedthrough an ohmic contact to a terminalreferred to as the drain (D), while the lowerend of the same material is connected throughan ohmic contact to a terminal referred to asthe source (S).

    The two p-type materials are connectedtogether and to the gate (G) terminal.

    Chapter 5 FETs 4

    Therefore, the drain and source are connectedto the ends of the n-type channel and thegate to the two layers of p-type material.

    Under no-bias condition, there are two p-n junctions. The result is a depletion region ateach junction. A depletion region is that region void of free carriers and therefore unableto support conduction through the region.

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    Analogy

    The source of water pressure can be likened to the applied voltage from drain to sourcethat will establish a flow of water (electrons) from the spigot (source). The gate,through an applied signal (potential) controls the flow of water (charge) to the drain

    Chapter 5 FETs 5

    through an applied signal (potential), controls the flow of water (charge) to the drain .The drain and source terminals are at opposite ends of the n-channel because theterminology is defined for electron flow.

    VGS = 0V, VDS Some Positive Value

    In this figure, a positive voltage VDS has beenapplied across the channel and the gate hasbeen connected directly to the source toestablish the condition VGS=0V.

    The result is a gate and source terminal atthe same potential and a depletion region inthe low end of each p-material similar to thedistribution of the no-bias condition.

    The instant the voltage VDD (=VDS) is appliedthe electrons will be drawn to the drainterminal, establishing the conventional currentID. The path of charge flow clearly reveals that The drain and source currents are equivalent

    Chapter 5 FETs 6

    The drain and source currents are equivalent(ID=IS).The flow of charge is limited solely by theresistance of the n-channel between drain andsource.

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    It is noted here that the depletion region is wider near the top of both p-type materials. Assuminga uniform resistance in the n-channel, the resistanceof the channel can be broken down to the divisionsshown in the figure. The current ID will establishthe voltage levels through the channel as indicatedthe voltage levels through the channel as indicatedon the same figure.For example, the upper region of the p-typematerial will be reverse-biased by about 1.5V, withthe lower region only reverse-biased by 0.5V.

    Recall from the discussion of the diode operationthat the greater the applied reverse bias, the widerthe depletion region.

    Chapter 5 FETs 7

    The fact that the p-n junction is reverse biased for the length of the channel results in agate current of zero amperes. The fact that IG=0A is an important characteristics ofthe JFET.

    As the voltage VDS is increased from 0 to a few volts, the current will increase asdetermined by Ohms law. The relative straightness of the plot reveals that for the regionof low values of VDS, the resistance is essentially constant.As VDS increases and approaches a level referred to as VP, the depletion region will widen,causing a noticeable reduction in the channel width. The reduced path of conduction causesthe resistance to increase and the curve in the graph to occur. The more horizontal the curve, the higherthe resistance If VDS is increased to a level wherethe resistance. If VDS is increased to a level whereit appears that the two depletion regions would touchas shown in the figure, the condition is referred to asPinch Off will result.

    Chapter 5 FETs 8

    VP:Pinch-off voltage

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    In the saturation region, the level of ID remains essentially the same. Therefore, onceVDS > VP the JFET has the characteristics of a source current.As shown in the previous figure (output characteristics), the current is fixed at ID=IDSSbut the voltage VDS (for levels > VP) is determined by the applied load.

    The notation of IDSS is derived from the fact that it is the Drain-to-Source current witha Short-circuit connection from gate to source.

    IDSS is the maximum drain current for a JFET and is defined by the conditions

    Chapter 5 FETs 9

    DSS s t e a u d a cu e t o a J a d s de ed by t e co d t o sVGS = 0V and VDS > VP.

    VGS < 0 V

    VGS is the voltage from gate to source and is the controlling voltage of the JFET.

    For the n-channel device the controlling voltage VGS is made more and more negativeFrom its VGS = 0V level. In other words, the gate terminal will be set at lower and lowerpotential levels as compared to the source.

    In the figure, a negative voltage of 1V hasbeen applied between the gate and sourceterminals for a low level of VDS.The effect of the applied negative-bias VGSis to establish depletion regions similar tothose obtained with VGS =0V but at lowerlevels of VDS.The result of applying a negative bias to thegate is to reach the saturation level at a lowerlevel of VDS.The resulting saturation level for I has been

    Chapter 5 FETs 10

    The resulting saturation level for ID has beenreduced and in fact will continue to decreaseas VGS is made more and more negative.

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    The pinch-off voltage continues to drop in a parabolic manner as VGS becomes moreand more negative.Eventually, VGS when VGS = -VP will be sufficiently negative to establish a saturationlevel that is essentially 0 mA, for all practical purposes the dvice has been turned off.

    Chapter 5 FETs 11

    The level of VGS that results in ID = 0 mA is defined by VGS = VP with VP being anegative voltage for n-channel devices and a positive voltage for p-channel JFETs.

    Voltage-Controlled Resistor

    The region to the left of the pinch-off locus is referred to as ohmic or voltage-controlledresistance region. In this region, the JFET can actually be employed as a variableresistor whose resistance is controlled by the applied gate-to-source voltage.

    Note that the slope of each curve and therefore the resistance of the device betweendrain and source for VDS < VP is a function of the applied voltage VGS.d a a d sou ce o DS P s a u ct o o t e app ed o tage GSAs VGS becomes more and more negative, the slope of each curve becomes moreand more horizontal, corresponding with an increasing resistance level.

    The following equation will provide a good approximation to the resistance level interms of the applied voltage VGS.

    Chapter 5 FETs 12

    Where ro is the resistance with VGS = 0V and rd the resistance at a particular level ofVGS.For an n-channel JFET with ro equal to 10 kOhm (VGS =0V, VP=-6V), the above equationWill result in 40 kOhm at VGS = -3V.

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    p-Channel DevicesThe p-channel JFET is constructed in exactly the same manner as the n-channel device.The defined current directions are reversed as are the actual polarities for the voltage VGSand VDS.

    Chapter 5 FETs 13

    For the p-channel device, the channel will be constricted by increasing positive voltagesfrom gate to source and the double-subscript notation for VDS will result in negativevoltages for VDS on the above output characteristics which has an IDSS of 6 mA and apinch-off voltage of VGS = +6V. The minus signs for VDS simply indicate that the source isat a higher potential than the drain.

    Symbols

    n-channel JFET p-channel JFET

    The arrow is pointing in for n-channel device to represent the direction in which IG would flow if the p-n junction were forward-biased.

    The only difference in the symbol isthe direction of the arrow.

    Chapter 5 FETs 14

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    SUMMARY(i) The maximum current is defined as IDSS and occurs when VGS = 0V and VDS>=|VP|.(ii) For gate-to-source voltages VGS less than (more negative than) the pinch-off level,

    the drain current is 0A (ID=0A).(iii) For all levels of VGS between 0V and the pinch-off level, the current ID will range

    between IDSS and 0A, respectively.(iv) For p-channel JFETs a similar list mentioned above can be developed.

    Chapter 5 FETs 15

    TRANSFER CHARACTERISTICSFor the BJTs, the output current IC and input