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  • (19) United States (12) Patent Application Publication (10) Pub. No.: US 2012/02484.16 A1

    Zhou et al.

    US 2012O248416A1

    (43) Pub. Date: Oct. 4, 2012

    (54)

    (75)

    (73)

    (21)

    (22)

    (60)

    HIGH PERFORMANCE FIELD-EFFECT TRANSISTORS

    Inventors: Chongwu Zhou, Arcadia, CA (US); Alexander Badmaev, Hillsboro, OR (US); Chuan Wang, Albany, CA (US); Yuchi Che, Los Angeles, CA (US)

    Assignee: UNIVERSITY OF SOUTHERN CALIFORNLA, Los Angeles, CA (US)

    Appl. No.: 13/430,457

    Filed: Mar. 26, 2012

    Related U.S. Application Data

    Provisional application No. 61/468,993, filed on Mar. 29, 2011.

    Publication Classification

    (51) Int. Cl. HOIL 29/786 (2006.01) HOIL 29/06 (2006.01) HOIL 2/336 (2006.01)

    (52) U.S. Cl. ........ 257/29; 438/197; 257/9; 257/E29.022; 257/E29.297; 257/E21.411

    (57) ABSTRACT

    A high performance field-effect transistor includes a sub strate, a nanomaterial thin film disposed on the Substrate, a Source electrode and a drain electrode formed on the nano material thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the Source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proxi mate the source electrode and the drain electrode in the chan nel area.

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  • Patent Application Publication Oct. 4, 2012 Sheet 1 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 2 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 3 of 13 US 2012/024841.6 A1

  • Patent Application Publication Oct. 4, 2012 Sheet 4 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 5 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 7 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 8 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 9 of 13 US 2012/024841.6 A1

  • US 2012/024841.6 A1 Oct. 4, 2012 Sheet 10 of 13 Patent Application Publication

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  • Patent Application Publication Oct. 4, 2012 Sheet 12 of 13 US 2012/024841.6 A1

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  • Patent Application Publication Oct. 4, 2012 Sheet 13 of 13 US 2012/024841.6 A1

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  • US 2012/024841.6 A1

    HIGH PERFORMANCE FIELD-EFFECT TRANSISTORS

    CROSS-REFERENCE TO RELATED APPLICATION

    0001. This application claims priority to U.S. Application Ser. No. 61/468,993, filed on Mar. 29, 2011, and entitled Design and scalable fabrication approach for high perfor mance field-effect transistors based on carbon nanomateri als, which is incorporated by reference herein in its entirety.

    FEDERALLY SPONSORED RESEARCHOR DEVELOPMENT

    0002 This invention was made with government support under Grant No. 53-4502-6301 awarded by the National Sci ence Foundation. The government has certain rights in the invention.

    FIELD OF THE INVENTION

    0003. This invention is related to scalable high perfor mance field-effect transistors.

    BACKGROUND

    0004 Nanomaterials, such as graphene and carbon nano tubes (CNTs), hold great potential as materials for electronic components, due to remarkable properties such as extremely high charge carrier mobilities and current densities. Single atomic layer thickness provides ultimate electrostatic geom etry for scaling down field-effect transistors (FETs). FETs fabricated with graphene and CNTs have shown improved performance compared to conventional semiconductor devices of the same size, but the performance of FETs fabri cated with these carbon nanomaterials is far from their theo retical potential.

    SUMMARY

    0005. In a first aspect, fabricating a high performance self aligned field-effect transistor (FET) with a T-shaped gate electrode includes forming a source electrode and a drain electrode on a nanomaterial thin film, thereby defining a channel area between the source electrode and the drain elec trode. The nanomaterial thin film is disposed on a Substrate, and at least a portion of the nanomaterial thin film located outside the channel area is removed from the substrate. A resist is disposed over the source electrode, the drain elec trode, and the nanomaterial thin film in the channel area, and a portion of the resist between the source electrode and the drain electrode is removed, thereby forming an opening in the resist between the source electrode and the drain electrode. The resist is developed, and an electrically conductive mate rial is applied over the developed resist, thereby forming a gate electrode in the opening. The gate electrode includes a head region and a foot region. The foot region is in contact with a portion of the nanomaterial thin film in the channel area and has a length parallel to the Surface of the nanomaterial thin film shorter than the maximum length of the head region parallel to the surface of the nanomaterial thin film. The developed resist is removed, and a dielectric layer is formed on the outer Surface of the gate electrode. A metal layer is deposited over the source electrode, the drain electrode, the head region of the gate electrode, and a second portion of the nanomaterial thin film in the channel area. The head region of

    Oct. 4, 2012

    the gate electrode inhibits deposition of the metal layer over a third portion of the nanomaterial thin film proximate the foot region of the gate electrode (e.g., when the metal is deposited in a direction normal to the Surface of the nanomaterial thin film.) 0006 Implementations may include one or more of the following features. For example, the opening in the resist is a T-shaped opening, and forming the gate electrode includes forming a T-shaped gate electrode. Forming the Source elec trode and the drain electrode on the nanomaterial thin film includes depositing metal pads on the nanomaterial thin film. Removing at least the portion of the nanomaterial thin film located outside of the channel area includes etching the Sub strate. In some cases, disposing resist over the source elec trode, the drain electrode, and the nanomaterial thin film in the channel area includes forming a bilayer resist mask or a trilayer resist mask. Removing the portion of the resist between the source electrode and the drain electrode includes exposing the portion of the resist to radiation. For example, exposing the portion of the resist to radiation includes expos ing at least some of the portion of the resist to a first dose of radiation, and exposing the rest of the portion to a second dose of radiation, wherein the first dose of radiation is more ener getic than the second dose of radiation. 0007. In some cases, applying the electrically conductive material over the developed resist includes forming a unitary gate electrode in the opening. In certain cases, forming the dielectric layer on the outer surface of the gate electrode includes allowing the gate electrode to oxidize in air, and may include forming a dielectric layer between the foot region of the gate electrode and the portion of the nanomaterial thin film in contact with the foot region. Depositing the metal layer typically includes depositing the metal layer from a direction normal to the surface of the nanomaterial thin film. However, the metal layer may also be deposited from another angle. As described herein, depositing the metal layer over the source electrode, the drain electrode, the head region of the gate electrode, and a second portion of the nanomaterial thin film in the channel area includes self-aligning the Source electrode and the drain electrode (e.g., the T-gate electrode is self-aligned). Fabricating a high performance self-aligned FET with a T-shaped gate electrode may also include dispos ing the nanomaterial thin film on the Substrate before forming the Source electrode and the drain electrode on the nanom