Synthesis and Testing

Synthesis:

Once the coding of a logic is done, the code has to be synthesized to test for any kind of errors, syntactical or logical. To synthesize a logic, once the code is saved, follow the below steps:

Step1:

In Xilinx, on the left hand side of the program window, a design pane and Hierarchy pane exist. In the Hierarchy pane, all the modules in the logic are shown under the top level block. In the design pane, various options are provided to test, simulate and synthesize the logic.

To synthesize the logic, select the top level block in the hierarchy pane and run the option “Synthesize – XST” in the design pane. This will run the options available under it – “Check Syntax, View RTL, View Technology”. These options can be also be run separately for particular uses.

Once the synthesis is run, it will show any errors that exist in the logic or syntax in the “Errors” tab of the bottom pane. Otherwise, is it completely successfully, a green done mark is shown beside it.

A warnings tab is also available in the bottom pane, which will show any warnings which might be bad way of implementing something or any other possible adverse effects. This will, in many cases does not effect the systhesis.

Step2:

Once synthesis is completed successfully, the implemented logic can be viewed using the option “View RTL Schematic” option in the Synthesis menu.

The internal logic of any block can be seen by double-clicking on the particular block. The internal logic of the basic gates and system generated modules cannot be viewed.

There is one more option “View Technology Schematic” which shows the way in which a logic is implemented on programmable devices like FPGAs or CPLDs. This will not be covered in this course.

Testing:

The implemented logic can be tested by creating a test bench as shown below:

Step1: Go to “Project” tab in menu and select “New Source”.

In the pop-up window, select the option “Verilog Test Fixture” and provide a name to the test module.

Step2:

In the next window, all the modules available in the logic are shown. Select the appropriate module which needs to be tested and press finish to create the test module.

Step3:

In the test module program window, the inputs are varied according to all the scenarios that need to be tested. A sample case of some test cases is as shown below:

Step4:

Once all the test case scenarios are coded into the test module, Select the radio button option “ Simulation” in the Hierarchy Pane on the left hand side of the program window.

Select the test module created and in the design pane, expand the “ ISim Simulator” and check the syntax using the option “Behavioral Check Syntax”. Then run the option “Simulate Behavioral Model” to simulate and test the logic.

The simulated output is shown in a separate window.