Lecture 6 2014 02 14 - Electronic System - Outcome2.1 (Analysis of Biasing of the FET)

8/11/2019 Lecture 6 2014 02 14 - Electronic System - Outcome2.1 (Analysis of Biasing of the FET)

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FET ( Field Effect Transistor)

1. Unipolar device i. e. operation depends on only one type ofcharge carriers (hor e)

2. Voltage controlled Device (gate voltage controls draincurrent)

3. Very high input impedance (109-1012 )

4. Source and drain are interchangeable in most Low-frequencyapplications

5. Low Voltage Low Current Operation is possible (Low-powerconsumption)

6. Less Noisy as Compared to BJT

7. No minority carrier storage (Turn off is faster)

8. Self limiting device

9. Very small in size, occupies very small space in ICs

10. Low voltage low current operation is possible in MOSFETS

11. Zero temperature drift of out put is possiblek

Few important advantages of FET over conventional Transisto


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Types of Field Effect Transistors(The Classification)

JFET

MOSFET(IGFET)

n-Channel JFET

p-Channel JFET

n-ChannelEMOSFET

p-ChannelEMOSFET

EnhancementMOSFET

DepletionMOSFET

n-ChannelDMOSFET

p-ChannelDMOSFET

FET


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Figure: n-Channel JFET.

The Junction Field Effect Transistor (JFET)


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Gate

Drain

Source

SYMBOLS

n-channel JFET

Gate

Drain

Source

n-channel JFET

Offset-gate symbol

Gate

Dra

S

p-channel JFET


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Figure: n-Channel JFET and Biasing Circuit.

Biasing the JFET


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Figure: The nonconductive depletion region becomes broader with increased reverse bias.

(Note:The two gate regions of each FET are connected to each other.)

Operation of JFET at Various Gate Bias Potentials


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P P+

-

+

-

+

-

N

N

Operation of a JFET

Gate

Drain

Source

O D i (V I ) Ch i i f JFET


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Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.

Non-saturation (Ohmic) Region:

The drain current is given by

2

2

2

2

DS

DSPGS

P

DSS

DS

VVVV

V

II

2

2 PGS

P

DSS

DSVV

V

I

I

2

1and

P

GS

DSSDS V

V

II

Where,IDSSis the short circuit drain current, VPis the pinch off voltage

Output or Drain (VD-ID) Characteristics of n-JFET

Saturation (or Pinchoff) Region:

PGSDSVVV

PGSDSVVV


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Figure: n-Channel FET for vGS = 0.

Simple Operation and Break down of n-Channel JFET


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Figure: If vDGexceeds the breakdown voltage VB, drain current increases rapidly.

Break Down Region

N-Channel JFET Characteristics and Breakdown


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Figure: Typical drain characteristics of an n-channel JFET.

VD-IDCharacteristics of EMOS FET

Saturation or Pinch off

Reg.

Locus of pts where PGSDS VVV


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Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

2

1

P

GS

DSSDS V

V

II

IDSS

VGS (off)=VP

Transfer (Mutual) Characteristics of n-Channel JFET


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JFET Transfer CurveThis graph shows the value of IDfor a givenvalue of VGS


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Biasing Circuits used for JFET

Fixed bias circuit Self bias circuit

Potential Divider bias circuit

JFET (n channel) Biasing


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JFET (n-channel) BiasingCircuits

2

1

P

GS

DSSDS V

V

II

GSGSGGGG FixedVVRIV

DDSDDDS

P

GS

DSSDS

RIVV

V

VII

and

1

2

S

GS

DS

SDSGS

R

VI

RIV

0

For Self Bias Circuit

For Fixed Bias Circuit

Applying KVL to gate circuit we g

and

Where, Vp=VGS-off& IDSSis Short ckt


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JFET BiasingCircuits Count

or Fixed Bias Ckt.


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JFET Self (or Source) Bias Circuit

2

1and

P

GS

DSSDS V

V

II

S

GS

P

GS

DSS R

V

V

V

I

2

1

21

2

P

GS

P

GS

DSS R

V

V

V

V

V

I

This quadratic equation can be solved for VGS& I


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The Potential (Voltage) Divider Bias

01

2

S

GSG

P

GS

DSS R

VV

V

V

I

DSGS

IVgivesequationquadraticthisSolving and

Lecture 6 2014 02 14 - Electronic System - Outcome2.1 (Analysis of Biasing of the FET)

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Transcript of Lecture 6 2014 02 14 - Electronic System - Outcome2.1 (Analysis of Biasing of the FET)