Electronic Devices

42

Chapter 6: Field-Effect Transistors (FETs)

The Field-Effect Transistor

The field-effect transistor (FET) is a semiconductor device, which depends for its

operation on the control of current by an electric field. Today FETs are the most widely

used components in integrated circuits. There are two of field effect transistors:

1. JFET (Junction Field-Effect Transistor).

2. MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

The FET has several advantages over conventional transistor.

1. In a conventional transistor, the operation depends upon the flow of majority and

minority carriers. That is why it is called bipolar transistor. In FET the operation

depends upon the flow of majority carriers only. It is called unipolar device.

2. The input to conventional transistor amplifier involves a forward biased PN

junction with its inherently low dynamic impedance. The input to FET involves a

reverse biased PN junction hence the high input impedance of the order of M ohm.

3. It is less noisy than a bipolar transistor.

4. It exhibits no offset voltage at zero drain current.

5. It has thermal stability.

6. It is relatively immune to radiation.

The main disadvantage is its relatively small gain bandwidth product in comparison with

conventional transistor.

Junction Field-Effect Transistor

The JFET is a type of FET that operates with a reverse-biased pn junction to control

current in a channel. Depending on their structure, JFETs fall into either of two

categories, n channel or p channel.

Figure 1: A representation of the basic structure of the two types of JFET.

Figure 1(a) shows the basic structure of an n-channel JFET. Wire leads are connected

to each end of the n-channel; the drain is at the upper end (analogous to the collector of

Electronic Devices

43

a BJT), and the source is at the lower end. Two p-type regions are diffused in the n-type

material to form a channel, and both p-type regions are connected to the gate (analogous

to the base of a BJT) lead. For simplicity, the gate lead is shown connected to only one

of the p regions.

Operation of JFET

To illustrate the operation of a JFET, Figure 2 shows dc bias voltages applied to an n-

channel device, when the drain is positive with respect to the source and there is no gate-

source voltage, there is current in the channel. When a negative gate voltage is applied

to the FET, the electric field causes the channel to narrow, which in turn causes current

to decrease.

Figure 2: A biased n-channel JFET.

The symbol for an n-channel JFET is shown, along with the proper polarities of the

applied dc voltages. For an n-channel device, the gate is always operated with a negative

(or zero) voltage with respect to the source.

Figure 3: JFET schematic symbols.

JFET characteristics and parameters

There are three regions in the characteristic curve for a JFET as illustrated for the case

when VGS=0V. Between A and B is the Ohmic region, where current and voltage are

related by Ohm’s law. From B to C is the active (constant-current) region where current

is essentially independent of VDS. Beyond C is the breakdown region. Operation here

can damage the FET.

Electronic Devices

44

Figure 4: The drain characteristic curve of a JFET for VGS=0.

When VGS is set to different values, the relationship between VDS and ID develops a

family of characteristic curves for the device. An n-channel characteristic is illustrated

Figure 5. Notice that Vp is positive and has the same magnitude as VGS(off).

Figure 5: Family of drain characteristic curves.

JFET Universal Transfer Characteristic

A plot of VGS to ID is called the transfer or transconductance curve. The transfer curve is

a is a plot of the output current (ID) to the input voltage (VGS).

Figure 6: JFET universal transfer characteristic curve (n-channel).

Electronic Devices

45

The transfer curve is based on the equation

ID = IDSS (1 −VGS

VGS(off))

2

By substitution, you can find other points on the curve for plotting the universal curve.

Figure 7: gm varies depending on the bias point (VGS).

The transconductance (transfer conductance), gm, is the ratio of a change in output

current (ΔID) to a change in the input voltage (ΔVGS). This definition is

gm =∆𝐼𝐷

∆𝑉𝐺𝑆

The following approximate formula is useful for calculating gm if you know gm0.

gm = gm0(1 −

VGS

VGS(off))

The value of gm0 can be found from

gm0 =2IDSS

|VGS(off)|

Because the slope changes at every point along the curve, the transconductance is not

constant, but depends on where it is measured.

The input resistance of a JFET is given by:

RIN = |VGS

IGSS|

where IGSS is the current into the reverse biased gate. JFETs have very high input

resistance, but it drops when the temperature increases.

Example: A certain JFET has an IGSS of -2nA for VGS=-20V. Determine the input

resistance.

Solution: RIN = |VGS

IGSS| =

20V

2nA= 10GΩ

Electronic Devices

46

JFET Biasing

Just as with the BJT, the purpose of biasing is to select the proper dc gate-to-source

voltage to establish a desired value of drain current and, thus, a proper Q-point. Three

types of bias are self-bias, voltage-divider bias, and current-source bias.

Self-bias

Self-bias is simple and effective, so it is the most common biasing method for JFETs.

The JFET must be operated such that the gate-source junction is always reverse-biased.

This condition requires a negative VGS for an n-channel JFET and a positive VGS for a p-

channel JFET. This can be achieved using the self-bias arrangements shown in Figure 8.

The gate resistor (RG) does not affect the bias because it has essentially no voltage drop

across it; and therefore the gate remains at 0V. RG is necessary only to force the gate to

be at 0V and to isolate an ac signal from ground in amplifier applications.

Figure 8: Self-biased JFETs (IS= ID in all FETs).

For the n-channel JFET in Figure 8(a), IS produces a voltage drop across RS and makes

the source positive with respect to ground. Since IS=ID and VG=0, then VS=IDRS.

The gate-to-source voltage is

VGS=VG-VS = 0 - IDRS= - IDRS

Thus, VGS = -IDRS

For the p-channel JFET shown in Figure 8(b), the current through RS produces a

negative voltage at the source, making the gate positive with respect to the source.

Therefore, since IS =ID,

VGS = +IDRS

Keep in mind that analysis of the p-channel JFET is the same except for opposite-

polarity voltages. The drain voltage with respect to ground is determined as follows:

VD = VDD - IDRD

Since VS=IDRS, the drain-to-source voltage is

VDS =VD-VS =VDD - ID(RD+RS)

Electronic Devices

47

Example: For the JFET in the following Figure, the drain current (ID) is approximately

5 mA. Determine VDS and VGS.

Solution: VS=IDRS= (5mA)(220Ω)=1.1V

VD = VDD-IDRD=15V-(5mA)(1.0kΩ)

=15V - 5V=10V

Therefore, VDS= VD - VS = 10 V - 1.1 V = 8.9 V

Since VG=0 V,

VGS = VG - VS = 0 V - 1.1 V = -1.1 V

Voltage-Divider Bias

Voltage-divider biasing is a combination of a voltage-divider and a source resistor to

keep the source more positive than the gate. VG is set by the voltage-divider and is

independent of VS. VS must be larger than VG in order to maintain the gate at a negative

voltage with respect to the source. Voltage-divider bias helps stabilize the bias for

variations between transistors.

Figure 9: An n-channel JFET with voltage-divider bias (IS=ID).

Current-Source Bias

An even more stable form of bias is current-source bias. The current-source can be

either a BJT or another FET. With current-source biasing, the drain current is essentially

independent of VGS.

Figure 10: Current-source bias.

Electronic Devices

48

In this circuit, Q2 serves as a current source for Q1. An advantage to this particular

circuit is that the output can be adjusted (using RS2) for 0 V DC.

Example: A current-source bias circuit has the following values: VDD= 9V, VEE=-6V,

and RG=10MΩ. To produce a 10 mA drain current and a 5V drain voltage,

determine the values of RE and RD.

Solution:

RE =VEE

ID=

6V

10mA= 600Ω

RD =VDD − VD

ID=

9V − 5V

10mA= 400Ω

JFET Ohmic Region

As described before, the ohmic region is between the origin and the active region. A

JFET operated in this region can act as a variable resistor. Data from an actual FET is

shown. The slopes (which represent conductance) of successive VGS lines are different in

the ohmic region. JFETs are often biased in the ohmic region for use as a voltage

controlled variable resistor. The control voltage is VGS, and it determines the resistance

by varying the Q-point.

Figure 11: The ohmic region is the shaded area.

THE MOSFET

The MOSFET (metal oxide semiconductor field-effect transistor) is another category

of field-effect transistor. The n-channel MOSFET (Figure 12) has only a single p region

(called the substrate), one side of which acts as a conducting channel. A metallic gate is

separated from the conducting channel by an insulating metal oxide (usually SiO2). The

p-channel MOSFET, formed by interchanging p and n semiconductor materials, is

described by complementary voltages and currents. The MOSFET, different from the

JFET, has no pn junction structure. The two basic types of MOSFETs are enhancement

and depletion. Because of the insulated gate, MOSFETs are sometimes called IGFETs.

Electronic Devices

49

Enhancement MOSFET (E-MOSFET)

The E-MOSFET operates only in the enhancement mode and has no depletion mode. It

differs in construction from the D-MOSFET, in that it has no structural channel, and the

substrate extends completely to the SiO2 layer as shown in Figure 12(a). For an n-

channel device, A channel is induced by applying a VGS greater than the threshold value,

VGS(th), by creating a thin layer of negative charges in the substrate region adjacent to the

SiO2 layer, as shown in Figure 12(b). The positive gate voltage attracts electron from the

substrate to the region along the insulating layer. If the gate is made sufficiently positive,

enough electrons will be pulled up from the substrate, an n-channel starts to form. The

channel does not form uniformly but rather begins to form on the drain side. As the gate

voltage increases, the channel length also increases. Finally, the gate voltage increases to

the point (VGS(th)) where the channel reaches the source, and conduction begins. The

conductivity of the channel is enhanced by increasing the VGS

Figure 12: The basic E-MOSFET construction and operation (n-channel).

E-MOSFET Transfer Characteristic

The transfer curve for a MOSFET is has the same parabolic shape as the JFET but the

position is shifted along the x-axis. The transfer curve for p-channel and n-channel E-

MOSFET is entirely in the first quadrant as shown. The curve is on the enhancement

region, ID = 0A when VGS = 0V and ID = 0A until VGS reaches the threshold value.

Figure 13: E-MOSFET general transfer characteristic curves.

Electronic Devices

50

The curve starts at VGS(th), which is a nonzero voltage that is required to have channel

conduction. The equation for the drain current is

ID= K(VGS-VGS(th))2 where K is constant is given by: 𝐊 =

𝐈𝐃(𝐨𝐧)

(𝐕𝐆𝐒−𝐕𝐆𝐒(𝐭𝐡))𝟐

Depletion MOSFET (D-MOSFET)

The D-MOSFET has a channel that can is controlled by the gate voltage. For an n-

channel type, a negative voltage depletes the channel; and a positive voltage enhances

the channel. The D-MOSFET can be operated in either of two modes—the depletion

mode or the enhancement mode, depending on the gate voltage, and is sometimes called

a depletion/enhancement MOSFET. The n-channel MOSFET operates in the depletion

mode when a negative gate-to-source voltage (VGS) is applied and in the enhancement

mode when a positive gate-to-source voltage (VGS) is applied. D-MOSFET are generally

operated in the depletion mode.

Figure 14: The basic structure of D-MOSFETs.

Depletion Mode: with a negative VGS, the electric field produces in the channel drives

electrons away from a portion of the channel near the SiO2 layer. This portion is

depleted of carriers and the channel width is effectively narrowed. The channel

conductivity is decreased. Further increasing the negative voltage at the gate pushes

even more electrons away, narrowing the channel and decreasing the current (Figure 15)

Figure 15: Operation of n-channel D-MOSFET.

Electronic Devices

51

Enhancement Mode: VGS can be made positive without any concern for the

consequences of forward biasing a junction. With a positive VGG, more conduction

electrons are attracted into the channel. The channel conductivity is enhanced

(increased), as shown in Figure 15 (b).

D-MOSFET Transfer Characteristic

Recall that the D-MOSFET can be operated in either mode. This is indicated on the

general transfer characteristic curves in Figure 16 for both n-channel and p-channel

MOSFETs. For the region VGS < 0V operation is in depletion mode, in the region VGS >

0V operation in enhancement mode. As with the JFET, The point on the curves where

VGS=0 corresponds to IDSS. The equation for drain current is

ID = IDSS (1 −VGS

VGS(off))

2

Figure 16: D-MOSFET general transfer characteristic curves.

MOSFET Symbols

The symbols for the n-channel and p-channel MOSFETs are shown in Figure 17. Notice

the broken line representing the E-MOSFET that has an induced channel. An inward-

pointing substrate arrow is for n-channel, and an outward-pointing arrow is for p-

channel.

Figure 17: (a) E-MOSFET schematic symbols (b) D-MOSFET schematic symbols.

Electronic Devices

52

MOSFET Biasing E-MOSFETs can be biased using bias methods like the BJT methods studied earlier.

Voltage-divider bias and drain-feedback bias are illustrated for n-channel devices.

Biasing

Figure 18: Common E-MOSFET biasing arrangements.

The simplest way to bias a D-MOSFET is with zero bias. This works because the

device can operate in either depletion or enhancement mode, so the gate can go above or

below 0 V.

Figure 19: A zero-biased D-MOSFET.

The drain-to-source voltage is expressed as follows:

VDS = VDD - IDSSRD

The purpose of RG is to accommodate an ac signal input by isolating it from ground, as

shown in Figure 19(b). Since there is no dc gate current, RG does not affect the zero

gate-to-source bias.

Example: The datasheet for a 2N7002 E-MOSFET gives ID(on)=500 mA (minimum) at

VGS=10 V and VGS(th)=1 V. Determine the drain current for VGS = 5V.

Solution: First, solve for K

Electronic Devices

53

K =ID(on)

(VGS − VGS(th))2=

500mA

(10V − 1V)2= 6.17mA/V2

Next, using the value of K, calculate ID for VGS=5 V.

ID= K(VGS-VGS(th))2=(6.17mA/V2)(5V-1V)2=98.7mA

Example: For a certain D-MOSFET, IDSS=10 mA and VGS(off) = -8V.

(a) Is this an n-channel or a p-channel?

(b) Calculate ID at VGS = -3 V.

(c) Calculate ID at VGS =+3 V.

Solution:

(a) The device has a negative VGS(off); therefore, it is an n-channel MOSFET.

(b) ID = IDSS (1 −VGS

VGS(off))

2

= 10 mA (1 −−3V

−8V)

2= 𝟑. 𝟗𝟏𝐦𝐀

(c) ID = 10 mA (1 −+3V

−8V)

2= 𝟏𝟖. 𝟗𝐦𝐀

JFET vs MOSFET

1. The gate and channel in a JFET are

separated by a pn junction

1. The gate of a MOSFET is insulated

from the channel by a SiO2 layer

2. The channel width is controlled by the

size of the depletion region of a pn

junction

2. The channel width is controlled by

the action of the electric field

3. Operates in depletion mode 3. Operates in depletion and

enhancement modes