FPGA basics and Nios II Processor Intro

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FPGA basics and Nios II Processor Intro. Week 2 Dr. Kimberly E. Newman Hybrid Embedded Systems. Material Covered. Textbook Chapter 5 Nios II Processor Reference Handbook Chapter 1 & 2 Homework Assignment #1 is available. Assignment is due next week before class. - PowerPoint PPT Presentation

Transcript of FPGA basics and Nios II Processor Intro

Nios II

FPGA basics and Nios II Processor IntroWeek 2Dr. Kimberly E. NewmanHybrid Embedded SystemsMaterial CoveredTextbook Chapter 5Nios II Processor Reference HandbookChapter 1 & 2Homework Assignment #1 is available. Assignment is due next week before class. Submit through Blackboard since there will be code involved that needs to be verified.Turn in signed verification sheets for Lab #1 to Dan for recording in Blackboard.Lab #2 will cover the LCD peripheral and interfacing to external memory (SDRAM).Field Programmable DevicesThe fundamental piece of a configurable logic device is a programmable macrocell. Figure 5.20 on page 213 shows an overview of the components in a simple configuration.Each macrocell has a programmable register that an be either a D, T, JK and SR flip-flop with individual clear and clock control. Input to the macrocell is configured through the logic array. Eight product terms form a programmable AND array that feeds an OR gate for combinatorial logic implementation. And XOR gate is provided to allow for inversion of the output.Routing and use of clocks and output signals are also controlled through configuration.

Complex Programmable Logic Devices (CPLD)Multiple PLDs are placed in a single device as shown on page 214 in fig 5.21.Typically the CPLD has an EEPROM included so that the configuration is not lost when power is removed. Look at the Data Sheet for the MAX II http://www.altera.com/literature/hb/max2/max2_mii51002.pdf

CPLD architecture (from the data sheet on the last slide)

Logic Array Blocks (LAB)

Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, a look-up table (LUT) chain, and register chain connection lines.There are 26 possible unique inputs into a LAB with an additional 10 local feedback input lines fed by LE outputs in the same LABCPLD Logic Element

Field Programmable Gate Arrays(textbook section 5.4)An FPGA is more flexible than a CPLD.The logic blocks in an FPGA are connected by wiring channels that are much smaller than those of a CPLD.There are many more logic blocks available in the FPGA.Memory blocks are also available that can be configured as general purpose RAM.Flex 10kSRAM-based that can be programmed through the JTAG interfaceA serial PROM can be used to provide configuration information on power upThe EPF10K70 has a total of 70,000 typical gates that include logic and RAM.The entire array contains 468 Logic Array Blocks (LABs) arranged into 52 columns and 9 rows.Alteras Cyclone FPGA (pg 223 )This processor is based on a 1.5 V, 0.13m all-layer copper SRAM process. Densities can reach up to 20,060 logic elements and up to 288 Kbits of RAM. The devices supports the creation of phase-lock-loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements.We are using the EP2c35F672C6N with the DE2 board.Nios II Processor System basics (info from the PRH)General purpose RISC processor coreFull 32-bit instruction set, data path, and address space32 general-purpose registers32 external interrupt sourcesALU supports:Single-instruction 32x32 multiply and divide producing a 32-bit result (Dedicated instructions for computing 64-bit and 128-bit products of multiplication)Floating-point instructions for single-precision floating-point operationsSingle Instruction barrel shifterI/O capabilities:Access to on-chip peripheralsInterfaces to off-chip memories and peripherals

Nios II Processor System basicsDebugging capabilities:Hardware-assisted debug module enabling processor start, stop, step, and trace under integrated development environment (IDE) controlSignalTap II Embedded Logic AnalyzerOptional featuresMemory Management Unit (MMU)Memory Protection Unit (MPU)SpeedPerformance up to 250 DMIPSExample of a Nios II processor system

Customizing Nios II Processor DesignsPin locations on the FPGA layout can be moved to make traces smaller for external access to the processor.Glue logic on the FPGA can be implemented. On the larger Altera devices the Nios II processor system consumes on the order of 5% of the on board resources.Additional cores and peripherals can be included in a design to enhance the system performanceProcessor ArchitectureNios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions.A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document.The processor core does not include peripherals or the connection logic to the outside world. Nios II Processor Core Block DiagramFunctional Units:Register fileArithmetic logic unit (ALU)Interface to custom instruction logicException controllerInterrupt controllerInstruction busData busMemory management unit (MMU)Memory protection unit (MPU)Instruction and data cache memoriesTightly-coupled memory interfaces for instructions and dataJTAG debug module

Register FileNios II architecture supports a flat register fileThere are thirty two 32-bit general-purpose integer registersUp to thirty two 32-bit control registers with supervisor and user modes to allow system code to protect control registers from errant applications.Allows for the future additional of floating-point registersArithmetic Logic UnitOperates on data stored in general-purpose registersOperations take one or two inputs from registers and stores a result back in a register.CategoryDetailsArithmeticThe ALU supports addition, subtraction, multiplication, and division on signed and unsigned operationsRelationalThe ALU supports the equal, not-equal, greater-than-or-equal, and less-than relational operations (==, !=, >=,