FPGA basics and Nios II Processor Intro
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Transcript of FPGA basics and Nios II Processor Intro
FPGA basics and Nios II Processor Intro
Week 2Dr. Kimberly E. Newman
Hybrid Embedded Systems
Material CoveredTextbook Chapter 5Nios II Processor Reference Handbook
Chapter 1 & 2Homework Assignment #1 is available.
Assignment is due next week before class. Submit through Blackboard since there will be code
involved that needs to be verified.Turn in signed verification sheets for Lab #1 to
Dan for recording in Blackboard.Lab #2 will cover the LCD peripheral and
interfacing to external memory (SDRAM).
Field Programmable DevicesThe fundamental piece of a configurable logic device is a
programmable macrocell. Figure 5.20 on page 213 shows an overview of the
components in a simple configuration.Each macrocell has a programmable register that an be
either a D, T, JK and SR flip-flop with individual clear and clock control.
Input to the macrocell is configured through the logic array. Eight product terms form a programmable AND array that
feeds an OR gate for combinatorial logic implementation. And XOR gate is provided to allow for inversion of the output.
Routing and use of clocks and output signals are also controlled through configuration.
Complex Programmable Logic Devices (CPLD)Multiple PLDs are placed in a single device as shown on page
214 in fig 5.21.Typically the CPLD has an EEPROM included so that the
configuration is not lost when power is removed. Look at the Data Sheet for the MAX II
http://www.altera.com/literature/hb/max2/max2_mii51002.pdf
CPLD architecture (from the data sheet on the last slide)
Logic Array Blocks (LAB) Each LAB consists of 10 LEs, LE carry chains, LAB control signals,
a local interconnect, a look-up table (LUT) chain, and register chain connection lines.
There are 26 possible unique inputs into a LAB with an additional 10 local feedback input lines fed by LE outputs in the same LAB
CPLD Logic Element
Field Programmable Gate Arrays(textbook section 5.4)An FPGA is more flexible than a CPLD.The logic blocks in an FPGA are connected by
wiring channels that are much smaller than those of a CPLD.
There are many more logic blocks available in the FPGA.
Memory blocks are also available that can be configured as general purpose RAM.
Flex 10kSRAM-based that can be programmed
through the JTAG interfaceA serial PROM can be used to provide
configuration information on power upThe EPF10K70 has a total of 70,000 typical
gates that include logic and RAM.The entire array contains 468 Logic Array
Blocks (LABs) arranged into 52 columns and 9 rows.
Altera’s Cyclone FPGA (pg 223 )This processor is based on a 1.5 V, 0.13µm
all-layer copper SRAM process. Densities can reach up to 20,060 logic
elements and up to 288 Kbits of RAM. The devices supports the creation of phase-
lock-loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements.
We are using the EP2c35F672C6N with the DE2 board.
Nios II Processor System basics (info from the PRH)General purpose RISC processor core
Full 32-bit instruction set, data path, and address space32 general-purpose registers32 external interrupt sourcesALU supports:
Single-instruction 32x32 multiply and divide producing a 32-bit result (Dedicated instructions for computing 64-bit and 128-bit products of multiplication)
Floating-point instructions for single-precision floating-point operations
Single Instruction barrel shifterI/O capabilities:
Access to on-chip peripherals Interfaces to off-chip memories and peripherals
Nios II Processor System basicsDebugging capabilities:
Hardware-assisted debug module enabling processor start, stop, step, and trace under integrated development environment (IDE) control
SignalTap II Embedded Logic AnalyzerOptional features
Memory Management Unit (MMU)Memory Protection Unit (MPU)
SpeedPerformance up to 250 DMIPS
Example of a Nios II processor system
Customizing Nios II Processor Designs
Pin locations on the FPGA layout can be moved to make traces smaller for external access to the processor.
Glue logic on the FPGA can be implemented. On the larger Altera devices the Nios II
processor system consumes on the order of 5% of the on board resources.
Additional cores and peripherals can be included in a design to enhance the system performance
Processor ArchitectureNios II architecture describes an instruction set
architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions.
A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document.
The processor core does not include peripherals or the connection logic to the outside world.
Nios II Processor Core Block Diagram Functional Units:
Register file Arithmetic logic unit (ALU) Interface to custom
instruction logic Exception controller Interrupt controller Instruction bus Data bus Memory management unit
(MMU) Memory protection unit
(MPU) Instruction and data cache
memories Tightly-coupled memory
interfaces for instructions and data
JTAG debug module
Register FileNios II architecture supports a flat register
fileThere are thirty two 32-bit general-purpose
integer registersUp to thirty two 32-bit control registers with
supervisor and user modes to allow system code to protect control registers from errant applications.
Allows for the future additional of floating-point registers
Arithmetic Logic UnitOperates on data stored in general-purpose registersOperations take one or two inputs from registers and
stores a result back in a register.Category DetailsArithmetic The ALU supports addition, subtraction,
multiplication, and division on signed and unsigned operations
Relational The ALU supports the equal, not-equal, greater-than-or-equal, and less-than relational operations (==, !=, >=, <) on signed and unsigned operands.
Logical The ALU supports AND, OR, NOR, and XOR logical operations.
Shift and Rotate
The ALU supports shift and rotate operations, and can shift/rotate data by 0 to 31 bit positions per instruction. The ALU supports arithmetic shift right and logical shift right/left. The ALU supports rotate left/right.
InstructionsUnimplemented Instructions
Some core implementations do not provide support for the entire instruction set.
An exception is generated so that the instruction can be emulated in software.
To determine a list of potentially unimplemented instructions refer to the Programming Model chapter of the Nios II Processor Reference Handbook
Custom Instructions User-defined custom instructions are allowed. The ALU
connects directly to the new instruction logic so that use and access are the same as the native instructions.
For further information refer to the Nios II Custom Instruction User Guide
Floating Point operations Single precision floating
point is supported as specified in the IEEE Std 754-1985
TradeoffsFloating point operations do require many
more elements in the FPGA.Designers should be aware of tradeoffs in the
HW/SW implementation.Speed vs. resource usage should be evaluated
for a given application.
Motivational Videos:Hybrid embedded systems are growing in need and facilitate the
grand challenges of tomorrow.Transportation, environmental management and health care
applications are just a few examples of where better designs are needed.
Autonomous VehiclesBig Belly Robot Garbage BinRobonurse