Nios Embedded Processor Hardware Tutorial

Nios™ Embedded Processor

Hardware Tutorial

Altera Corporation101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com

Nios Embedded Processor Hardware TutorialVersion 1.0November 2000

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Table of Contents

Tutorial Overview ............................................................................................1Tutorial Files.......................................................................................2

Design Entry.....................................................................................................3Create a Quartus Project ..........................................................................3

1. Start the Quartus Software ............................................................32. Create a Project...............................................................................3

Create a Nios System Module..................................................................51. Create a New Block Design File.....................................................52. Create the Nios Embedded Processor ..........................................63. Create & Memory Map System Peripherals .................................8

Create the boot_monitor_rom System Peripheral ................9Create the ext_flash & ext_ram System Peripherals ........10Create the button_pio, lcd_pio, led_pio & seven_seg_pio System Peripherals......................................14Create the uart1 System Peripheral .......................................17Create the timer1 System Peripheral.....................................19

4. Configure System Module Settings.............................................205. Synthesize the Design with LeonardoSpectrum Software........216. Enter Input, Output, Bidirectional & Primitive Symbols ..........237. Name the Pins...............................................................................268. Connect the Pins ..........................................................................29

Compilation ...................................................................................................33Create Compiler Settings .......................................................................33

1. View the Compiler General Settings ...........................................332. Specify the Device Family & Device............................................34

Assign Signals to Device Pins.................................................................361. Assign Pins with a Tcl Script........................................................362. Verify the Pin Assignments..........................................................37

Specify Device, Programming & EDA Tool Settings ............................381. Reserve Unused Pins....................................................................392. Specify Optional Programming Files..........................................393. Specify EDA Tool Settings............................................................40

Compile the Design................................................................................40Programming .................................................................................................43

Configure an APEX Device.....................................................................43Download the Design to Flash Memory ...............................................46

1. Start the bash Shell.......................................................................472. Run the Sample hello.srec Test Program ...................................483. Download the Configuration Data to Flash Memory................49

Restore Factory Default Configuration.................................................52Contacting Altera ...........................................................................................54

Technical Support............................................................................54

iii

Nios Embedded Processor Hardware Tutorial

Product Information........................................................................ 54

iv

Tutorial Overview

This tutorial introduces you to the Nios™ embedded processor. It shows you how to use the Quartus™ software to create and process your own Nios embedded processor design that interfaces with components provided on the Nios development board.

The sections in this tutorial guide you through the steps necessary to create, compile, and download a 32-bit Nios embedded processor design, called nios_system_module. A Nios system module is composed of a Nios embedded processor and its associated system peripherals and interconnections.

After you create the nios_system_module design, you can download it into an Altera® APEX™ device. When you download the design to the device, the system module pins are logically connected to pins on the APEX device. The external physical pins on the APEX device are in turn connected to other hardware components on the Nios development board, allowing the Nios embedded processor to interface with RAM, flash memory, LEDs, LCDs, switches, and buttons.

The tutorial is divided into the following three sections:

� “Design Entry” on page 3 teaches you how to create the Nios system module in a Block Design File (.bdf) using the MegaWizard Plug-In Manager™ - Nios System Builder. This section also teaches you how to connect the system module ports to pins in the APEX device.

� “Compilation” on page 33 teaches you how to compile the Nios embedded processor system module using Compiler settings, pin assignments, and EDA tool settings to control compilation processing.

� “Programming” on page 43 teaches you how to use the Quartus Programmer and the ByteBlasterMV™ cable to download the design to an APEX device. It also teaches you how to download the design to a flash memory device provided on the Nios development board.

Altera Corporation 1


1 This tutorial assumes that you have completed the following prerequisite items:

� Installed the following software on a PC:– Quartus software version 2000.05, with support for

the APEX EP20K200E device, as described in the Quartus Installation and Licensing for PCs manual

– Exemplar Logic LeonardoSpectrum software version 1999.1j licensed for Verilog HDL. If you have a VHDL license, replace references to Verilog HDL with VHDL in this tutorial.

– Nios embedded processor– GNUPro® Nios software development tools

� Set up the Nios development board, as described in the Nios Embedded Processor Quick Start Guide

� Installed the ByteBlaster driver, as described in the Quartus Installation and Licensing for PCs manual

� Learned the basic features and operation of the Quartus software, as described in the Quartus Tutorial manual.

Tutorial Files

This tutorial assumes that you create and save your files in a working directory on the d: drive on your computer. If your working directory is on another drive, substitute the appropriate drive name.

The Nios embedded processor installation creates the following directories in the \altera\excalibur directory by default:

Directory Name: Description:

\nios_documentation Contains documentation for the Nios embedded processor, Nios development board, and GNUPro Toolkit.

\nios_sample_designs Contains Nios sample designs, including the \reference_design_32_bit\reference_design project that loads on the Nios development board automatically upon power up. The nios_system_module design you create in this tutorial is based on the reference_design.

2 Altera Corporation


Design Entry

The following tutorial sections guide you through the steps needed to create the nios_system_module project, and then explain how to create a top-level BDF that contains the Nios system module. You create and instantiate the Nios system module using the MegaWizard Plug-In Manager.

Create a Quartus Project

1. Start the Quartus Software

In this section, you start the Quartus software and begin creating your project.

To start the Quartus software, perform one of the following steps:

v Choose Programs > Altera > Quartus 2000.05 (Windows Start menu).

or

v Type quartusr at the command prompt. The Quartus window opens.

2. Create a Project

To create a new project, follow these steps:

1. Choose New (File menu). The Design Files tab of the New dialog box appears automatically.

2. Click the Project Files tab.



3. In the Project Files tab, select Project File.

4. Click OK. The New Project dialog box appears.

5. To specify the project directory, type d:\Altera\Excalibur\nios_tutorial in the Project directory box.

6. In the Project name box, type nios_system_module as the name of the project.

7. In the Top-level design entity box, make sure nios_system_module is specified as the name of the top-level design entity of the project. See the following illustration:

8. Click OK. When the Quartus software asks you if you want to create the new directory, click Yes.

The project is now created. The top-level design entity name appears in the Hierarchies tab of the Project Navigator window. See the following illustration:

Top-level design entity name



Create a Nios System Module

This section describes how to create the top-level BDF that contains a Nios system module. After creating a design file, you can use the MegaWizard Plug-In Manager to create the Nios embedded processor and configure system peripherals. Next, you create the connections from the Nios embedded processor and system peripherals to hardware components on the Nios development board.

This section includes the following steps:

1. Create a new Block Design File (.bdf).2. Create the Nios embedded processor.3. Create & memory map system peripherals.4. Configure system module settings.5. Synthesize the design with LeonardoSpectrum software.6. Enter input, output, bidirectional & primitive symbols.7. Name the pins.8. Connect the pins.

1. Create a New Block Design File

In this step you create a new BDF called nios_system_module.bdf. This file is the top-level design entity of the nios_system_module project.

To create a new BDF, follow these steps:

1. Choose New (File menu). The Design Files tab of the New dialog box appears automatically.

2. In the Design Files tab, select Block Diagram/Schematic File.

3. Click OK. A new Block Editor window appears.

4. Choose Save As (File menu).

5. Select the folder where you want to save the BDF. The Save As dialog box should automatically display the project directory name, d:\Altera\Excalibur\nios_tutorial, as the directory for saving the file.



6. In the File name box, type nios_system_module as the name of the BDF, if necessary.

7. Make sure Add file to current project is turned on.

8. Click Save. The file is saved and added to the project.

2. Create the Nios Embedded Processor

The MegaWizard Plug-In Manager allows you to create (or modify) design files that contain custom variations of megafunctions, such as the Nios system module. A complete Nios system module contains a Nios embedded processor and its associated system peripherals. The MegaWizard Plug-In Manager - Nios System Builder helps you specify options for the system module easily. The wizard prompts you about the values you want to set for parameters and which optional ports and peripherals you want to use. Once the wizard generates the Nios system module, you can instantiate it in the design file.

Follow these steps to create the Nios embedded processor in the nios_system_module.bdf file:

1. Click the Selection Tool button on the toolbar. The Block Editor toolbar has the following default toolbar buttons:

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears.

Selection Tool Text Tool

Symbol Tool Block Tool

Orthogonal Node Tool Orthogonal Bus ToolZoom Tool Full Screen

Find

Flip VerticalFlip Horizontal

Rotate Left 90

Rectangle Tool Oval Tool

Line Tool Arc Tool



3. Click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager is displayed, as shown in the following illustration:

4. Under Which action do you want to perform?, select Create a new custom megafunction variation and click Next. MegaWizard Plug-In Manager page 2a appears.

5. In the Available Megafunctions list, make sure Altera Excalibur Nios(tm) is selected.

6. Specify the following responses to the remaining wizard prompts in MegaWizard Plug-In Manager page 2a:

7. Click Next. MegaWizard Plug-In Manager - Nios System Builder page 3 appears.

8. In the Name box, leave the default name for the Nios embedded processor, nios32_cpu.

9. To specify options for the Nios embedded processor, click Next. MegaWizard Plug-In Manager - Nios page 1 appears.

Wizard Prompt: Response:

Which type of output file do you want to create?

Select Verilog HDL

What name do you want for the output file?

Type d:\Altera\Excalibur\nios_tutorial\nios32.v



10. To specify that you want to use a 32-bit Nios embedded processor, select Nios-32.

11. Click Next. MegaWizard Plug-In Manager - Nios page 2 appears.

12. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - Nios pages 2 through 4:

13. In MegaWizard Plug-In Manager - Nios page 4, click Next. MegaWizard Plug-In Manager - Nios page 5 appears.

14. To generate the Nios embedded processor with the options you specified, click Finish. MegaWizard Plug-In Manager - Nios System Builder page 4 appears.

3. Create & Memory Map System Peripherals

The Nios system peripherals allow the Nios embedded processor to connect and communicate with internal logic in the APEX device, or external hardware on the Nios development board. You can use the MegaWizard Plug-In Manager - Nios System Builder to specify the name, type, alignment, memory map addresses, and interrupts of the system peripherals for your Nios system module.

1 These memory mappings ensure that the nios_system_module design functions correctly on the Nios development board, and allow you to run the software examples provided in the \Cygwin\usr\altera\excalibur\nios-sdk\examples directory.


Size of Address Bus Make sure 21 is selectedRegister File Size Make sure 256 is selectedInternal Shifter Speed Make sure 7 is selectedHardware-Assisted Multiplication

Turn on Include Multiply-step unit



Create the boot_monitor_rom System Peripheral

The boot_monitor_rom on-chip ROM system peripheral is implemented with Embedded System Blocks (ESBs) in the APEX device. To create the boot_monitor_rom system peripheral, follow these steps:

1. In MegaWizard Plug-In Manager - Nios page 5, click Next. MegaWizard Plug-In Manager - Nios System Builder page 4 appears, as shown in the following illustration:

2. In the New Peripheral Name box, type boot_monitor_rom.

3. In the Type list, select On-Chip ROM.

4. To specify ROM options, click Add. MegaWizard Plug-In Manager - Nios Internal ROM page 1 appears.

5. Under ROM Size, select 512 as the number of half-words.

6. To specify the file that controls initialization of the Nios embedded system processor, under ROM Input File type reference_design_32_germs_monitor.mif or click Browse Nios Library to select the file.

1 The Altera-provided reference_design_32_germs_monitor.mif file contains the instructions necessary to initialize the Nios embedded processor. This file is automatically executed when



your design is downloaded to the APEX device. The assembly language source code for this file is located in the \Cygwin\usr\altera\excalibur\nios-sdk\otherstuff\germMon.s file.

7. Click Next. MegaWizard Plug-In Manager - Nios Internal ROM page 2 appears.

8. Click Finish to generate the boot_monitor_rom system peripheral according to your specifications. The boot_monitor_rom system peripheral name appears in MegaWizard Plug-In Manager - Nios System Builder page 4, as shown in the following illustration:

9. To specify the base address of the boot_monitor_rom system peripheral, click the Base Addr cell highlighted in yellow.

10. In the Base Addr cell, type 0x0r. The end address 0x0003FF appears in the End Addr column automatically.

1 You can simply type 0r rather than 0x0r and the Quartus software displays the address in hexadecimal notation automatically.

Create the ext_flash & ext_ram System Peripherals

The ext_flash and ext_ram off-chip memory system peripherals allow the Nios embedded processor to interface with external memory components on the Nios development board. To create the ext_flash and ext_ram system peripherals, follow these steps:

Base Address cell highlighted in yellow



1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type ext_flash in the New Peripheral Name box.

2. In the Type list, select Memory Interface.

3. Click Add. MegaWizard Plug-In Manager page 1 appears.

4. Under Peripheral Type or Description, type Ext AM29LV800BB as the peripheral type, as shown in the following illustration:

1 The Peripheral Type or Description box is for information purposes only; therefore, you can type any name you want in the box.

5. Click Next. MegaWizard Plug-In Manager page 2 appears.

6. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager pages 2 through 7:


Is your peripheral on-chip or off-chip?

Make sure Off-Chip is selected

Width of Data Bus Make sure 16 is specifiedWidth of Address Bus Type 19



7. On MegaWizard Plug-In Manager page 6, click Next. MegaWizard Plug-In Manager page 7 appears.

8. Click Finish to generate the ext_flash system peripheral. The ext_flash system peripheral name appears in MegaWizard Plug-In Manager - Nios System Builder page 4.

9. Click the Alignment cell for the ext_flash system peripheral and select halfword from the list, as shown in the following illustration:

10. Click the Base Addr cell for the ext_flash system peripheral.

11. In the Base Addr cell, type 0x100000r. The end address 0x1FFFFF appears in the End Addr cell automatically.

Registered Chip-Select Option Make sure Use APEX Fast Output Register for Chip-Select is turned on

Wait-State Generation Select Fixed number of wait-states

Read Wait States Type 8Write Wait States Make sure 8 is specifiedInterrupt Request Make sure Peripheral produces

Interrupt-request signal is turned off


ext_flash system peripheral Alignment cell



12. Repeat steps 1 through 11 to create the ext_ram system peripheral with the options listed in the following table:

The system peripherals appear in MegaWizard Plug-In Manager - Nios System Builder page 4, as shown in the following illustration:


New Peripheral Name Type ext_ramType Select Memory InterfacePeripheral Type or Description

Type Ext SRAM2xIDT71V016SA

Is your peripheral on-chip or off-chip?

Make sure Off-Chip is selected

Width of Data Bus Type 32Width of Address Bus Type 16Registered Chip-Select Option Make sure Use APEX Fast Output

Register for Chip-Select is turned on

Duplicate Chip-Select Outputs

Select Two identical

Wait-State Generation Select Fixed number of wait-states

Read Wait States Type 0Write Wait States Make sure 0 is specifiedInterrupt Request Make sure Peripheral produces

Interrupt-request signal is turned off

Alignment Make sure word is selectedBase Addr Type 0x40000



Create the button_pio, lcd_pio, led_pio & seven_seg_pio System Peripherals

The button_pio, lcd_pio, led_pio, and seven_seg_pio parallel I/O system peripherals allow the Nios embedded processor to interface with external components, such as buttons, switches, the LCD display, and LEDs on the Nios development board. To create the button_pio, lcd_pio, led_pio, and seven_seg_pio system peripherals, follow these steps:

1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type button_pio in the New Peripheral Name box.

2. In the Type list, select Parallel I/O.

3. Click Add. MegaWizard Plug-In Manager - PIO page 1 appears.

1 If you have installed the Adobe Acrobat Reader software on your PC, you can press F1 to display the data sheet for the PIO system peripherals automatically.

4. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - PIO pages 1 through 2:



5. In MegaWizard Plug-In Manager - PIO page 2, click Next. MegaWizard Plug-In Manager - PIO page 3 appears.

6. To generate the button_pio system peripheral, click Finish. The button_pio system peripheral name appears in MegaWizard Plug-In Manager - Nios System Builder page 4.

7. Make sure word is specified in the Alignment cell for the button_pio system peripheral.

8. Click the Base Addr cell for the button_pio system peripheral.

9. In the Base Addr cell, type 0x470r. The end address of 0x00047F appears in the End Addr cell automatically.

10. Click the IRQ cell for the button_pio system peripheral.

11. In the IRQ cell, type 19. The system peripherals appear in MegaWizard Plug-In Manager - Nios System Builder page 4, as shown in the following illustration:


How many bits of PIO would you like (1-32)?

Type 12

Type of pins Select Input pins onlyEdge Capture Register Turn on Synchronously sample

inputs and capture. Select Any Edge.

Interrupt source Turn on Generate irq input and select Edge



12. Repeat steps 1 through 11 to create three more parallel I/O system peripherals—lcd_pio, led_pio, and seven_seg_pio—with the options listed in the following tables.

Specify the following responses to the wizard prompts for the lcd_pio system peripheral:

Specify the following responses to the wizard prompts for the led_pio system peripheral:


New Peripheral Name Type lcd_pioType Select Parallel I/OHow many bits of PIO would you like (1-32)?

Type 11

Type of pins Select Tri-state (bidirectional) pins

Edge Capture Register Make sure Synchronously sample inputs and capture is turned off

Interrupt source Make sure Generate irq input is turned off

Alignment Make sure word is selectedBase Addr Type 0x480IRQ N/A


New Peripheral Name Type led_pioType Select Parallel I/OHow many bits of PIO would you like (1-32)?

Type 2

Type of pins Select Output pins onlyAlignment Make sure word is selectedBase Addr Type 0x460IRQ N/A



Specify the following responses to the wizard prompts for the seven_seg_pio system peripheral:

The system peripherals appear in MegaWizard Plug-In Manager - Nios System Builder page 4, as shown in the following illustration:

Create the uart1 System Peripheral

To create the uart1 RS-232 asynchronous receiver/transmitter UART system peripheral, follow these steps:

1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type uart1 in the New Peripheral Name box.

2. In the Type list, select Uart.

3. Click Add. MegaWizard Plug-In Manager - UART page 1 appears.


New Peripheral Name Type seven_seg_pioType Select Parallel I/OHow many bits of PIO would you like (1-32)?

Make sure 16 is specified

Type of pins Select Output pins onlyAlignment Make sure word is selectedBase Addr Type 0x420IRQ N/A



1 If you have installed the Adobe Acrobat Reader software on your PC, you can press F1 to display the data sheet for the UART system peripheral automatically.

4. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - UART page 1:

1 These UART specifications are compatible with the nios-run terminal emulation program that you use later in this tutorial.

5. On MegaWizard Plug-In Manager - UART page 1, click Next. MegaWizard Plug-In Manager - UART page 2 appears.

6. To generate the uart1 system peripheral, click Finish. The uart1 system peripheral name appears in MegaWizard Plug-In Manager - Nios System Builder page 4.

7. Make sure word is specified in the Alignment cell for the uart1 system peripheral.

8. Click the Base Addr cell for the uart1 system peripheral.

9. In the Base Addr cell, type 0x400r. The end address of 0x00041F appears in the End Addr cell automatically.

10. Click the IRQ cell for the uart1 system peripheral.

11. In the IRQ cell, type 16. The system peripherals appear in MegaWizard Plug-In Manager - Nios System Builder page 4, as shown in the following illustration:


Input Clock Frequency Make sure 33333000 is specifiedBaud Rate Select 115200 and make sure

Baud rate can be changed by software is turned off.

Parity Make sure N is selectedData Bits Make sure 8 is selectedStop Bits Select 2



Create the timer1 System Peripheral

To create the timer1 32-bit interval timer system peripheral, follow these steps:

1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type timer1 in the New Peripheral Name box.

2. In the Type list, select Interval Timer.

3. Click Add. MegaWizard Plug-In Manager - TIMER page 1 appears.

1 If you have installed the Adobe Acrobat Reader software on your PC, you can press F1 to display the data sheet for the timer system peripheral automatically.

4. Click Next. MegaWizard Plug-In Manager - TIMER page 2 appears.

5. To generate the timer1 system peripheral, click Finish. The timer1 system peripheral name appears in MegaWizard Plug-In Manager - Nios System Builder page 4.

6. Make sure word is specified in the Alignment cell for the timer1 system peripheral.

7. Click the Base Addr cell for the timer1 system peripheral.

8. In the Base Addr cell, type 0x440r. The end address 0x00045F appears in the End Addr cell automatically.

9. Click the IRQ cell for the timer1 system peripheral.

10. In the IRQ cell, type 15.



You have now created all necessary system peripherals for the design, as shown in the following illustration:

4. Configure System Module Settings

You must specify the reset address, vector table, and main program memory in your design by configuring the system module settings. To configure the system module settings, follow these steps:

1. On MegaWizard Plug-In Manager - Nios System Builder page 4, click Next. MegaWizard Plug-In Manager - Nios System Builder page 5 appears.

2. Under Reset Address, specify the following responses to the wizard prompts:


Peripheral Make sure boot_monitor_rom is selected

Offset Make sure 0x0 is specified



3. Under Vector Table, specify the following responses to the wizard prompts:

4. Under Main Program Memory, make sure ext_ram is selected. See the following illustration:


5. Synthesize the Design with LeonardoSpectrum Software

Before you can compile the Nios system module with the Quartus software, you must first synthesize the logic of the system module. You can use the LeonardoSpectrum software, provided with the Quartus programmable logic development tools, to synthesize the logic of the nios32 system module and generate the nios32.edf file.


Peripheral Make sure ext_ram is selectedOffset Make sure 0x0 is specified



1 To run the LeonardoSpectrum software or other OEM tools from within the Quartus software, the location of the command-line program for the tool must be specified in your system search path, as described in the \Altera\Excalibur\nios_documentation\faq_hdk.txt file.

To synthesize the design with LeonardoSpectrum software, follow these steps:

1. On MegaWizard Plug-In Manager - Nios System Builder page 6, select Leonardo Spectrum as the synthesis tool.


3. To synthesize the logic of the nios32 system module, click Finish.

The LeonardoSpectrum software runs within the MegaWizard Plug-In Manager - Nios System Builder and begins to synthesize the nios32 system module. As the LeonardoSpectrum software synthesizes the design, it generates and displays various information and warning messages in the wizard. Complete synthesis may require up to 10 minutes or more. The wizard displays a message when synthesis is complete, as shown in the following illustration:

4. When synthesis is complete, click Finish to exit the MegaWizard Plug-In Manager and return to the Symbol dialog box. A preview of the new nios32 symbol appears in the Symbol dialog box.



5. To instantiate the nios32 symbol in the BDF, click OK in the Symbol dialog box. An outline of the nios32 symbol is attached to the pointer.

6. To place the symbol, click an empty space in the Block Editor window. The nios32 symbol is instantiated in the BDF, as shown in the following illustration:

7. Choose Save (File menu).

6. Enter Input, Output, Bidirectional & Primitive Symbols

To enter input, output, bidirectional, and primitive symbols, follow these steps:



1. Click the Symbol Tool button on the Block Editor toolbar (see step 1 on page 6 for an illustration of the toolbar buttons). The same Symbol dialog box that you used to enter the nios32 symbol appears. Note, however, that using the toolbar button opens this dialog box with the Repeat-insert mode option turned on.

1 When Repeat-insert mode is turned on, an outline of the selected symbol remains attached to the pointer, regardless of how many times you click the mouse pointer, allowing you to place multiple copies of the symbol easily. Whenever you want to stop placing copies of a symbol, you can press Esc or choose Cancel (right button pop-up menu).

2. In the Symbol dialog box, in the Libraries list, click the + icon to expand the d:\quartus\libraries folder, expand the primitives folder, and then expand the pin folder.

3. In the pin folder, select the input primitive.

4. Click OK.

5. Click an empty space four times to insert a total of four INPUT symbols on the left-hand side of the file. Symbols are automatically named as pin_name<number> in sequence. Press Esc.

6. Repeat steps 1 to 5 to insert and position a total of 13 OUTPUT pin symbols and 2 BIDIR pin symbols in the file in the locations shown in the following illustration:



7. Click the Symbol Tool button on the Block Editor toolbar. The Symbol dialog box appears.

8. In the Symbol dialog box, in the Libraries list, click the + icon to expand the d:\quartus\libraries folder, expand the primitives folder, and then expand the other folder.

9. In the other folder, select the gnd primitive.

10. Click OK.

11. Click an empty space in the BDF to insert the GND symbol.

12. Click the Symbol Tool button on the Block Editor toolbar. The Symbol dialog box appears.

13. In the Symbol dialog box, in the Libraries list, click the + icon to expand the d:\quartus\libraries folder, expand the primitives folder, and then expand the logic folder.

14. In the other folder, select the not primitive.

15. Click OK.



16. Click an empty space in the BDF to insert the NOT symbol.


7. Name the Pins

You can now name the input, output, and bidirectional pins. To name a pin, follow these steps:

1. With the Selection Tool, double-click the first input pin symbol you entered. The General tab of the Pin Properties dialog box appears automatically. See the following illustration:

2. In the Pin name(s) box, type clk to replace the default name of the first pin, that is, to replace pin_name.

3. Click OK.

4. Repeat steps 1 to 3 to rename each of the pins with the names listed in the following tables.



Specify the following names for the INPUT pin symbols:

Specify the following names for OUTPUT and BIDIR pin symbols:

Pin Type: Rename As: Description

INPUT clk(already entered)

Clock signal

INPUT button_pio[11..0] Input from buttons and switches

INPUT reset_n System reset

INPUT rxd uart1 receive signal


OUTPUT JP12_sel_n Enables the JP12 switchable 5V-tolerant header used with the LCD display

OUTPUT ext_sram_addr17 Output of SRAM address 17 (Flash and SRAM addr17 signals connected to separate APEX I/O pins)

BIDIR lcd_pio[10..0] LCD bidirectional data signal

OUTPUT ext_addr[19..0] Off-chip shared address signal

OUTPUT ext_be_n[3..0] Byte enables for off-chip memory

BIDIR ext_data[31..0] Off-chip bidirectional data signal



Specify the following names for the remaining OUTPUT pin symbols:

5. Move the INPUT, OUTPUT, BIDIR, GND, and NOT symbols so they line up with the appropriate ports and pinstubs, as shown in the following illustration:


OUTPUT ext_oe_n Shared off-chip output enable

OUTPUT ext_ram_we_n SRAM write enable

OUTPUT ext_flash_we_n Flash memory write enable (Flash and SRAM we_n signals connected to separate APEX I/O signals)

OUTPUT seven_seg_pio[15..0] Output signal to the seven segment LED display

OUTPUT ext_ram_select_0_n SRAM chip select 0

OUTPUT ext_ram_select_1_n SRAM chip select 1

OUTPUT ext_flash_select_n Flash memory chip select

OUTPUT txd uart1 transmit signal

OUTPUT led_pio[1..0] Output signal to the LEDs




8. Connect the Pins

After entering the inputs and outputs, you must connect them to the appropriate ports on the Nios system module. To connect the pins and primitives by drawing node and bus lines, follow these steps:

1. Click the Orthogonal Node Tool button on the toolbar (see step 1 on page 6 for an illustration of the toolbar buttons).

2. Click the pinstub of the clk input pin to define the start of the node, and then drag the pointer to draw a line that connects to the pinstub of the clk port of the nios32 system module.

GND symbol NOT symbol



1 When Use rubberbanding is turned on in the Block & Symbol Editor General Options tab (Options command), you can also draw node or bus lines by moving two symbols together so that their borders and pinstubs touch. When you move one of the symbols, a new line forms automatically between the pinstubs of the two symbols.

3. Repeat steps 1 through 2 to make additional connections between input and output pins and the nios32 system module ports shown in the following table. You can also refer to Figure 1 on page 32.

4. Click the Orthogonal Bus Tool button on the toolbar.

Draw Node Line From: To:

INPUT pin clk clk port (already entered)

INPUT pin reset_n reset_n port

INPUT pin rxd rxd_to_the_uart1 port

OUTPUT pin JP12_sel_n Pinstub of GND symbol

OUTPUT pin ext_oe_n off_chip_shared_oe_n port

OUTPUT pin ext_ram_we_n

off_chip_shared_we_n port

OUTPUT pin ext_flash_we_n

Node connecting the ext_ram_we_n pin to the off_chip_shared_we_n port

OUTPUT pin ext_ram_select_0_n

select_0_n_to_the_ext_ram port

OUTPUT pin ext_ram_select_1_n

select_1_n_to_the_ext_ram port

OUTPUT pin ext_flash_select_n

select_n_to_the_ext_flash port

OUTPUT pin txd txd_from_the_uart1 port



5. Click the pinstub of the button_pio[11..0] input pin to define the start of a bus, and then drag the pointer to draw a line that connects to the in_port_to_the_button_pio[11..0] port of the nios32 system module.

6. Repeat steps 4 through 5 to make additional bus connections between the INPUT, OUTPUT, and BIDIR pins and the nios32 system module ports shown in the following table. You can also refer to Figure 1 on page 32.

7. Click the Orthogonal Node Tool button on the toolbar.

8. To create a node that can be connected by name, draw a line from the pinstub of the ext_sram_addr17 output pin to an empty space.

9. Click the Selection Tool button on the toolbar.

Draw Bus Line From: To:

INPUT pin button_pio[11..0]

in_port_to_the_button_pio[11..0] port (already entered)

BIDIR pin lcd_pio[10..0]

bidir_port_to_and_from_the_lcd_pio[10..0] port

OUTPUT pin ext_addr[19..0]

off_chip_shared_address[19..0] port

OUTPUT pin ext_be_n[3..0]

off_chip_shared_be_n[3..0] port

BIDIR pin ext_data[31..0]

off_chip_shared_data_bus[31..0] port

OUTPUT pin seven_seg_pio[15..0]

out_port_from_the_seven_seg_pio[15..0] port

OUTPUT pin led_pio[1..0]

Output pinstub of the NOT primitive

NOT primitive input pinstub

out_port_from_the_led_pio[1..0] port



10. Double-click the node line that connects to the pinstub of the ext_sram_addr17 output pin. The General tab of the Node Properties dialog box appears automatically.

11. In the Name box, type ext_addr17 as the name of the node.

12. Click OK. The name now appears above the node line. Adding this name creates a logical connection between the ext_addr17 pin and the ext_sram_addr17 output pin that is connected to the SRAM device on the Nios development board.

13. Choose Save (File menu). The BDF is complete. See the following illustration:

Figure 1. The Completed nios_system_module BDF



Compilation

The Quartus Compiler consists of a series of modules that check the design for errors, synthesize the logic, fit the design into an Altera device, and generate output files for simulation, timing analysis, and device programming.

The following tutorial sections guide you through the steps necessary to create Compiler settings, assign signals to device pins, specify EDA tool settings, and compile the design.

Create Compiler Settings

You can create Compiler settings to control compilation processing. The Compiler settings specify the compilation focus, the type of compilation to perform, the device to target, and other options. This section includes the following steps:

1. View the Compiler general settings.2. Specify the device family and device.

1 The procedures below explain how to view and edit Compiler settings using menu commands and dialog boxes. However, you can also easily specify Compiler settings by following the steps in the Compiler Settings Wizard (Processing menu).

1. View the Compiler General Settings

The General tab of the Compiler Settings dialog box allows you to select an existing group of Compiler settings for use during compilation, define and save a new group of Compiler settings, specify the compilation focus, or delete existing settings.

To view the default Compiler general settings created for the current project, follow these steps:



1. Make sure that you are in Compile mode by selecting Compile Mode (Processing menu).

2. Choose Compiler Settings (Processing menu). The General tab of the Compiler Settings dialog box appears automatically.

At this point in the tutorial, the General tab displays only the default Compiler general settings created by the Quartus software when the project was initially created. These default settings are given the name of the top-level design entity in the project, nios_system_module. See the following illustration:

2. Specify the Device Family & Device

The Chips & Devices tab of the Compiler Settings dialog box allows you to select the family and device you want to target for compilation.

Shows the existing Compiler settings for your project.

Specifies the hierarchical path name of the design entity you want to compile.

Specifies the current Compiler settings.



To select the device family and device, follow these steps:

1. In the Compiler Settings dialog box, click the Chips & Devices tab.

2. In the Family list, make sure APEX20KE is selected.

3. Under Target device, select Specific device selected in “Available devices” list.

4. Under Show in “Available devices” list, select the following options:

a. In the Package list, select FBGA.

b. In the Pin count list, select 484.

c. In the Speed grade list, select -2. See the following illustration:

5. In the Available devices list, select EP20K200EFC484-2X.

Identifies the Compiler settings you are editing.



6. To accept the defaults for the remaining Compiler settings, click OK.

Assign Signals to Device Pins

During compilation, the Compiler assigns the logic of your design to physical device resources. You can also make pin assignments to direct the Compiler to assign signals in your design to specific pins in the target device. Because the targeted APEX device is already mounted on the Nios development board, you must assign the signals of the design to the appropriate pins in the device.

The Quartus software provides several methods for making pin assignments. You can assign pins individually with the Assignment Organizer (Tools menu) or with the Pin Assignments dialog box, or you can assign all necessary pins at once with a Tcl script. Because of the number of pin assignments to be made in the tutorial, you can use the Altera-provided pin_assign.tcl Tcl script to make the appropriate pin assignments easily.

This session includes the following steps:

1. Assign pins with a Tcl script.2. Verify the pin assignments.

1. Assign Pins with a Tcl Script

To make pin assignments with the Altera-provided pin_assign.tcl Tcl script, follow these steps:

1. Make sure the Altera-provided pin_assign.tcl file is located in the d:\Altera\Excalibur\nios_tutorial project directory.

2. To open the Quartus Tcl Console window, choose Auxiliary Windows > Tcl Console (View menu). The Quartus Tcl Console window appears. See the following illustration:



3. At the Quartus Tcl Console command prompt, type the following command:

source pin_assign.tclr

The Tcl script is executed and assigns all necessary pins. When the assignments are complete, the assignment made message appears in the Tcl Console window.

2. Verify the Pin Assignments

To verify the pin assignments, follow these steps.

1. Choose Compiler Settings (Processing menu). The General tab of the Compiler Settings dialog box appears automatically.

2. Click the Chips & Devices tab.

3. Click Assign Pins. The Pin Assignments dialog box appears with the new pin assignments listed in the Available Pins & Existing Assignments list. See the following illustration:



4. When you are done viewing the pin assignments, click OK.

Specify Device, Programming & EDA Tool Settings

Before compiling the design, you can specify options that control the use of unused pins, optional programming file generation, and EDA tool settings. This section includes the follow steps:

Lists the pin assignments made by the Tcl script



1. Reserve unused pins.2. Specify optional programming files.3. Specify EDA tool settings.

1. Reserve Unused Pins

To specify options for reserving unused pins, follow these steps:

1. In the Chips & Devices tab of the Compiler Settings dialog box, click Device & Pin Options. The General tab of the Device & Pin Options dialog box appears automatically.

2. Click the Unused Pins tab.

3. Under Reserve all unused pins, select As inputs, tri-stated.

2. Specify Optional Programming Files

By default, the Compiler always generates an SRAM Object File (.sof). The Programmer uses an SOF to configure an APEX device with your design. However, you can also direct the Compiler to generate other optional programming files during compilation. For example, you can generate a Hexadecimal (Intel-Format) Output File (.hexout) that can be used to download your design to the user-configuration area of the flash memory device provided on the Nios development board.

To specify optional programming files, follow these steps:

1. In the Device & Pin Options dialog box, click the Programming Files tab.

2. Turn on Hexadecimal (Intel-Format) Output File (.hexout).

3. To accept the remaining defaults and save the device and pin options, click OK.

4. In the Chips & Devices tab, click OK.



3. Specify EDA Tool Settings

To specify the appropriate EDA tool settings for use when compiling a design synthesized with the LeonardoSpectrum software, follow these steps:

1. Choose EDA Tool Settings (Project menu). The EDA Tool Settings dialog box appears.

2. Under Design entry/synthesis tool, select Leonardo Spectrum (Level 1). See the following illustration:

3. Click OK.

Compile the Design

During compilation the Compiler locates and processes all design and project files, generates messages and reports related to the current compilation, and creates the SOF and any optional programming files.



To compile the nios_system_module design, follow these steps:

1. Choose Start Compilation (Processing menu).

The Compiler immediately begins to compile the nios_system_module design entity, and any subordinate design entities, using the nios_system_module Compiler settings. As the design compiles, the Status window automatically displays, as a percentage, the total compilation progress and the time spent in each stage of the compilation. The results of the compilation are updated in the Compilation Report window. The total compilation time may require 20 minutes or more, depending on your system.

The Compiler may generate one or more of the following warning messages that do not affect the outcome of your design:

2. If you receive a message indicating that compilation was successful, click OK to close the message box.

1 If the Compiler displays any error messages, you should correct them in your design and recompile it until it is error-free before proceeding with the tutorial. You can select the message and choose Locate (right button pop-up menu) to find its source(s), and/or choose Help (right button pop-up menu) to display help on the message.

Warning messages



Programming

After a successful compilation, the Quartus Compiler generates one or more programming files that the Programmer can use to program or configure a device. You can download configuration data directly into the APEX device with the ByteBlasterMV communications cable connected to the JTAG port on the Nios development board. You can also download configuration data to a flash memory device on the Nios development board over a serial port using a terminal emulation program. Then, you can configure the APEX device using the data stored in flash memory.

Configure an APEX Device

Once you have properly connected and set up the MasterBlasterMV cable to transmit configuration data over the JTAG port, you can configure the APEX device on the Nios development board with your design.

To configure the APEX device on the Nios development board with the nios_system_module design, perform the following steps:

1. Choose Open Programmer (Processing menu). The Programmer window opens a blank Chain Description File (.cdf), as shown in the following illustration:



2. Choose Save As (File menu).

3. In the Save As dialog box, type nios_system_module.cdf in the File name box.

4. Make sure that in the Save as type list, Chain Description File is selected.

5. Click Save.

6. In the Mode list of the Programmer window, make sure JTAG is selected.

7. Under Programming Hardware, click Setup. The Hardware Setup dialog box opens.

8. In the Hardware Type list, select ByteBlasterMV.

9. In the Port list, select the port that is connected to the ByteBlasterMV cable. Click OK.

10. Click Add File. The Select File dialog box appears.

11. Specify the nios_system_module.sof file in the File name box.

12. Click Open. The SOF is listed in the Programmer window.



13. In the Programmer window, turn on Program/Configure. See the following illustration:

14. On the Nios development board, make sure switch SW8 is in the CONNECT position, and that switches SW9 and SW10 are in the BYPASS position. Figure 2 illustrates the correct configuration of the JTAG switches:

Figure 2. Nios Development Board JTAG Switch Configuration

Program/Configure turned on

Apex JTAG

Max JTAG

PMC JTAG

SW

8S

W9

SW

10

CONNECT BYPASS



15. Click Start. The Programmer begins to download the configuration data to the APEX device. The Progress field displays the percentage of data that is downloaded. A message appears when the configuration is complete.

When the design is successfully downloaded to the APEX device, the following events occur:

� The instructions specified in the boot_monitor_rom system peripheral are executed. In this case, the reference_designs_32_germs monitor.mif file (also known as the “GERMS monitor”) located at 0x000 is executed. The GERMS monitor performs the following system initialization tasks:

– Disables interrupts on the UART, timer, and switch PIO.– Sets the Stack Pointer register to 0x080000.– Examines two flash memory bytes at 0x14000C for executable

code.– Determines the state of button SW4 on the Nios development

board.

� When the GERMS monitor determines that the flash memory bytes at 0x14000C contain n and i and that button SW4 is not pressed, it executes a call to location 0x140000. By default, this call loads a sample peripheral test program that you use later in this tutorial.

When the configuration is successfully completed, LED1 and LED2 are lit on the Nios development board.

1 If you are unable to correctly configure the device, you can press the RESET button on the Nios development board to reload the factory default reference design and continue the tutorial.

Download the Design to Flash Memory

You can store configuration data in the flash memory device provided on the Nios development board. This section describes how to use the GERMS monitor to erase the user-configurable section of the flash memory device



on the Nios development board. Then, you can use the nios-run utility to download the configuration data to the flash memory device on the Nios development board.

This section contains the following steps:

1. Start the bash shell.2. Run the sample hello.srec test program.3. Download the configuration data to flash memory.

1. Start the bash Shell

The bash shell, provided with the GNUPro Nios software development tools, is a UNIX-like command shell that allows you to run the nios-run utility and various test programs on the Nios development board.

To start the bash shell, perform the following steps:

1. Choose Programs > Cygwin > bash (Windows Start menu). The bash window appears. The bash window displays some text, including path information and some messages about sample programs. See the following illustration:



2. Run the Sample hello.srec Test Program

You can compile and run the Altera-provided hello.c program to test the functionality of the nios_system_module design you downloaded into the APEX device. The hello.c program is located in the default directory of the bash shell, \Cygwin\usr\altera\excalibur\nios-sdk\examples. You can use the nios-build and nios-run utilities to compile the hello.c program and run it on your Nios system module.

To compile and run the sample hello.c test program from the bash shell, follow these steps:

1. Type the following command at the bash command prompt:

nios-build hello.cr

The nios-build utility compiles the C code in the hello.c file and generates the hello.srec file.

2. To run the hello.srec program, type the following command at the bash prompt:

nios-run -p com<com port number> hello.srecr

1 If you do not specify a COM port with the-p com<com port number> text, the nios-run utility attempts to use COM1 by default.

The nios-run utility runs the hello.srec program on the Nios system module you created. This program generates the message Hello, from Nios! and causes the 2-digit 7-segment LED (D1) to count down from 99 to 00. See the following illustration:



3. When the hello-srec program is complete, press the CLEAR button on the Nios development board to clear the program from the Nios embedded processor.

3. Download the Configuration Data to Flash Memory

You can use the nios-run utility to switch the bash shell to terminal mode. The terminal mode allows you to communicate with the Nios development board through the GERMS monitor. By sending commands through the GERMS monitor, you can erase the user-section of the flash memory device and download the nios_system_module.hexout file that stores configuration data for your project.

To download configuration data to the flash memory device on the Nios development board, follow these steps:

1. To change to the project directory, type the following command at the bash prompt:

cd d:/Altera/Excalibur/nios_tutorialr

1 Note that you must use the “/” character instead of the“\” character as a directory separator in the bash window.



2. To use the nios-run utility in terminal mode, type the following command at the bash prompt:

nios-run -p com<com port number> -tr

The nios-run utility is now in terminal mode.

3. Press r. The version number of the Nios embedded processor appears, followed by the command prompt.

4. At the command prompt, press r. The GERMS monitor displays the four lines of eight half-words located at the Stack Pointer register memory address, followed by the command prompt. See the following illustration:

Command prompt

Nios embedded processor version number

Stack Pointer register memory contents



5. To erase the user-section of the flash memory contents, beginning at memory address 0x180000, type the following commands at the GERMS monitor prompt:

e180000re190000re1a0000re1b0000rr180000r

1 If you make a mistake entering any of these commands, you cannot use the Backspace key to correct the error. Instead, you must press Esc and re-enter the entire line.

The e command erases the block of flash memory at the specified hexadecimal flash memory address. The r command relocates the Stack Pointer register to the specified hexadecimal flash memory address.

6. To exit the GERMS monitor prompt, press Ctrl + C. The bash prompt appears.

7. To download configuration data for your project to the flash memory device on the Nios development board, type the following command at the bash prompt:

nios-run -p com<com port number> nios_system_module.hexoutr

The nios-run utility begins to download the configuration data to the flash memory device on the Nios development board, beginning at memory address 0x180000. This task may require several minutes to complete. The nios-run utility returns to terminal mode when the download is complete.

8. To configure the APEX device with the nios_system_module data stored in the flash memory, press the RESET button (SW2) on the Nios development board. The APEX device is configured with the nios_system_module data stored in the flash memory device. When the configuration is complete, LED1 and LED2 are lit on the Nios development board, and the peripheral test program stored in flash memory appears in the bash window automatically.



Restore Factory Default Configuration

After you are finished using the nios_system_module design on the Nios development board, you can optionally restore the board to its factory default state and run a peripheral test program.

To restore the Nios development board to its factory default configuration and run the peripheral test program, follow these steps:

1. On the Nios development board, shunt across jumper JP2 and press the RESET button (marked SW2). The nios_system_module design is cleared and the factory default reference_design is loaded into the APEX device. The Nios Peripheral Test Main Menu appears in the bash window, as shown in the following illustration:

2. If you want to test any of the peripherals on the development board, type a through f to select a peripheral from the Main Menu.

3. When you are done testing the development board peripherals, return to the Main Menu and type q to exit the peripheral test program and return to terminal mode. The GERMS monitor prompt (+) appears, as shown in the following illustration:



1 You can stop the GERMS monitor from automatically running the peripheral test program stored in flash memory by pressing and releasing the CLEAR (SW3) button while pressing and holding the SW4 button on the Nios development board.

GERMS monitor prompt




Contacting Altera

If you have any additional questions about Altera products, contact Altera for technical support and product information.

Technical Support

If you need technical support, call or fax the Altera Applications Department Monday through Friday.

You can also e-mail the Altera Applications Department at [email protected].

In addition, you can visit the Atlas® online solutions database, which is located at http://www.altera.com.

For additional technical support for the Quartus software, choose Altera on the Web > Quartus Home Page (Help menu), or point your browser to the Quartus support page at https://websupport.altera.com. This web site provides information on how to register your software and obtain license information, and provides other support information.

Product Information

If you need the latest Altera product information or literature, use the Altera web site, which is available 24 hours a day, seven days a week.

f Go to “Contacting Altera” in Quartus Help for complete information on Altera technical support services.

Tel: (800) 800-EPLD (408) 544-7000

(6:00 a.m. to 6:00 p.m. Pacific Time)(7:30 a.m. to 5:30 p.m. Pacific Time)

Fax: (408) 544-6401

Web site: http://www.altera.com

Nios Embedded Processor Hardware Tutorial

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