Nios II Processor Reference Handbook - John Loomis Introduction This handbook is the primary...

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Transcript of Nios II Processor Reference Handbook - John Loomis Introduction This handbook is the primary...

  • 101 Innovation Drive San Jose, CA 95134 www.altera.com

    Nios II Processor Reference Handbook

    NII5V1-8.0

    http://www.altera.com

  • Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap- plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services.

    Printed on recycled paper

    ii Altera Corporation

  • Altera Corporation

    Contents

    Chapter Revision Dates ........................................................................... ix

    About This Handbook .............................................................................. xi Introduction ............................................................................................................................................... xi

    Prerequisites ..................................................................................................................................... 1–xi How to Find Further Information ........................................................................................................ xii How to Contact Altera ........................................................................................................................... xii Typographical Conventions ................................................................................................................. xiii

    Section I. Nios II Processor

    Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Nios II Processor System Basics .......................................................................................................... 1–1 Getting Started with the Nios II Processor ........................................................................................ 1–2 Customizing Nios II Processor Designs ............................................................................................. 1–3 Configurable Soft-Core Processor Concepts ...................................................................................... 1–4

    Configurable Soft-Core Processor .................................................................................................. 1–4 Flexible Peripheral Set and Address Map .................................................................................... 1–5 Custom Instructions ......................................................................................................................... 1–5 Automated System Generation ...................................................................................................... 1–6

    OpenCore Plus Evaluation ................................................................................................................... 1–6 Referenced Documents ......................................................................................................................... 1–7 Document Revision History ................................................................................................................. 1–7

    Chapter 2. Processor Architecture Introduction ............................................................................................................................................ 2–1 Processor Implementation .................................................................................................................... 2–3 Register File ............................................................................................................................................ 2–3 Arithmetic Logic Unit ........................................................................................................................... 2–4

    Unimplemented Instructions .......................................................................................................... 2–4 Custom Instructions ......................................................................................................................... 2–4 Floating Point Instructions .............................................................................................................. 2–5

    Reset Signals ........................................................................................................................................... 2–6 Exception and Interrupt Controller .................................................................................................... 2–7

    Exception Controller ........................................................................................................................ 2–7 Integral Interrupt Controller ........................................................................................................... 2–7 Interrupt Vector Custom Instruction ............................................................................................. 2–7

    iii

  • Contents

    Memory and I/O Organization ........................................................................................................... 2–8 Instruction and Data Buses ........................................................................................................... 2–10 Cache Memory ................................................................................................................................ 2–12 Tightly-Coupled Memory ............................................................................................................. 2–14 Address Map ................................................................................................................................... 2–15 Memory Management Unit .......................................................................................................... 2–15 Memory Protection Unit ................................................................................................................ 2–16

    JTAG Debug Module .......................................................................................................................... 2–17 JTAG Target Connection ............................................................................................................... 2–18 Download and Execute Software ................................................................................................. 2–18 Software Breakpoints ..................................................................................................................... 2–18 Hardware Breakpoints .................................................................................................................. 2–18 Hardware Triggers ......................................................................................................................... 2–19 Trace Capture .................................................................................................................................. 2–20

    Referenced Documents ....................................................................................................................... 2–21 Document Revision History ............................................................................................................... 2–22

    Chapter 3. Programming Model Introduction ............................................................................................................................................ 3–1 Operating Modes ................................................................................................................................... 3–2

    Supervisor Mode .............................................................................................................................. 3–2 User Mode ......................................................................................................................................... 3–3

    Memory Management Unit .................................................................................................................. 3–3 Recommended Usage ...................................................................................................................... 3–3 Memory Management ..................................................................................................................... 3–4 Address Space and Memory Partitions ......................................................................................... 3–5 TLB Organization ............................................................................................................................. 3–8 TLB Lookups ..................................................................................................