Nios II Processor Reference Handbook

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Transcript of Nios II Processor Reference Handbook

  • Nios II Classic Processor Reference Guide

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    NII5V12016.06.17

    101 Innovation DriveSan Jose, CA 95134www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=NII5V1mailto:[email protected]?subject=Feedback%20on%20Nios%20II%20Classic%20Processor%20Reference%20Guide%20(NII5V1%202016.06.17)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Introduction........................................................................................................ 1-1Nios II Processor System Basics................................................................................................................. 1-1Getting Started with the Nios II Processor............................................................................................... 1-2Customizing Nios II Processor Designs....................................................................................................1-3Configurable Soft Processor Core Concepts............................................................................................ 1-4

    Configurable Soft Processor Core..................................................................................................1-4Flexible Peripheral Set and Address Map..................................................................................... 1-4Automated System Generation...................................................................................................... 1-5

    OpenCore Plus Evaluation..........................................................................................................................1-5Document Revision History....................................................................................................................... 1-6

    Processor Architecture........................................................................................ 2-1Processor Implementation.......................................................................................................................... 2-2Register File...................................................................................................................................................2-3Arithmetic Logic Unit................................................................................................................................. 2-4

    Unimplemented Instructions......................................................................................................... 2-4Custom Instructions........................................................................................................................ 2-5Floating-Point Instructions.............................................................................................................2-5

    Reset and Debug Signals........................................................................................................................... 2-10Exception and Interrupt Controllers....................................................................................................... 2-11

    Exception Controller..................................................................................................................... 2-11EIC Interface...................................................................................................................................2-11Internal Interrupt Controller........................................................................................................2-12

    Memory and I/O Organization................................................................................................................2-12Instruction and Data Buses...........................................................................................................2-14Cache Memory............................................................................................................................... 2-16Tightly-Coupled Memory.............................................................................................................2-17Address Map................................................................................................................................... 2-18Memory Management Unit.......................................................................................................... 2-18Memory Protection Unit...............................................................................................................2-19

    JTAG Debug Module................................................................................................................................. 2-20JTAG Target Connection...............................................................................................................2-20Download and Execute Software................................................................................................. 2-21Software Breakpoints..................................................................................................................... 2-21Hardware Breakpoints...................................................................................................................2-21Hardware Triggers..........................................................................................................................2-21Trace Capture..................................................................................................................................2-22

    Document Revision History.....................................................................................................................2-23

    Programming Model........................................................................................... 3-1Operating Modes..........................................................................................................................................3-1

    TOC-2

    Altera Corporation

  • Supervisor Mode.............................................................................................................................. 3-1User Mode......................................................................................................................................... 3-2

    Memory Management Unit........................................................................................................................ 3-2Recommended Usage...................................................................................................................... 3-2Memory Management..................................................................................................................... 3-3Address Space and Memory Partitions......................................................................................... 3-4TLB Organization............................................................................................................................ 3-5TLB Lookups.....................................................................................................................................3-7

    Memory Protection Unit.............................................................................................................................3-7Memory Regions.............................................................................................................................. 3-8Overlapping Regions....................................................................................................................... 3-9Enabling the MPU............................................................................................................................3-9

    Registers.........................................................................................................................................................3-9General-Purpose Registers........................................................................................................... 3-10Control Registers............................................................................................................................3-11Shadow Register Sets..................................................................................................................... 3-30

    Working with the MPU.............................................................................................................................3-32MPU Region Read and Write Operations.................................................................................. 3-32MPU Initialization......................................................................................................................... 3-33Debugger Access............................................................................................................................ 3-33

    Working with ECC.....................................................................................................................................3-34Enabling ECC................................................................................................................................. 3-34Handling ECC Errors.................................................................................................................... 3-34Injecting ECC Errors..................................................................................................................... 3-34

    Exception Processing.................................................................................................................................3-36Terminology....................................................................................................................................3-36Exception Overview.....................................................