field effect transistors

20
Field Effect Transistors (FETs)

Transcript of field effect transistors

Page 1: field effect transistors

Field Effect Transistors (FETs)

Page 2: field effect transistors

Junction FETs

Figure 23-1. Cross section of an N-channel JFET.

Page 3: field effect transistors

Junction FETs (cont’d.)

Figure 23-2. Lead connections for an N-channel JFET.

Page 4: field effect transistors

Junction FETs (cont’d.)

Figure 23-3. Properly biased N-channel JFET.

Page 5: field effect transistors

Junction FETs (cont’d.)

Figure 23-4. Schematic symbols for JFETs.

Page 6: field effect transistors

Figure 23-5. The polarities required to bias an N-channel JFET.

Figure 23-6. The polarities required to bias a P-channel JFET.

Page 7: field effect transistors

Depletion Insulated Gate FETs (MOSFETs)

Figure 23-7. N-channel depletion MOSFET.

Page 8: field effect transistors

Depletion Insulated Gate FETs (MOSFETs) (cont’d.)

Figure 23-8. N-channel depletion MOSFET with bias supply.

Page 9: field effect transistors

Depletion Insulated Gate FETs (MOSFETs) (cont’d.)

Figure 23-9. Schematic symbol for an N-channel depletion MOSFET.

Page 10: field effect transistors

Depletion Insulated Gate FETs (MOSFETs) (cont’d.)

Figure 23-10. Properly biased N-channel depletion MOSFET.

Page 11: field effect transistors

Depletion Insulated Gate FETs (MOSFETs) (cont’d.)

Figure 23-11. Schematic symbol for a P-channel depletion MOSFET.

Page 12: field effect transistors

Enhancement Insulated Gate FETs (MOSFETs)

Figure 23-12. P-channel enhancement MOSFET.

Page 13: field effect transistors

Enhancement Insulated Gate FETs (MOSFETs)

Figure 23-13. Schematic symbol for a P-channel enhancement MOSFET.

Page 14: field effect transistors

Enhancement Insulated Gate FETs (MOSFETs)

Figure 23-14. Properly biased P-channel enhancement MOSFET.

Page 15: field effect transistors

Enhancement Insulated Gate FETs (MOSFETs)

Figure 23-15. Schematic symbol for an N-channel enhancement MOSFET.

Page 16: field effect transistors

Enhancement Insulated Gate FETs (MOSFETs)

Figure 23-16. Properly biased N-channel enhancement MOSFET.

Page 17: field effect transistors

MOSFET Safety PrecautionsKeep the leads shorted togetherWear a grounded metallic wristbandUse a grounded soldering iron tipMake sure power is off

Page 18: field effect transistors

Testing FETsCommercial transistor test equipmentOhmmeter

Page 19: field effect transistors

SummaryThe three leads of a JFET are attached to the

gate, source, and drainMOSFETs (insulated gate FETs) isolate the

metal gate from the channel with a thin oxide layer

Depletion mode MOSFETs are usually N-channel devices and are classified as normally on

Page 20: field effect transistors

Summary (cont’d.)Enhancement mode MOSFETs are usually P-

channel devices and are normally offElectrostatic charges from fingers can

damage a MOSFETJFETs and MOSFETs can be tested using a

commercial transistor tester or an ohmmeter