Lecture 28 Field-Effect Transistors 28 Field-Effect Transistors. ... MOSFET Summary. ELECTRICAL...

ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.

Lecture 28Field-Effect Transistors


Field-Effect Transistors

1. Understand MOSFET operation.

2. Analyze basic FET amplifiers using the load-line technique.

3. Analyze bias circuits.


4. Use small-signal equivalent circuits to analyze FET amplifiers.

5. Compute the performance parameters of several FET amplifier configurations.

7. Understand the basic operation of CMOS logic gates.


NMOS Transistor


Operation in the Cutoff Region

toGSD Vvi ≤= for 0


Operation Slightly Above Cut-Off

By applying a positive bias between the Gate (G) and the body (B), electrons are attracted to the gate to form a conducting n-typechannel between the source and drain. The positive charge on the gate and the negative charge in the channel form a capacitor where:

oxgate t

WLdAC εε ==


The amount of negative charge that accumulates in the channel is given by:

DS

toGSgate

vL

EL

VvCQ

μμτ

2

velocityL

)(

===

−=

This amount of charge is able to move a distance L from the source to the drain in a time τ given by:



The initial current flow for low drain-source voltage is given by:

DStoGSox

DS

toGSgate

DS

vVvLt

WvL

VvC

Qi

)(

)(metransit ti

in transit charge

2

−=

−=

==

μεμ

τ




DStoGSox

DS vVvLt

Wi )( −=με

For small values of vDS, iD is proportional to vDS. The device behaves as a resistance whose value depends on vGS.


Operation in the Triode Region

( )[ ]22 DSDStoGSD vvvvCi −−=

2KP

LWC ⎟

⎠⎞

⎜⎝⎛=


Operation in the Saturation Region

( )

2

2

DSD

toDSGS

toDSGSDSGSGD

toGD

toGSD

Cvi

VvvVvvvvv

VvVvCi

=

+==−→−=

=

−=

boundary the at saturation into transition the at


Exercise 12.1Consider an NMOS transistor having Vto=2V. What is the region of

operation (triode, saturation, or cutoff) if:

1. vGS = 1V and vDS = 5V? Cutoff since vGS <Vto

2. vGS = 3V and vDS = 0.5V? Triode since vGS >Vto and vDS<vGS - Vto

3. vGS = 3V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS – Vto

4. vGS = 5V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS - Vto


Exercise 12.2Suppose that we have an NMOS transistor with KP = 50μA/V2, Vto = 1V, L = 2μm and W = 80μm. Sketch the drain characteristics for vDS from 0 to 10V and vGS=0, 1, 2, 3 and 4V.

For vGS= 0 or 1V, the transistor is cutoff and the drain current is zero. In the saturation region:

2

26

)(

/12

80)1050(21

2

toGSD VvCI

VmaxLWKPC

−=

=⎟⎠⎞

⎜⎝⎛=⎟

⎠⎞

⎜⎝⎛= −

The boundary between the triode and saturation regions occurs when toGSDS Vvv −=

394243112

)()( DSDGS vmAiVv

2DSD CvI =


Exercise 12.2


PMOS Transistor

p+ p+

n


MOSFET Summary


Exercise 12.3Suppose that we have an PMOS transistor with KP = 25μA/V2, Vto= -1V, L = 2μm and W = 200μm. Sketch the drain characteristics for vDS from 0 to -10V and vGS= 0, -1, -2, -3 and -4V.

For vGS= 0 or -1V, the transistor is cutoff and the drain current is zero. In the saturation region:

2

26

)(

/25.12

200)1025(21

2

toGSD VvCI

VmaxLWKPC

−=

=⎟⎠⎞

⎜⎝⎛=⎟

⎠⎞

⎜⎝⎛= −

The boundary between the triode and saturation regions occurs when toGSDS Vvv −=

325.114253125.12

)()(

−−−−−−

DSDGS vmAiVv

2DSD CvI =


Exercise 12.3


Load-Line Analysis of a Simple NMOS Circuit

( ) ( )tvtiRv DSDDDD +=


To establish the load line, we first locate two points on it:


For vDD = 20V and RD=1kΩ

( ) ( )

( ) ( )

mAkViv

VvitvtikV

tvtiRv

DDS

DSD

DSD

DSDDDD

201200

200120

=Ω

=→=

=→=+Ω=

+=



The quiescent operating point (Q point) is found for vin = 0V

0Vfor 44)()(

==+=

in

inGS

vVVtvtv



The maximum gate-to-source voltage is found for vin = 1V

1Vfor 54)()(==

+=

in

inGS

vVVtvtv



The minimum gate-to-source voltage is found for vin = -1V

1Vfor 34)()(

−==+=

in

inGS

vVVtvtv


Peak to peak swing of vGS is 2V

Peak to peak swing of vDS is 12V 6212" −=−

=VA"


The output is not proportional to the input. The output goes down by 7V for a change of +1V on the input. The output goes up by 5V for a change of -1V on the input. The output is said to be “distorted”. This is due to the uneven spacing of the characteristic curves.

vDSQ=11V+5V

-7V



Uneven spacing of the drain characteristics


Exercise 12.4Find vDSQ, vDSmin and vDSmax if the circuit values are changed to VDD=15V, VGG=3V:

3V

15V

1Vfor 4-1Vfor 2V0Vfor 3

3)()(

+======

+=

in

in

in

inGS

vVvvV

Vtvtv


To establish the load line, we first locate two points on it:

For vDD = 15V and RD=1kΩ

( ) ( )

( ) ( )

mAkViv

VvitvtikV

tvtiRv

DDS

DSD

DSD

DSDDDD

151150

150115

=Ω

=→=

=→=+Ω=

+=

Exercise 12.4


Exercise 12.4

vDSQ=11V

vDSmin=6V vDSmax=14V

1Vfor V4

-1Vfor 2V

0Vfor V3

max

min

+==

==

==

inGS

inGS

inGS

vv

vv

vvQ


FET Logic


CMOS Inverter


Two-Input CMOS NAND Gate


Two-Input CMOS NOR Gate

Lecture 28 Field-Effect Transistors 28 Field-Effect Transistors. ... MOSFET Summary. ELECTRICAL...

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Transcript of Lecture 28 Field-Effect Transistors 28 Field-Effect Transistors. ... MOSFET Summary. ELECTRICAL...