Digital Logic Design Lecture # 14 University of Tehran.
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Digital Logic Design Lecture # 14 University of Tehran
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Transcript of Digital Logic Design Lecture # 14 University of Tehran.
Digital Logic Design
Lecture # 14University of Tehran
Outline
Review of Lecture #13 PLA PAL Structure of PROM’s Transistors MSI Parts as a ROM Cascading ROMs
Review of Lecture #13 Let us continue our discussion of
programmable devices. We saw the structure of a ROM with 4 inputs that had 16 lines entering its OR plane from the AND plane. The AND plane can actually be considered a 4-to-16 DCD as seen in the following figure:
AND OR
0
15
...A B C D
w x y z
Review of Lecture #13 (continued…) We saw that no minimization was done when
realizing functions with ROMs, because all minterms were produced in the fixed AND plane.
PLA Consider the following truth table:
B C D w
0
0
00
00
000 1
0
0
0
0
1
1
11
1
11
1
1
0
111
11
1
0
0
0
0
00
00
000 0
0
0
0
1
1
1
11
1
11
1
1
0
111
11
0
0
0
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
z
0
1
0
1
1
1
1
0
0
0
0
1
0
1
1
1
y
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
3:
2:
1:
0:
5:
4:
7:
6:
11:
10:
9:
8:
13:
12:
15:
14:
PLA (continued…) Note all minterms are used in the realization of
a function, and so minimizing this truth table using 4 variable KMs can be useful. Consider the following minimization:
41 1
0 1
AB
CD
000
1 5
70 1
1 0
3
2 6
01
11
10
81 1
0 0
12
13 9
111 0
1 0
15
14 10
00 01 11 10
z
40 0
0 1
AB
CD
000
1 5
71 0
1 0
3
2 6
01
11
10
81 0
0 0
12
13 9
111 0
1 0
15
14 10
00 01 11 10
x
41 0
1 0
AB
CD
000
1 5
70 1
1 0
3
2 6
01
11
10
80 0
0 1
12
13 9
110 1
0 1
15
14 10
00 01 11 10
w
41 1
1 0
AB
CD
000
1 5
70 0
0 1
3
2 6
01
11
10
81 1
1 1
12
13 9
110 1
0 1
15
14 10
00 01 11 10
yWe will show whythese 1s are mapped
like this later on
PLA (continued…) In the minimization method shown in the last
slide, the number of variables used in a term is of no importance. What we are looking to do in this minimization is to share product terms between the different functions thus being able to decrease the number of rows in our AND plane. Doing this the shown truth table can be realized as shown in the next slide.
PLA (continued…)A B C D w zyx
B C D
A B D
A B C
A B C D
A B C
A B C
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
C D
_
__
_
___
_
_
_
__
_
__
_ _
__
_
_
__
PLA (continued…) The reason we don’t look for decreasing the
number of literals in our product terms is rather obvious as there is no hardware difference. What we gain in this procedure is better layout and less rows which can be better observed in functions of a larger number of variables. These structures are called PLAs. AND OR
Fixed Prog.ROM
PLA Prog.Prog.
PLA (continued…) We should see PLAs as structured logic
components helping us with a reduction of size in comparison to the more general-purposed ROM ICs.
Nowadays PLA programmers use other techniques such as column sharing in order to decrease the size of PLAs even more.
PAL There is also a third kind of programmable
device with a fixed OR plane and a programmable AND plane. An example of this structure called a PAL structure can be seen below: Feedback
lineA B C D
DCBACDBA
BCDDCBAf
ABCCBfDC
f
permanentconnection
programmableconnection
PAL (continued…) As you can see in the last figure, PALs give us
the ability to share certain product terms between two particular functions. Another choice PALs give us in order to realize larger functions in the ability to feedback an output of an OR gate back into the AND plane and use it as a part of a larger function. It must be noted that a feedback line can itself be used as an output.
PAL (continued…) PALs do have a benefit with respect to PLAs
alongside all the restrictions they bring for realization of a function and that is better timing. This is because there is less delay on the OR gates of a PLA because of the fixed and rather small number of inputs to each OR gate.
Structure of PROM’s Transistors Let’s see the kind of transistors that are used
in PROMs. These transistors are called floating gate transistors and are structured as shown below:
diffdiff
floating gatemain gate
Structure of PROM’s Transistors (continued…) When such a transistor is to be disabled the
floating gate is given a high voltage that brings electrons from the two diffusion areas into it, giving it a negative charge and thus disabling the gate. Ultra violet light can be used to send these electrons back to the diffusion area.
MSI Parts as a ROM Let’s consider a 2764: In this figure the VPP
and PFM pins are used when programming the package. This package has 13 inputs that gives us 213
*8 memory locations. That is 213 addresses pointing to 8 bit words.
...
...
2764vpppfm
A0A1
A12
CSOE
o0 o1 o7
MSI Parts as a ROM (continued…) The output lines are also used as input lines
with the use of three state buffers as can be seen. When both CS and OE signals are 0, these pins act as output and otherwise can be inputs for programming.
EN
B
EN
B
EN
B
EN
B
CSOE
Cascading ROMs Standard packages need to have the ability to
cascade. ROMs are cascaded in 2 styles: The following method is called horizontal cascading
that expands our word length:
13
8
vpppfm
276413
8
vpppfm
2764
16
13
010
1
CSOE
Cascading ROMs (continued…)
The other one is called vertical cascading that expands our address space to 14 lines that is 16k, as shown in the following figure:
13
8
vpppfm
2764
OECS
13
8
vpppfm
2764
OECS
A0A1A12…A13
8
0
01
1
Cascading ROMs (continued…) Note that the programming of these packages
must be done each on its own and not in cascaded form.
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