Digital Logic Design Lecture # 11 University of Tehran.
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Transcript of Digital Logic Design Lecture # 11 University of Tehran.
Digital Logic Design
Lecture # 11University of Tehran
Outline
Encoder Verilog
Encoder We talked about using a decoder to decode a
coded number, obviously there has to also be a way of encoding data as well.
0
234567
10
234567
1
0
21
0
21
0
01
0
01
Decoder Encoder
Encoder (continued…)
I0I1I2I3
y00
23
1y1
I0I1I2I3
4d 1
0 d
000
1 5
7d d
0 d
3
2 6
01
11
10
8d 1
d d
12
13 9
11d d
d d
15
14 10
00 01 11 10
y1I0I1I2I3
4d 0
0 d
000
1 5
7d d
1 d
3
2 6
01
11
10
8d 1
d d
12
13 9
11d d
d d
15
14 10
00 01 11 10
y0
Encoder (continued…) As you can see in the last example of a binary
encoder we have only paid attention to 5 of the 16 possible inputs, them being:
I3 0 0 0 0 1I2 0 0 0 1 0I1 0 0 1 0 0 I0 0 1 0 0 0
Even this state has been set don’t care in our KM.
Encoder (continued…) Using the KM shown in the latter slides or
simply considering the fact that y0 is active when either I1 or I3 is active and a similar observation for y1 we have:
I2y1
I3
I1I3
y0
Encoder (continued…) An encoder can find other uses as well. For
instance consider a stage in a CPU’s working time when two interrupts are sent to it at the same time. One asking for the process of a key press event and the other pointing to a power failure. Obviously in such a situation the first need not be processed because the second interrupt indicates a very severe problem (specially in OSs like Linux).
Encoder (continued…) Now if in a specific problem such as what
mentioned in the last slide, there does actually occur a time when two or more of the inputs are active, we will be using a priority encoder. In such a case the input line with the higher number is chosen to be of higher priority. This means that for instance if we choose X3 as a power failure interrupt line, no other interrupt request will ever surpass it through priority.
Encoder (continued…) To design this priority encoder, consider the
following truth table and KMs:
x0
x1
x2
x3
y0
y1
GS
0
0
00
00
000 0
0
0
0
0
0
1
11
1
11
0
1
1
111
11
1
1
1
0
0
00
00
000 1
0
0
0
1
1
1
11
1
11
1
1
1
111
11
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y1 y0
0
1
10
0
0
0
0
1
1
11
1
1
1
1
GS
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x0x1x2x3
Increase of Priority
Encoder (continued…)
40 0
0 0
000
1 5
71 0
1 0
3
2 6
01
11
10
81 1
1 1
12
13 9
111 1
1 1
15
14 10
00 01 11 10
y0
X3X2
X0X1
X3X2
X0
40 1
0 1
000
1 5
70 1
0 1
3
2 6
01
11
10
81 1
1 1
12
13 9
111 1
1 1
15
14 10
00 01 11 10
y1
X1
321 xxy 1230 xxxy
Encoder (continued…) Note: When we use the shown encoder as an
interrupt handler, GS becomes active when one of the interrupt lines become active, and the interrupt number is given to the CPU through y1y0. The GS output is in fact a path through which the interrupt handler can inform the CPU of the occurrence of an interrupt request somewhere in the system.
Encoder (continued…) Now let’s see a standard encoder package
74148 which is an 8-to-3 encoder:1
A 1 NA 0 NG S NE O N
A 2 N
1 N0 N
5 N4 N3 N2 N
7 N6 N
E IN
7 4 1 4 8
E N C O D E R
Encoder (continued…) In the package 74148, the EO output (Enable
Output) will be active when none of the input lines are active (simply put there to use the extra left out pin of our IC).
Encoder (continued…) The following figure shows how we can
cascade two 4-to-2 encoders:
EI
EO
GS
01
0123
EI
EO
GS
01
0123
I0_I1_I2_I3_
I4_I5_I6_I7_
y2
_
y1
_
y0
_
Verilog In this session we want to see how to bring our
level of description higher than switch level and gate level to data flow description. Example: module MyAnd(a, b, z); input a, b;
output z;
assign #5 z=a&b;endmodule
Other logic operators can also be used in continuous assignments such as:
assign z=(a&b)|(a^b)
ab
ab
z
Verilog (continued…) The following is a code for a 4 bit adder
module: module adder(a, b, z);input [3:0] a, b;
output [3:0] z;assign z=a+b;
endmodule
Verilog (continued…) Let’s now write a test bench for the above
adder: module test_adder();reg [3:0] aa, bb;
wire [3:0] zz;adder u(aa, bb,
zz); initial begin
aa=4; bb=6;#10;end
endmodule
Verilog (continued…) The following code shows how we can work
with a part of our bus:module function(a, b, z);
input [3:0] a, b;output [3:0] z;
assign z=a+b;assign
z[3]=a[3]^b[3]; endmodule
Verilog (continued…) Example:
module adder(a, b, cin, s, cout);input [3:0] a, b;input cin;
output [3:0] s;output cout;
assign {cout, s}=a+b+cin;endmodule
The statement {cout, s}=a+b+cin; shows concatenation of s and cout, cout being MSB and s LSB.
Verilog (continued…) Let’s take a look at some examples:
A 4 bit And module:module And4bit(a, b, z);
input [3:0] a, b;output [3:0] z;assign z=a&b;
endmodule
Verilog (continued…) A comparator:
module comparator(a, b, gt, eq, lt);input [3:0] a, b;
output gt, eq, lt;assign gt=(a>b);
assign lt=(a<b);assign eq=(a==b);
endmodule
Verilog (continued…) 16 bit 2-to-1 multiplexer:
module MUX2to1(s, a, b, z);input [15:0] a, b;
input s;output [15:0] z;
assign z=(s==1)?a:b;endmodule
Verilog (continued…) 4 bit 4-to-1 multiplexer:
module MUX4to1(s, a, b, c, d, z);input [1:0] s;
input [3:0] a, b, c, d;output [3:0] z;assign z=(s[1]==1)?((s[0]==0)?a:b):
((s[0]==0)?c:d) endmodule
Verilog (continued…) Note: As we saw before we have concurrency of
statements in Verilog. This concurrency is also true about assign statements, for instance the following two assign statements resemble the circuit in the figure:
assign z=~a&b;assign y=z^b;
~ab
b
z
y