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### Transcript of Digital Logic Design Lecture # 12 University of Tehran

• Slide 1
• Digital Logic Design Lecture # 12 University of Tehran
• Slide 2
• Outline Adders Subtractor Designing Example Hard wares Using the Standard Packages ALU (Arithmetic Logic Unit) Verilog
• Slide 3
• Adders Consider the following addition process: Observing this addition as a slice by slice process, we could realize the whole process by realizing one of the slices in hardware, that is by designing a hardware that would add two bits and the carry from the last slice and generate a sum and a carry out. As we saw in the last sessions, this logic would give:
• Slide 4
• Adders (continued) And the logic diagram of our design was:
• Slide 5
• Adders (continued) As mentioned in the last session if we want to do a 4 bit addition we could simply use four full adders next to each other creating a ripple carry adder:
• Slide 6
• Adders (continued) We could use a half adder for the addition of the rightmost bit because this stages carry in as always 0. But the fact that using a half adder instead of a full adder for the first bit stage will not give us a considerable amount of extra space must be taken into consideration.
• Slide 7
• Adders (continued) Looking at our design it is rather obvious that this design could result in a very big delay time if used for a large number of bits. For instance if each and/or gate had a delay of 5 ns this would result in a 40 ns delay in a 4 bit ripple carry adder. To solve the above problem, we need a design where each cell can predict its own carry and with a timing overhead for this prediction, our result could be ready in 15 ns. This design is named carry look ahead.
• Slide 8
• Adders (continued) Another very simple method that can help in increasing speed of our addition and decreasing delay times is to make each cell a little more complex and do the addition 2 bits by 2 bits. In such a case because we still are using 2 level networks the delay on each cell will still be 10 ns. We cant use this method for larger cells than 2 bits at a time because the size of the hardware would make it impractical.
• Slide 9
• Slide 10
• Subtractor As we saw before, one of the features of the 2s complement system was that the addition and subtraction processes were very much the same. We can perform subtraction by simply inverting the bits of one operand and setting the carry in bit of the operation to 1.
• Slide 11
• Subtractor (continued) In order to be able to use one package for both addition and subtraction, we can use XOR gates as controllable inverters. These packages have the following structure:
• Slide 12
• Subtractor (continued) Lets now design a structure that can give us the and result of the two inputs or the add/sub result based on a select line.
• Slide 13
• Subtractor (continued) As you can see in the last example, four 2-to-1 multiplexers with a common select are used to give us the needed result based on the value of the select line.
• Slide 14
• Designing Example Hard wares Using the Standard Packages Lets use the packages weve seen so far to design a hardware that converts a 2s complement number to its equivalent sign and magnitude form. This means that a conversion will take place whenever the MSB is 1 that in when our number is negative (positive numbers need no conversion).
• Slide 15
• ALU (Arithmetic Logic Unit) An ALU is a component that can do both arithmetic and logic operations on its inputs. It can also have a comparator inside that gives outputs such as overflow flag, zero flag etc as well as its operation results. Note: The adders inside an ALU are usually carry look ahead adders and in order to be able to cascade adders and keep this feature in them, they have outputs that can help in prediction of the next stages carry in bits. These outputs are usually called p and g.
• Slide 16
• ALU (Arithmetic Logic Unit) (continued) 74181: In this package, four select lines choose the function performed by the ALU, as shown in the following table. This ALU has g and p outputs that keeps addition carry look ahead even after cascading.
• Slide 17
• Verilog Consider the following Verilog code: module max(a, b, z); input [3:0] a, b; output [3:0] z; assign z=(a>b)?a:b; endmodule This kind of description is called data flow description that can be given to a synthesis tool which will give us a hadware realization for it.
• Slide 18
• Verilog (continued) The following code is the code for an adder subtractor module: module addsub(a, b, select, cout, sum); input [7:0] a, b; input select; output [7:0] sum; output cout; assign {cout, sum}=select?(a-b):(a+b); endmodule
• Slide 19
• Verilog (continued) An adder with overflow detection: module adder(a, b, cin, sum, cout, ov); input [7:0] a, b; input cin; output [7:0] sum; output cout, ov; assign {cout, sum}=a+b+cin; assign ov=a&b& ~ sum | ~ a& ~ b&sum; endmodule
• Slide 20
• Verilog (continued) When writing Verilog code for different problems many a time can occur where writing assign statements using condition expressions can become very complex. In such cases always block is used. Pay attention to the following example in the next slide.
• Slide 21
• Verilog (continued) Example:module ALU(a, b, s, z); input [7:0] a, b; input [1:0] s; output [7:0] z; reg [7:0] z; always @(a, b, s) begin if (s==0) z=a+b; else if(s=1) z=a-b; else if(s=2) z=a&b; else z=a^b; end endmodule
• Slide 22
• Verilog (continued) Note: The list of variables given in parentheses in front of always @ are called the sensitivity list. As we know a combinational circuit changes its output whenever one of its inputs change, that is the inputs to that circuit are its sensitivity list. This syntax is different for sequential circuits as we will see later on.
• Slide 23
• Verilog (continued) An important issue that must be noted here is that when describing a circuit for synthesis (as the examples we saw today) we do not use any timings in our code. This is because the software is going to use certain hardware for the design and thus we are not in a situation to be able to issue any delay times. We use Verilog for two main reasons: Synthesis Modeling for simulation
• Slide 24
• Verilog (continued) When using Verilog for synthesis we do not issue delay times (that is it is ignored even if we do). But when modeling for simulation or when were using particular packages we know about, we must issue delay times in order for the simulation wave forms to be something near to results we will get in reality.