ELEN 468 Lecture 141 ELEN 468 Advanced Logic Design Lecture 14 Synthesis of Sequential Logic.

ELEN 468 Lecture 14 1

ELEN 468Advanced Logic Design

Lecture 14Synthesis of Sequential Logic


Synthesis of Sequential Logic: General

Event control of a cyclic behavior must be synchronized to a single edge of a single clockalways @ ( posedge clock )

Different behaviors may be synchronized to different clocks or different edges of a clock but clock periods should be same


Options for Implementing Sequential Logic

User-defined primitiveBehavior with timing controlsInstantiated library register cellInstantiated module


Commonly Synthesized Sequential Logic

Data registerTransparent latchShift registerBinary counterFinite state machinePulse generatorClock generator Parallel/serial converter

… …Table 9.2, page 346


Synthesis of Sequential UDPs

Only one synchronizing signal Clock level – latch Clock signal edge – flip-flop

A synthesis tool may have its own requirement For example, may constrain the order

of rows – asynchronous first


Example of Sequential UDPprimitive d_flop( q, clock, d );

output q;input clock, d;reg q;table

// clock d state q/next_state(01) 0 : ? : 0; // Parentheses indicate signal transition(01) 1 : ? : 1; // Rising clock edge(0?) 1 : 1 : 1;(0?) 0 : 0 : 0;(?0) ? : ? : -; // Falling clock edge? (??) : ? : -; // Steady clockendtable

endprimitive

clock

d qd_flop


Synthesis of Latches

Latches are incurred at Incompletely specified input

conditions for Continuous assignment -> mux with

feedback Edge-triggered cyclic behavior -> gated

datapath with register Level-sensitive cyclic behavior -> latch

Feedback loop


Latch Resulted from Unspecified Input State

module myMux( y, selA, selB, a, b );input selA, selB, a, b;output y;reg y;

always @ ( selA or selB or a or b ) case ( {selA, selB} )

2’b10: y = a;2’b01: y = b;

endcaseendmodule

module myMux( y, selA, selB, a, b );input selA, selB, a, b;output y;reg y;

always @ ( selA or selB or a or b ) case ( {selA, selB} )

2’b10: y = a;2’b01: y = b;

endcaseendmodule

b

a

selA’

selB

selA

selB’latch

yen


Latch Resulted from Feedback Loop

module latch1 ( out, in, enable );input in, enable,output out;reg out;

always @ ( enable ) begin if ( enable )

assign out = in; else

assign out = out; end

endmodule

module latch1 ( out, in, enable );input in, enable,output out;reg out;

always @ ( enable ) begin if ( enable )

assign out = in; else

assign out = out; end

endmodule

outin

enable

mux


Synthesis of Edge-triggered Flip-flops

A register variable in a behavior might be synthesized as a flip-flop if It is referenced outside the scope of

the behavior Referenced within the behavior before

it is assigned value Assigned value in only some branches

of the activity


Event Control Sensitive to Multiple Signal Edges

module DReg ( out, in, clock, reset );input in, clock, reset;output out;register out;

always @ ( posedge clock or posedge reset ) begin

if ( reset == 1’b1 ) out = 0;else out = in;

endendmodule

module DReg ( out, in, clock, reset );input in, clock, reset;output out;register out;

always @ ( posedge clock or posedge reset ) begin

if ( reset == 1’b1 ) out = 0;else out = in;

endendmodule• The decoding of signals immediately after the event control tells the synthesis tool how to distinguish control signals from synchronizing signal

• The control signals must be decoded explicitly in the branches of the if statement


Registered Combinational Logic

module reg_and ( y, a, b, c, clk );

input a, b, c, clk;

output y;

reg y;

always @ ( posedge clk )

y = a & b & c;endmodule

module reg_and ( y, a, b, c, clk );input a, b, c, clk;

output y;

reg y;

always @ ( posedge clk )

y = a & b & c;

endmoduley

clk

a

cb


Shift Registermodule shift4 ( out, in, clock, reset );

input in, clock, reset;output out;reg [3:0] data_reg;

assign out = data_reg[0];

always @ ( negedge reset or posedge clock )begin if ( reset == 1’b0 ) data_reg = 4’b0; else data_reg = { in, data_reg[3:1] };

endendmodule

module shift4 ( out, in, clock, reset );input in, clock, reset;output out;reg [3:0] data_reg;

assign out = data_reg[0];

always @ ( negedge reset or posedge clock )begin if ( reset == 1’b0 ) data_reg = 4’b0; else data_reg = { in, data_reg[3:1] };

endendmodule

Figure 9.10, page 361


Countermodule ripple_counter ( count, clock, toggle, reset );

input clock, toggle, reset; output [3:0] count; reg [3:0] count; wire c0, c1, c2;assign c0 = count[0]; assign c1 = count[1]; assign c2 = count[2];always @ ( posedge reset or posedge clock ) if ( reset == 1’b1 ) count[0] = 1’b0; else if ( toggle == 1’b1 ) count[0] = ~count[0];always @ ( posedge reset or negedge c0 ) if ( reset == 1’b1 ) count[1] = 1’b0; else if ( toggle == 1’b1 ) count[1] = ~count[1];always @ ( posedge reset or negedge c1 ) if ( reset == 1’b1 ) count[2] = 1’b0; else if ( toggle == 1’b1 ) count[2] = ~count[2];always @ ( posedge reset or negedge c2 ) if ( reset == 1’b1 ) count[3] = 1’b0; else if ( toggle == 1’b1 ) count[3] = ~count[3];

endmodule

module ripple_counter ( count, clock, toggle, reset );input clock, toggle, reset; output [3:0] count; reg [3:0] count; wire c0, c1, c2;assign c0 = count[0]; assign c1 = count[1]; assign c2 = count[2];always @ ( posedge reset or posedge clock ) if ( reset == 1’b1 ) count[0] = 1’b0; else if ( toggle == 1’b1 ) count[0] = ~count[0];always @ ( posedge reset or negedge c0 ) if ( reset == 1’b1 ) count[1] = 1’b0; else if ( toggle == 1’b1 ) count[1] = ~count[1];always @ ( posedge reset or negedge c1 ) if ( reset == 1’b1 ) count[2] = 1’b0; else if ( toggle == 1’b1 ) count[2] = ~count[2];always @ ( posedge reset or negedge c2 ) if ( reset == 1’b1 ) count[3] = 1’b0; else if ( toggle == 1’b1 ) count[3] = ~count[3];

endmodule

Fig. 9.14

Page 366


Synthesis of Explicit Finite State Machines

A behavior describing the synchronous activity may contain only one clock-synchronized event control expressionThere is always one and only one explicitly declared state registerState register must be assigned value as an aggregate, bit select and part select assignments to state register is not allowedAsynchronous control signals must be scalars in the event control expression of behaviorValue assigned to state register must be constant or a variable that evaluates to a constant


Comparison of Explicit and Implicit FSMs

Explicit FSM Implicit FSM

Explicit State Register

Yes No

State Encoding Yes No

Sequence of States

Specified Implicit

Sequence Control

Explicit assignment to state register

Specified by procedural

flow


State Encoding Example

# Binary Gray Johnson One-hot

0 000 000 0000 00000001

1 001 001 0001 00000010

2 010 011 0011 00000100

3 011 010 0111 00001000

4 100 110 1111 00010000

5 101 111 1110 00100000

6 110 101 1100 01000000

7 111 100 1000 10000000

Same number of bits as binary Two adjacent codes only differ by one bit


State EncodingA state machine having N states will require at least log2N bits register to store the encoded representation of statesBinary and Gray encoding use the minimum number of bits for state registerGray and Johnson code: Two adjacent codes differ by only one bit

Reduce simultaneous switching Reduce crosstalk Reduce glitch


One-hot EncodingEmploy one bit register for each stateLess combinational logic to decodeConsume greater area, does not matter for certain hardware such as FPGAEasier for design, friendly to incremental change case and if statement may give different result for one-hot encoding Runs faster ‘define state_0 3’b001

‘define state_1 3’b010‘define state_2 3’b100

‘define state_0 3’b001‘define state_1 3’b010‘define state_2 3’b100


Rules for Implicit State Machines

… …always @ ( posedge clock ); begin

a <= b;c <= d;

@( negedge clock ) begin e <= f; g <= h; end

end… …

… …always @ ( posedge clock ); begin

a <= b;c <= d;

@( negedge clock ) begin e <= f; g <= h; end

end… …

Synchronizing signals have to be aligned to the same clock edge in an implicit FSM, the following Verilog code will not synthesize


Resets

Strongly recommended that every sequential circuit has a reset signalAvoid uncertain initial statesSpecification for output under reset should be complete, otherwise wasted logic might be generated


Gated Clock

Pro: reduce power consumptionCon: unintentional skew

data

clock

clock_enable

Q

flip-flop


Design Partitions

Partition cells such that connections between partitions is minimum

1

2

3

a

b

c

1

2

3

a

c

b


Example: Sequence Detector

Single bit serial input Synchronized to falling edge of clock

Single bit output Assert if two or more successive 0 or 1 at input Active on rising edge of clock

ClockInput

Output


State Transition Diagram

State0

Start state

State1

Input 0

State2

Input 1

0/0 1/0

0/11/1

1/0

0/0

ELEN 468 Lecture 141 ELEN 468 Advanced Logic Design Lecture 14 Synthesis of Sequential Logic.

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