ADVANCED VLSI CHAP6-3

7/28/2019 ADVANCED VLSI CHAP6-3

1/43

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

Topics

Memories:

ROM;

SRAM;

DRAM;

Flash.

Image sensors.

FPGAs.

PLAs.


2/43


High-density memory

architecture


3/43


Memory operation

Address is divided into row, column.

Row may contain full word or more than one

word.

Selected row drives/senses bit lines in

columns.

Amplifiers/drivers read/write bit lines.


4/43


Read-only memory (ROM)

ROM core is organized as NOR gates

pulldown transistors of NOR determine

programming.

Erasable ROMs require special processing

that is not typically available.

ROMs on digital ICs are generally mask-programmedplacement of pulldowns

determines ROM contents.


5/43


ROM core circuit


6/43


Static RAM (SRAM)

Core cell uses six-transistor circuit to store

value.

Value is stored symmetricallyboth true

and complement are stored on cross-

coupled transistors.

SRAM retains value as long as power isapplied to circuit.


7/43


SRAM core cell


8/43


SRAM core operation

Read:

precharge bit and bit high;

set select line high from row decoder;

one bit line will be pulled down.

Write:

set bit/bit to desired (complementary) values;

set select line high;

drive on bit lines will flip state if necessary.


9/43


SRAM sense amp


10/43


Sense amp operation

Differential pairtakes advantage of

complementarity of bit lines.

When one bit line goes low, that arm of diff

pair reduces its current, causing

compensating increase in current in other

arm. Sense amp can be cross-coupled to increase

speed.


11/43


3-transistor dynamic RAM

(DRAM)

First form of DRAMmodern commercial

DRAMs use one-transistor cell.

3-transistor cell can easily be made with a

digital process.

Dynamic RAM loses value due to charge

leakagemust be refreshed.


12/43


3-T DRAM core cell


13/43


3-T DRAM operation

Value is stored on gate capacitance of t1.

Read:

read = 1, write = 0, read_data is precharged;

t1will pull down read_data if 1 is stored.

Write:

read = 0, write = 1, write_data = value;

guard transistor writes value onto gate

capacitance.


14/43


3-T DRAM operation

Value is stored on gate capacitance of t1.

Read:

read = 1, write = 0, read_data is precharged;

t1will pull down read_data if 1 is stored.

Write:

read = 0, write = 1, write_data = value;

guard transistor writes value onto gate

capacitance.


15/43


1-T DRAM

Word line controls

pass transistor.

Pass transistor guardsaccess to capacitor.

Read is destructive.


16/43


Stacked capacitor DRAM


17/43


Trench capacitor DRAM


18/43


Floating gate transistor

Poly 1 gate is not

connected.

Schematic symbol:

p

n+ n+

poly 1

poly 2 SiO2


19/43


Fowler-Nordheim tunneling

p

n+ n+

poly 1

poly 2 SiO2

n-well

n+p+

floating

- -

+20 V


20/43


Fowler-Nordheim erasing

p

n+ n+

poly 1

poly 2 SiO2

n-well

n+p+

floating floating- -

+20 V


21/43


NOR flash architecture

Same as NOR ROM

but with floating gate

pulldowns.

pullup

+


22/43


NAND flash architecture

Want to provide

banked memory for

higher datathroughput.

Widely used for data

storage.

Likely to become

standard architecture.

bank

0

bank

1

bank

2

bank

3

address

data

address 1address 2

data 1 data 2


23/43


2-bit NAND flash cell

bit

n+ source

Select bottom

Select top

RA0

RA1


24/43


NAND flash cell programming

bit

Select bottom

Select top

RA0

RA1

+20V

+20V

+5V

0V

+7V

Row not

programmed


25/43


Wear in flash memory

Write cycles slowly damage devices.

Limited number of write cycles: 10,000.

Software balances utilization of locations to

level wear across the device.


26/43


Image sensors

Two major types of image sensors:

Charge-coupled device (CCD) requires

specialized fabrication steps.CMOS image sensor uses standard CMOS

technology, perhaps with low-noise

modifications.

CMOS image sensor is an array circuit

similar to a RAM.


27/43


Photodiodes

Photodiode turns

photons into electrons.

Photocurrent density:

photons+

n

p

x1

x2

x3


28/43


Active pixel sensor (APS) circuit


29/43


APS column


30/43


SRAM-based FPGAs

Program logic functions, interconnect using

SRAM.

Advantages:

dynamically reconfigurable;

uses standard processes.

Disadvantages:

SRAM burns power.

Possible to steal, disrupt configuration bits.


31/43


Logic elements

Logic element includes combinational

function + register(s).

Use SRAM as lookup table forcombinational function.


32/43


LUT-based logic element

Lookup

table

configuration

bits

out

inputs

Can multiplex at output or address at input


33/43


Example

1, 1, 1, 1, 1, 1, 1, 0

111

0, 1, 1, 0, 1, 0, 0, 1

111

0 1


34/43


Evaluation of SRAM-based LUT

N-input LUT can handle function of 2n

inputs.

All logic functions take the same amount ofspace.

SRAM is larger than static gate equivalent

of function.

Burns power at idle.


35/43


Static CMOS gate vs. LUT

Number of transistors:NAND/NOR gate has 2n transistors.

4-input LUT has 128 transistors in SRAM, 96 inmultiplexer.

Delay: 4-input NAND gate has 9t delay.

SRAM decoding has 21t delay.

Power: Static gates power depends on activity.

SRAM always burns power.


36/43


Registers in logic elements

Want to selectively add register to LE:

Comb

logicD Q

Configuration bit

LE out


37/43


Other LE features

Multiple logic functions in an LE.

Addition logic:

carry chain.


38/43


Programmable interconnect

MOS switch controlled by configuration bit:

D Q

Programmable vs fixed


39/43


Programmable vs. fixed

interconnect

Switch adds delay.

Transistor off-state is worse in advanced

technologies.

FPGA interconnect has extra length = added

capacitance.


40/43


Programmable logic array (PLA)

Used to implement specialized logic

functions.

A PLA decodes only some addresses (inputvalues); a ROM decodes all addresses.

PLA not as common in CMOS as in nMOS,

but is used for some logic functions.


41/43


PLA organization

AND plane OR plane

p1

p2

p3

p4

f0 f1i0 i0 i1 i1product term


42/43


PLA structure

AND plane, OR plane, inverters together

form complete two-level logic functions.

Both AND and OR planes are implementedas NOR circuits.

Pulldown transistors form

programming/personality of PLA.Transistors may be referred to as

programming tabs.


43/43

PLA AND/OR cell

programming

tab

no tab

VSS

input 1 input 2

output 1

output 2

ADVANCED VLSI CHAP6-3

Documents

Transcript of ADVANCED VLSI CHAP6-3