Spring 08, Mar 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring...

Spring 08, Mar 13Spring 08, Mar 13 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2008Spring 2008VLSI Test PrinciplesVLSI Test Principles

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html


ReferenceReference

M. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Essentials of Electronic Testing for Digital, Memory and Mixed-Signal Electronic Testing for Digital, Memory and Mixed-Signal VLSI CircuitsVLSI Circuits, Springer, 2000., Springer, 2000.


Testing and DiagnosisTesting and Diagnosis

TestingTesting Determine whether of not a device is faulty.Determine whether of not a device is faulty. Accomplished through input-output experiment.Accomplished through input-output experiment.

DiagnosisDiagnosis Given a device has failed, locate the fault that caused Given a device has failed, locate the fault that caused

failurefailure Accomplished by analysis of test data and by intrusive Accomplished by analysis of test data and by intrusive

experiments.experiments.


Principle of TestingPrinciple of Testing


Automatic Test Equipment (ATE)Automatic Test Equipment (ATE) Consists of:Consists of:

Powerful computerPowerful computer Powerful 32-bit Powerful 32-bit Digital Signal ProcessorDigital Signal Processor (DSP) (DSP)

for analog testingfor analog testing Test Program (written in high-level language) Test Program (written in high-level language)

running on the computerrunning on the computer Probe Head (actually touches the bare or Probe Head (actually touches the bare or

packaged chip to perform fault detection packaged chip to perform fault detection experiments)experiments)

Probe CardProbe Card or or Membrane ProbeMembrane Probe (contains (contains electronics to measure signals on chip pin or electronics to measure signals on chip pin or pad)pad)


ADVANTEST Model T6682 ATEADVANTEST Model T6682 ATE


LTX FUSION HF ATELTX FUSION HF ATE


Cost of Manufacturing Test (2000AD)Cost of Manufacturing Test (2000AD) ATE purchase price: analog instruments, 1,024 ATE purchase price: analog instruments, 1,024

digital pins (0.5-1.0GHz)digital pins (0.5-1.0GHz)= $1.2M + 1,024 x $3,000 = $4.272M= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)Running cost (five-year linear depreciation)= = Depreciation + Maintenance + OperationDepreciation + Maintenance + Operation

= $0.854M + $0.085M + $0.5M= $0.854M + $0.085M + $0.5M

= $1.439M/year= $1.439M/year

Test cost (24 hour ATE operation)Test cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= $1.439M/(365 x 24 x 3,600)

= 4.5 cents/second= 4.5 cents/second


A Modern VLSI DeviceA Modern VLSI DeviceSystem-on-a-chip (SOC)System-on-a-chip (SOC)

DSPcore

RAMROM

Interfacelogic

Mixed-signalCodec

Dataterminal

Transmissionmedium


Testing as Filter ProcessTesting as Filter Process

All fabricatedchips

Good chips

Defective chips

Prob(good) = Y

Prob(bad) = 1 – Y

Prob(pass test) = high

Prob(fail test) = high

Prob(fail test) = low

Prob(pass test) =

low

Mostlygoodchips

Mostlybad

chips


VLSI Chip YieldVLSI Chip YieldVLSI Chip YieldVLSI Chip Yield A manufacturing defect is a finite chip area with A manufacturing defect is a finite chip area with

electrically malfunctioning circuitry caused by electrically malfunctioning circuitry caused by errors in the fabrication process.errors in the fabrication process.

A chip with no manufacturing defect is called a A chip with no manufacturing defect is called a good chip.good chip.

Fraction (or percentage) of good chips produced in Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield a manufacturing process is called the yield. Yield is denoted by symbol is denoted by symbol YY..

Cost of a chip:Cost of a chip:

Cost of fabricating and testing a wafer

Yield × Number of chip sites on the wafer


Clustered VLSI DefectsClustered VLSI DefectsClustered VLSI DefectsClustered VLSI Defects

WaferDefects

Faulty chips

Good chips

Unclustered defectsWafer yield = 12/22 = 0.55

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77


Yield ParametersYield ParametersYield ParametersYield Parameters Defect density (d ) = Average number of defects per unit

of chip area Chip area (A ) Clustering parameter () Negative binomial distribution of defects,

p (x ) = Prob(number of defects on a chip = x )

Γ (α +x ) (Ad / α) x

= . x ! Γ (α) (1+Ad / α) α+x

where Γ is the gamma function

α = 0, p (x ) is a delta function (max. clustering)

α = , p (x ) is Poisson distr. (no clustering, William/Brown)


Yield EquationYield EquationYield EquationYield Equation

Y = Prob( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / α ) – α

Example: Ad = 1.0, α = 0.5, Y = 0.58

Unclustered defects: α = , Y = e – Ad

Example: Ad = 1.0, α = , Y = 0.37

too pessimistic !


Defect Level or Reject RatioDefect Level or Reject RatioDefect Level or Reject RatioDefect Level or Reject Ratio Defect level (DL) is the ratio of faulty chips among the

chips that pass tests. DL is measured as defective parts per million (dpm, or

simply ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured

product quality: For commercial VLSI chips a DL higher than 500 dpm is

considered unacceptable. Chip manufacturers strive for much lower defect levels. Below

100 dpm means high quality. Zero-defects refers to 3.4 or lower dpm.


Determination of Determination of DLDLDetermination of Determination of DLDL

From field return data: Chips failing in the field From field return data: Chips failing in the field are returned to the manufacturer. The number are returned to the manufacturer. The number of returned chips normalized to one million chips of returned chips normalized to one million chips shipped is the shipped is the DLDL..

From test data: Fault coverage of tests and chip From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the is fitted to the fallout data to estimate the DLDL..


Modified Yield EquationModified Yield EquationModified Yield EquationModified Yield Equation Three parameters:Three parameters:

Fault density, Fault density, ff = average number of stuck-at faults = average number of stuck-at faults per unit chip areaper unit chip area

Fault clustering parameter, Fault clustering parameter, Stuck-at fault coverage, Stuck-at fault coverage, TT

The modified yield equation:The modified yield equation:

Y (T ) = (1 + TAf / β) – β

Assuming that tests with 100% fault coverage(T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / β) – β


Defect LevelDefect LevelDefect LevelDefect Level Y (T ) – Y (1)DL (T ) =

Y (T )

( β + TAf ) β

= 1 –

( β + Af ) β

Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.

, Y (T ) = e –TAf and DL(T ) = 1 – Y (1)1 –T


Example: SEMATECH ChipExample: SEMATECH ChipExample: SEMATECH ChipExample: SEMATECH Chip Bus interface controller ASIC fabricated and tested at Bus interface controller ASIC fabricated and tested at

IBM, Burlington, VermontIBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O304-pin package, 249 I/O Clock: 40MHz, some parts 50MHzClock: 40MHz, some parts 50MHz 0.80.8 CMOS, 3.3V, 9.4mm x 8.8mm area CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverageFull scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz Advantest 3381 ATE, 18,466 chips tested at 2.5MHz

test clocktest clock Data obtained courtesy of Phil Nigh (IBM)Data obtained courtesy of Phil Nigh (IBM)


Test Coverage from Fault SimulatorTest Coverage from Fault SimulatorTest Coverage from Fault SimulatorTest Coverage from Fault Simulator

Stu

ck-a

t fa

ult

co

vera

ge

Vector number, V


Measured Chip FalloutMeasured Chip FalloutMeasured Chip FalloutMeasured Chip Fallout

Vector number, V

Mea

sure

d c

hip

fal

lou

t


Model FittingModel FittingModel FittingModel Fitting

Clustered faults:1 – (1+TAf/β)– β

Af = 2.1, β = 0.083

Measured chip fallout

Y (1) = 0.7623

Ch

ip f

allo

ut

and

co

mp

ute

d

1-Y

(T

)

Stuck-at fault coverage, T

Unclustered faults:1 – e– TAf

Af = 0.31, β = Y (1) = 0.7348


Computed Defect LevelComputed Defect LevelComputed Defect LevelComputed Defect LevelD

efec

t le

vel

(dp

m)

Stuck-at fault coverage (%)

Clustered faults, β = 0.083

Unclustered faults, β =

(1 – 0.7623)×106

(1 – 0.7348)×106


Fault ModelingFault Modeling


Why Model Faults?Why Model Faults?

I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing)

Real defects (often mechanical) too numerous and often not analyzable

A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments


Some Real Defects in ChipsSome Real Defects in Chips Processing defects

Missing contact windows Parasitic transistors Oxide breakdown . . .

Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) . . .

Time-dependent failures Dielectric breakdown Electromigration . . .

Packaging failures Contact degradation Seal leaks . . .

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981.


Observed PCB DefectsObserved PCB Defects

Defect classes

ShortsOpensMissing componentsWrong componentsReversed componentsBent leadsAnalog specificationsDigital logicPerformance (timing)

Occurrence frequency (%)

51 1 613 6 8 5 5 5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.


Common Fault ModelsCommon Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more details of fault models, see

M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000.


Single Stuck-at FaultSingle Stuck-at Fault Three properties define a single stuck-at fault

Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

a

b

c

d

e

f

10

g h i 1

s-a-0j

k

z

0(1)1(0)

1

Test vector for h s-a-0 fault

Good circuit valueFaulty circuit value


Fault EquivalenceFault Equivalence Number of fault sites in a Boolean gate circuit is

= #PI + #gates + # (fanout branches) Fault equivalence: Two faults f1 and f2 are equivalent

if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the

corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can

be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.


Equivalence RulesEquivalence Rules

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0

sa1

sa0

sa1

sa0

sa0sa1

sa1

sa0

sa0

sa0sa1

sa1

sa1

AND

NAND

OR

NOR

WIRE

NOT

FANOUT


Equivalence ExampleEquivalence Example

sa0 sa1sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

Faults in boldfaceremoved byequivalencecollapsing

20Collapse ratio = ── = 0.625 32


Fault DominanceFault Dominance If all tests of some fault F1 detect another fault F2, then

F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1,

then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient

to consider only the input faults of Boolean gates. See the next example.

In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.

If two faults dominate each other then they are equivalent.


Dominance ExampleDominance Example

s-a-1F1

s-a-1F2 001

110 010 000101 100

011

All tests of F2

Only test of F1s-a-1

s-a-1

s-a-1s-a-0

A dominance collapsed fault set


Dominance ExampleDominance Example

sa0 sa1sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

Faults in orangeremoved byequivalencecollapsing

15Collapse ratio = ── = 0.47 32

Faults in green removed bydominancecollapsing


CheckpointsCheckpoints Primary inputs and fanout branches of a

combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all

single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.

Total fault sites = 16

Checkpoints ( ) = 10


Classes of Stuck-at FaultsClasses of Stuck-at Faults

Following classes of single stuck-at faults are identified by fault simulators:

Potentially-detectable fault – Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability.

Initialization fault – Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault.

Hyperactive fault – Fault induces much internal signal activity without reaching PO.

Redundant fault – No test exists for the fault. Untestable fault – Test generator is unable to find a test.


Multiple Stuck-at FaultsMultiple Stuck-at Faults A multiple stuck-at fault means that any set of

lines is stuck-at some combination of (0,1) values.

The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1.

A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.

Statistically, single fault tests cover a very large number of multiple faults.


Transistor (Switch) FaultsTransistor (Switch) Faults

MOS transistor is considered an ideal switch and two types of faults are modeled:

Stuck-open – a single transistor is permanently stuck in the open state.

Stuck-short – a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the

measurement of quiescent current (IDDQ).


Stuck-Open ExampleStuck-Open Example

Two-vector s-op testcan be constructed byordering two s-at testsA

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test for A s-a-0(Initialization vector)

Vector 2 (test for A s-a-1)


Stuck-Short ExampleStuck-Short Example

A

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-short

1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector for A s-a-0

IDDQ path in

faulty circuit


SummarySummary Fault models are analyzable approximations of defects

and are essential for a test methodology. For digital logic single stuck-at fault model offers best

advantage of tools and experience. Many other faults (bridging, stuck-open and multiple

stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent

faults require special tests. Memory and analog circuits need other specialized fault

models and tests.


Review ExerciseReview Exercise What are three most common types of blocks a modern

SOC is likely to have – analog circuit, digital logic, fluidics, memory, MEMS, optics, RF?

The cost of a chip is $1.00 when its yield is 50%. What will be its cost if you could increased the yield to 80%.

What is the total number of single stuck-at faults, counting both stuck-at-0 and stuck-at-1, in the following circuit?


AnswersAnswers What are three most common types of blocks a modern

SOC is likely to have – analog circuit, digital logic, fluidics, memory, MEMS, optics, RF.

The cost of a chip is US$1.00 when its yield is 50%. What will be its cost if you increased the yield to 80%.

Assume a wafer has n chips, then

wafer costChip cost = ──────── = $1.00

0.5 × n

Wafer cost = 0.5n × $1.00 = 50n cents

For yield = 0.8, chip cost = wafer cost / (0.8n) = 50n / (0.8n) = 62.5 cents


Answers ContinuedAnswers Continued What is the total number of single stuck-at faults, counting

both stuck-at-0 and stuck-at-1, in the following circuit?

Counting two faults on each line,

Total number of faults = 2 × (#PI + #gates + #fanout branches)

= 2 × (2 + 2 + 2) = 12

s-a-0 s-a-1

s-a-0 s-a-1 s-a-0 s-a-1s-a-0 s-a-1

s-a-0 s-a-1

s-a-0 s-a-1

Spring 08, Mar 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring...

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