ADVANCED VLSI CHAP3-4

7/28/2019 ADVANCED VLSI CHAP3-4

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Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf

Topics

n Pseudo-nMOS gates.

n DCVS logic.

n Domino gates.

n Design-for-yield.

n

Gates as IP.


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Pseudo-nMOS

n Uses a p-type as a resistive pullup, n-type

network for pulldowns.


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Characteristics

n Consumes static power.

n Has much smaller pullup network than

static gate.

n Pulldown time is longer because pullup is

fighting.


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Output voltages

n Logic 1 output is always at VDD.

n Logic 0 output is above Vss.

n VOL = 0.25 (VDD - VSS) is one plausible

choice.


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Producing output voltages

n For logic 0 output, pullup and pulldown

form a voltage divider.

n Must choose n, p transistor sizes to create

effective resistances of the required ratio.

n Effective resistance of pulldown network

must be comptued in worst caseseries n-types means larger transistors.


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Transistor ratio calculation

n In steady state logic 0 output:

pullup is in linear region,Vds = Vout - (VDD -

VSS) ;

pulldown is in saturation.

n Pullup and pulldown have same current

flowing through them.


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Transistor ratio, contd.

n Equate two currents:

Idp = Idd.

n Using 0.5 mm parameters, 3.3V power

supply:

Wp/Lp / Wn/Ln = 3.9.


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DCVS logic

n DCVSL = differential cascode voltage

logic.

n Static logicconsumes no dynamic power.

n Uses latch to compute output quickly.

n Requires true/complement inputs, produces

true/complement outputs.


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DCVS structure


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DCVS operation

n Exactly one of true/complement pulldown

networks will complete a path to the power

supply.

n Pulldown network will lower output

voltage, turning on other p-type, which also

turns off p-type for node which is goingdown.


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DCVS example


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Precharged logic

n Precharged logic uses stored charge to help

evaluation.

n Precharge node, selectively discharge it.

n Take advantage of higher speed of n-types.

n Requires multiple phases for evaluation.


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Domino logic

n Uses precharge clock to compute output in

two phases:

precharge;

evaluate.

n Is not a complete logic familycannot

invert.


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Domino gate structure


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Domino phases

n Controlled by clock.

n Precharge:p-type pullup precharges the

storage node; inverter ensures that outputgoes low.

n Evaluate: storage node may be pulled down,

so output goes up.


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Domino buffer

n Output inverter is needed for two reasons:

make sure that outputs start low, go high so that

domino output can be connected to anotherdomino gate;

protects storage node from outside influence.


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Domino operation


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Domino effect

Gate outputs fall in sequence:

gate 1 gate 2 gate 3


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Monotonicity

n Domino gates inputs must be monotonically

increasing: glitch causes storage node to

discharge.


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Output buffer

n Inverting buffer isolates storage node.

Storage node and inverter have correlated

values.


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Using domino logic

n Can rewrite logic expression using De

Morgans Laws:

(a + b) = ab

(ab) = a + b

n Add inverters to network inputs/outputs as

required.


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Design-for-yield

n Design processes that improve chip yield in

very deep submicron/nanometer

technologies.n Must treat design and manufacturing as a

unified processing to maximize yield in

nanometer technologies.


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Variations in manufacturing

n Three types of variations:

Systematic variations can be predicted based on

design and mask information plusmanufacturing equipment.

Random variations include variations in

parameters, etc.

Environmental variations include temperature,

etc.


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Trends in manufacturing

n Larger variations in process and circuit

parameters.

n Higher leakage currents.

n Patterning problems caused by specific

combinations of geometric features.

n Metal width and thickness variations.

n Stress in vias.


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Gates as IP

n The standard cell library was one of the first

forms of IP.

Reusable across many chips.

Portable from one process to another.

n Standard cell compatibility issues:

Layout: cell size, pin placement.

Delay: driving specified load.

Power consumption.


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Standard cell physical design

n Basic cell organization is dictated by

placement and routing system.

n All cells are the same height.

May be one of a set of standard widths.

n Pins must be placed on routing grid, usually

determined by wiriing layers used.


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Standard cell logical design

n Must support a Boolean complete set of

functions.

n Should support enough gate types for goodlogic synthesis results.

n Need several electrical variations of each

function:Low power.

High speed.


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Cell verification and qualification

n Cells are verified by layout extraction and

circuit simulation.

Simulate a variety of process parametercombinations.

n Qualification requires fabrication of cells on

the target process.

ADVANCED VLSI CHAP3-4

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