ADVANCED VLSI CHAP1-1

7/28/2019 ADVANCED VLSI CHAP1-1

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Modern VLSI Design 4e: Chapter 1 Copyright 2008 Prentice Hall

Overview

Why VLSI?

Moores Law.

The VLSI design process.

IP-based design.


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Why VLSI?

Integration improves the design:

lower parasitics = higher speed;

lower power;

physically smaller.

Integration reduces manufacturing cost-

(almost) no manual assembly.


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VLSI and you

Microprocessors:

personal computers;

microcontrollers.

DRAM/SRAM.

Special-purpose processors.


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Moores Law

Gordon Moore: co-founder of Intel.

Predicted that number of transistors per chip

would grow exponentially (double every 18months).

Exponential improvement in technology is a

natural trend: steam engines, dynamos,automobiles.


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Moores Law plot


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Moores Law and Intel

processors


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Moore/Intel log scale


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Terminology

Manufacturing node: technology at a

particular channel length.

Deep submicron technology: 250-100 nm.

Nanometer technology: 100 nm and below.


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The cost of fabrication

Current cost: $4 billion.

Typical fab line occupies about 1 city block,

employs a few hundred people.

Most profitable period is first 18 months-2

years.


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Cost factors in ICs

For large-volume ICs:

packaging is largest cost;

testing is second-largest cost.

For low-volume ICs, design costs may

swamp all manufacturing costs.


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Cost of design

Design cost can be significant: $20 million

for a large ASIC, $500 million for a large

CPU. Cost elements:

Architects, logic designers, etc.

CAD tools.

Computers the CAD tools run on.


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Intellectual property

Intellectual property (IP): pre-designed

components.

May come from outside vendors, internalsources.

IP saves time, design cost.

IP blocks must be designed to be reused.


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Reliability

Nanometer technologies require attention to

reliability.

Design-for-manufacturing (DFM) anddesign-for-yield (DFY) techniques adjust

the design to improve yield.

Circuit and architecture techniques cancompensate for unreliable components.


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The VLSI design process

May be part of larger product design.

Major levels of abstraction:

specification;

architecture;

logic design;

circuit design;

layout.


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Dealing with complexity

Divide-and-conquer: limit the number of

components you deal with at any one time.

Group several components into largercomponents:

transistors form gates;

gates form functional units;

functional units form processing elements;

etc.


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Hierarchical name

Interior view of a component:

components and wires that make it up.

Exterior view of a component = type:

body;

pins.

Fulladder

a

bcin

sum

cout


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A hierarchical logic design

z

box1 box2 x


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Net lists and component lists

Net list:

net1: top.in1 in1.in

net2: i1.out xxx.Btopin1: top.n1 xxx.xin1

topin2: top.n2 xxx.xin2

botin1: top.n3 xxx.xin3

net3: xxx.out i2.in

outnet: i2.out top.out

Component list:

top: in1=net1 n1=topin1

n2=topin2 n3=topineout=outnet

i1: in=net1 out=net2

xxx: xin1=topin1

xin2=topin2xin3=botin1 B=net2

out=net3

i2: in=net3 out=outnet


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Component hierarchy

top

i1 xxx i2


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Hierarchical names

Typical hierarchical name:

top/i1.foo

component pin


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Layout and its abstractions

Layout for dynamic latch:


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Stick diagram


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Transistor schematic


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Mixed schematic

inverter


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Levels of abstraction

Specification: function, cost, etc.

Architecture: large blocks.

Logic: gates + registers.

Circuits: transistor sizes for speed, power.

Layout: determines parasitics.


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Circuit abstraction

Continuous voltages and time:


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Digital abstraction

Discrete levels, discrete time:


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Register-transfer abstraction

Abstract components, abstract data types:

+

+

0010

0001

0100

0011


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Top-down vs. bottom-up design

Top-down design adds functional detail.

Create lower levels of abstraction from upper

levels.

Bottom-up design creates abstractions from

low-level behavior.

Good design needs both top-down andbottom-up efforts.


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Design abstractions

specification

behavior

register-

transfer

logic

circuit

layout

English

Executable

program

Sequential

machines

Logic gates

transistors

rectangles

Throughput,

design time

Function units,

clock cycles

Literals,

logic depth

nanoseconds

microns

function cost


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Design validation

Must check at every step that errors havent

been introduced-the longer an error remains,

the more expensive it becomes to remove it. Forward checking: compare results of less-

and more-abstract stages.

Back annotation: copy performancenumbers to earlier stages.


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Manufacturing test

Not the same as design validation: just

because the design is right doesnt mean

that every chip coming off the line will beright.

Must quickly check whether manufacturing

defects destroy function of chip. Must also speed-grade.


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IP-based design

Almost every chip uses some form of IP:

Standard cell libraries.

Memories.

IP blocks.

Designers must know how to:

Create IP.

Use IP.


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Types of IP

Hard IP:

Pre-designed layout.

Allows more detailed characterization.

Soft IP:

No layout---logic synthesis, etc.

IP layout is created by the IP user.


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Hard IP

Must conform to many standards:

Layout pin placement.

Layer usage.

Transistor sizing.

Hard IP blocks are usually qualified on a

particular process.Component is fabricated and tested to show that

the IP works on that fab line.


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Soft IP

Conformance of layout to local standards is

easier since it is created by the user.

Timing can only be estimated until thelayout is done.

Must conform to interface standards.

A wrapper adapts a block to a new interface.


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IP across the design hierarchy

Standard cells.

Pitch matched in rows, compatible drive.

Register-transfer modules.

Memories.

CPUs.

Busses.

I/O devices.


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Specifying IP

Hard or soft?

Functionality.

Performance, including process corners.

Power consumption.

Special process features required.


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The I/O lifecycle

spec

HDL design

validation documentationextraction

qualification

IP

moduleschip design

IP

database

IPdocs


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Using IP

May come from vendor, open source, or

internal group.

Must identify candidate IP, evaluate forsuitability.

May have to pay for IP.

May want to qualify IP before use,particularly if it pushes analog

characteristics.

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