ADVANCED VLSI CHAP2-4

7/28/2019 ADVANCED VLSI CHAP2-4

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Modern VLSI Design 4e: Chapter 2 Copyright 2008 Prentice Hall PTR

Topics

SCMOS scalable design rules.

Reliability.

Stick diagrams.


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MOSIS SCMOS design rules

Designed to scale across a wide range of

technologies.

Designed to support multiple vendors.

Designed for educational use.

Ergo, fairly conservative.


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and design rules

is the size of a minimum feature.

Specifying particularizes the scalable

rules.

Parasitics are generally not specified in

units


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Wires

metal 36

metal 23

metal 13

pdiff/ndiff3

poly2


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Transistors

2

3

1

32

5


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Vias

Types of via: metal1/diff, metal1/poly,

metal1/metal2.

4

1

4

2


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Metal 3 via

Type: metal3/metal2.

Rules:

cut: 3 x 3

overlap by metal2: 1

minimum spacing: 3

minimum spacing to via1: 2


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Tub tie

4

1


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Spacings

Diffusion/diffusion: 3

Poly/poly: 2

Poly/diffusion: 1

Via/via: 2

Metal1/metal1: 3 Metal2/metal2: 4

Metal3/metal3: 4


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Overglass

Cut in passivation layer.

Minimum bonding pad: 100 m.

Pad overlap of glass opening: 6

Minimum pad spacing to unrelated

metal2/3: 30

Minimum pad spacing to unrelated metal1,

poly, active: 15


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Scmos VARIATIONS

SCMOS SCMOS

submicron

SCMOS deep

Poly space 2 3 3

Active extensionbeyond poly

3 3 4

Contact space 2 3 4

Via width 2 2 3

Metal 1 space 2 3 3

Metal 2 space 3 3 4


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Lithography for nanometer

processes

Interference causes

drawn features to be

distorted duringlithography.

Optical proximity

correction pre-distorts

masks so they createthe proper features

during lithography.


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3-D integration

3-D technology stacks multiple levels of

transistors and interconnect.

Through-silicon-via (TSV) with die

stacking uses special via to connect between

separately fabricated chips.

Multilayer buried structures build severallayers of devices on a substrate.


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Reliability

Failures happen early,

late in chips life.

Infant mortality iscaused by marginal

components.

Late failures are

caused by wear-out

(metal migration,

thermal, etc.).


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Mean-time-to-failure

MTF for metal wires = time required for

50% of wires to fail.

Depends on current density:

proportional to j-n e Q/kT

j is current density

n is constant between 1 and 3

Q is diffusion activation energy

Can determine lifetime from MTTF.


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Traditional sources of

unreliability

Diffusions and junctions: crystal defects,

impurity precipitation, mask misalignment,

surface contamination. Oxides: Mobile ions, pinholes, interface

states, hot carriers, time-dependent

dielectric breakdown. Metalization: scratches/voids, mechanical

damage, non-ohmic contacts, step coverage.


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TDDB

Time-dependent dielectric breakdown: gate

voltages cause stress in gate oxides.

More common as oxides become thinner.

TDDB failure rate:

MTTF = A 10 bE eEs/kt


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Hot carriers

Hot carrier has enough energy to jump from

silicon to oxide.

Accumulated hot carriers create a spacecharge that affects threshold voltage.


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NTBI

Negative bias temperature instability is

particular to pMOS devices.

Threshold voltage, transconductance changedue to stresses.

Can be reversed by applying a reverse bias

to the transistor.

l i i d


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Electromigration and stress

migration

Degenerative failure for wires.

Grains in metal have defects at grain surface

that cause electromigration.

Stress migration caused by mechanical

stress.

Can occur even with zero current.


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Soft errors

Caused by alpha particles.

Packages contain small amounts of uranium

and thorium, which generate error-inducingradiation.


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PVT

Borkar et al.:

variations in process,

supply voltage,temperature are key

design challenges in

nanometer technology.


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PVT challenges

Process variations: channel length and

threshold significantly in nanometer

technologies. Supply voltage: non-ideal wires introduce

variations in supply across chip.

Temperature: higher chip operatingtemperatures degrade both transistors and

interconnect.


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On-chip temperature sensors

Temperature sensors are used to shut off

part or all of the chip to stop thermal

runaway. Use a pn junction from a parasitic bipolar

transistor.

Can also use MOS transistor.


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Stick diagrams

A stick diagram is a cartoon of a layout.

Does show all components/vias (except

possibly tub ties), relative placement.

Does not show exact placement, transistor

sizes, wire lengths, wire widths, tub

boundaries.


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Stick layers

metal 3

metal 2

metal 1

poly

ndiff

pdiff


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Dynamic latch stick diagram

VDD

in

VSS

phiphi

out


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Sticks design of multiplexer

Start with NAND gate:


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NAND sticks

VDD

a

VSS

out

b


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One-bit mux sticks

VDD

VSS

N1

(NAND)select out

a

b

N1

(NAND)

out

a

b

N1

(NAND)

out

a

b

select

ai

bi


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3-bit mux sticks

m2(one-bit-mux)

select select VDD

VSS

oiai

bi

m2(one-bit-mux)

select select VDD

VSS

oiai

bi

m2(one-bit-mux)

select select VDD

VSS

oiai

bi

select select

a2

b2

a1

b1

a0

b0

o2

o1

o0


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Layout design and analysis tools

Layout editors are interactive tools.

Design rule checkers are generally batch---

identify DRC errors on the layout.

Circuit extractors extract the netlist from the

layout.

Connectivity verification systems (CVS)

compare extracted and original netlists.


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Automatic layout

Cell generators (macrocell generators)

create optimized layouts for ALUs, etc.

Standard cell/sea-of-gates layout createslayout from predesigned cells + custom

routing.

Sea-of-gates allows routing over the cell.


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M d VLSI D i 4 Ch t 2 C i ht 2008 P ti H ll PTR

Standard cell layout

routing area

routing arearoutinga

rea

routingare

a

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