ADVANCED VLSI CHAP4-4

7/28/2019 ADVANCED VLSI CHAP4-4

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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf

Topics

Interconnect design.

Crosstalk.

Power optimization.


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Interconnect

Even assuming logic structure is fixed, we

can:

change wire topology;

resize wires;

add buffers;

size transistors.


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Multipoint nets

Two-point nets are easy to design.

Multipoint nets are harder:

How do we connect all the pins using two-point

connections?


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Styles of wiring trees

source

sink 2

sink 1

Spanning tree

Steiner treeSteiner point


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Sized Steiner tree

source

sink 2

sink 1

Feeds both branches

Smaller currents in each branch


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Buffer insertion in wiring trees

More complex than placing buffers along a

transmission line:

complex topology;

unbalanced trees;

differing timing requirements at the leaves.


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Van Ginneken algorithm

Given:

placements of sources and sinks;

routing of wiring tree.

Place buffers within tree to minimize the

departure time at the source to meet all the

sink arrival times:Tsource = min i (T i -D i)

T i = arrival time at node i, D i = delay to node

I.


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Delay calculation

Use Elmore model to compute delay along

path from source to sink.


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Recursive delay calculation

Recursively compute Elmore delay through

the tree.

Start at sinks, work back to source.

r, c are unit resistance/capacitance of wire.

Lk is total capacitive load of subtree rooted at

node k.


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Modifying the tree

Add a wire of length l at node k: Tk = Tk- r/Lk - 0.5rcl.

Lk = Lk+ cl.

Buffer node k: Tk = Tk- Dbuf- RbufLk.

Lk = Cbuf. Join two subtrees m and n at node k:

Tk = (Tm , Tn).

Lk = Lm + Ln.


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Crosstalk

Capacitive coupling introduces crosstalk.

Crosstalk slows down signals to static gates,

can cause hard errors in storage nodes.

Crosstalk can be controlled by

methodological and optimization

techniques.


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Interleaved power/ground

VDD

VSS

VDD

VSS

VDD

VSS


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Twizzled wires

a

b

c

d

b

d

a

c

a

b

c

d


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Coupling and crosstalk

Crosstalk current depends on capacitance,

voltage ramp.

w1 w2

Cc

ic

t


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Crosstalk analysis

Assume worst-case voltage swings, signal

slopes.

Measure coupling capacitance based ongeometrical alignment/overlap.

Some nodes are particularly sensitive to

crosstalk:dynamic;

asynchronous.


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Coupling situations

sig1a x r

better worse

bus[0]

bus[1]

bus[2]


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Layer-to-layer coupling

Long parallel runs on adjacent layers are

also bad.

bus[0]

siga

SiO2


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Methodological solutions

Add ground wires between signal wires:

coupling to VSS, a stable signal, dominates;

can use VSS to distribute power, so long aspower line is relatively stable.

Extreme caseadd ground plane. Costs an

entire layer, may be overkill.


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Ground wires

VSS

sig1

VSS

sig2

VSS


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Crosstalk and signal routing

Can route wires to minimize required

adjacency regions.

Take advantage of natural holes in routingareas to decouple signals.

Minimizes need for ground signals.


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Assumptions

Take into account coupling only to wires in

adjacent tracks.

Ignore coupling of vertical wires.

Assume that coupling/crosstalk is

proportional to adjacency length.


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Crosstalk example


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Crosstalk analysis

Want to estimate delays induced by

crosstalk.

Effect of coupling capacitance Cc dependson relative transitions.

Aggressor changes, victim does not: Cc.

Aggressor, victim move in opposite directions:2Cc.

Aggressor, victim move in same direction: 0.


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Crosstalk analysis, contd.

Coupling effects depend on relative

switching time of nets.

Must use iterative algorithm to solve forcoupling capacitances and delays.


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Power optimization

Glitches cause unnecessary power

consumption.

Logic network design helps control powerconsumption:

minimizing capacitance;

eliminating unnecessary glitches.


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Glitching example

Gate network:


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Glitching example behavior

NOR gate produces 0 output at beginning

and end:

beginning: bottom input is 1;

end: NAND output is 1;

Difference in delay between application of

primary inputs and generation of newNAND output causes glitch.


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Adder chain glitching

badgood


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Explanation

Unbalanced chain has signals arriving at

different times at each adder.

A glitch downstream propagates all the wayupstream.

Balanced tree introduces multiple glitches

simultaneously, reducing total glitchactivity.


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Signal probabilities

Glitching behavior can be characterized by

signal probabilities.

Transition probabilities can be computedfrom signal probabilities if clock cycles are

assumed to be independent.

Some primary inputs may have non-standard signal probabilitiescontrol

signal may be activated only occasionally.


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Delay-independent probabilities

Compute output probabilities of primitive

functions:

PNOT = 1 - Pin

POR= 1 - Pi)

PAND = Pi

Can compute output probabilities ofreconvergent fanout-free networks by

traversing tree.


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Delay-dependent probabilities

More accurate estimation of glitching.

Glitch accuracy depends on accuracy of

delay model. Can use simulation-style algorithms to

propagate glitches.

Can use statistical models coupled withdelay models.


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Power estimation tools

Power estimator approximates power

consumption from:

gate network;

primary input transition probabilities;

capacitive loading.

May be switch/logic simulation based oruse statistical models.


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Factorization for low power

Proper factorization reduces glitching.

bad good


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Factorization techniques

In example, a has high transition

probability, b and c low probabilities.

Reduce number of logic levels throughwhich high-probability signals must travel

in order to reduce propagation of glitches.


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M d VLSI D i 4 Ch 4 Copyright 2008 Wayne Wolf

Layout for low power

Place and route to minimize capacitance of

nodes with high glitching activity.

Feed back wiring capacitance values topower analysis for better estimates.

ADVANCED VLSI CHAP4-4

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