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Nonvolatile, High Density, High Performance Phase Change Memory

Guy Wicker1, Scott Tyson2, Tyler Lowrey1, Stephen Hudgens1, Robert Pugh3, Ken Hunt3

1 Ovonyx, Inc., 1675 W. Maple Rd, Troy, MI 480842 Mission Research Corp., 5001 Indian School Rd NE, Albuquerque, NM 871103 Air Force Research Laboratory, 3550 Aberdeen SE, Kirtland AFB, NM 87117

ABSTRACT

A resistor-based approach has been developed as a basis for a new nonvolatile memory that is potentially denser, faster, andeasier to make than Dynamic RAM. It relies on phase transitions induced by nanosecond-scale heating and cooling of smallvolumes of chalcogenide films within the memory cell. Initial target markets include FLASH memory, embedded memory,and DRAM.

Keywords: nonvolatile memory, phase change, chalcogenide, amorphous, memory scaling

1. BACKGROUND

The first observation of changes in the electrical conductivity of a chalcogenide material resulting from a structural changeinduced by the passage of electrical current was reported1 in MoS2 nearly 80 years ago. During the 1950s, thesemiconducting properties of a range of crystalline and amorphous chalcogenide alloys were investigated.2 In the early1960s, new reversible phase change materials and electrically and optically programmable devices were reported,3 and thesedevices were proposed for use in digital computers as non-volatile memory. This announcement initiated significant interestin these applications, and widespread research into chalcogenide amorphous semiconductors and their applications followed.4

Commercial rewriteable optical memory disks using a laser-induced structural phase change in a chalcogenide alloy are nowin production. These disks include 650 Mbyte capacity PD and CD-RW disks and 2.6 Gbyte and 5.2 Gbyte DVD-RAMmedia. Progress towards commercialization of the electrically programmed memory device has occurred more slowly; butrecently, researchers have reported5 phase change non-volatile semiconductor memory devices with significantly increasedprogramming speed and reduced programming current compared to the original devices from the 1960s.

A number of recent developments have made it possible to use phase-change semiconductor memory devices aspractical high-performance memory elements. First, alloys exhibiting rapid crystallization have been developed andcommercialized for use in rewriteable optical disk applications,6-9 and these multi-component chalcogenide alloys are wellsuited for use in semiconductor memory applications as well. Second, a more detailed understanding of the device behaviorhas developed that permits the engineering of practical memory devices10. Third, lithographic scaling and processingimprovements have reduced the programming requirements of new cell designs, which can now be driven by minimumgeometry MOS transistors.

The commercial exploitation of this technology is now feasible. In fact, it is now believed that the chalcogenidetechnology can provide a lower cost and higher performance memory than EEPROM and DRAM. Furthermore, embeddedmemory applications can readily be achieved due to the simple, planar structure of the storage element.

2. THEORY OF OPERATION

Chalcogenide alloys have been designed that are highly resistive semiconductors in the amorphous phase and highlyconductive semimetals in the crystalline phase. A two-terminal memory element implementing the chalcogenide materialcan be fabricated which operates by converting a small volume of the chalcogenide material back and forth between thecrystalline and amorphous phases.

The phase conversion is accomplished by appropriate heating and cooling of the material. Once the chalcogenidematerial melts, the material loses all crystalline structure, and rapid cooling of the material to below its glass transitiontemperature causes the material to be locked into its amorphous phase. The amorphous phase is very stable near roomtemperature, but the rate of nucleation and growth of crystallites increases exponentially as the melting temperature is

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approached. To keep the material from recrystallizing during cooling, the cooling rate must be faster than the crystalnucleation and growth rate. To switch the memory element back to its conductive state, the material is heated to atemperature between the glass transition temperature and the melting temperature, causing nucleation and crystal growth torapidly occur over a period of several nanoseconds.

The crystal nucleation and growth rate depends on the chalcogenide alloy composition and can vary by more than 20orders of magnitude among various materials. Early chalcogenide semiconductors investigated for memory applications hadcrystallization speeds as great as a millisecond. It should come as no surprise that early electronic and optical memoriesmade from such alloys were not a commercial success. To be practical, the rewriteable optical disk required an alloy with acrystallization speed at or below 50ns. Work at Matsushita in the mid 1980s led to the development of TeGeSb system whichexhibits crystallization times below 50ns, a glass transition temperature above 300C, and a melting point above 600C 11-15.Optical disks employing these alloys rely on changes in the material's optical characteristics between the crystalline andamorphous phases. Changes in the electrical properties of these alloys are far more dramatic, with variations in the electricalconductivity by up to 6 orders of magnitude between phases.

Figure 1. Circuit description of memory array.

To create an electronic memory from these materials, an array of access transistors must each be capable ofproviding sufficient power to a memory element to melt a portion of the chalcogenide alloy. These transistors could beconnected to the array in the fashion shown above in Figure 1. Thermal isolation of the memory element itself from the heat-sinking substrate and metallization is a crucial aspect of the memory element design. The memory cell must be capable ofproviding the necessary resistance that biases the MOS transistor to deliver peak power. The chalcogenide film is alwayshighly conductive above the glass transition temperature, regardless of its phase. The resistance of the memory element musttherefore be tailored by adjusting the resistance of the contacts (RC) adjacent to the chalcogenide material.

When the material is in the amorphous state, its resistance is too high to allow any significant current to pass. As aresult, it would seem that when the material is in the amorphous phase that it would be difficult to pass sufficient electriccurrent through the film in order to provide the necessary heat to alter the materials phase back to its crystalline state.However, when an electric field of approximately 3X105 V/cm is applied, Poole-Frenkel conduction, combined with deviceheating, lowers the material's resistance and switches the chalcogenide film into a low impedance state that persists until thepulse is removed and the material cools16. To ensure that the electronic memory device can heat up during a write operationwhen it is in the insulating state, the write pulse must have a sufficiently high potential to cause this switching. Conversely,to read the device it is necessary to limit the applied potential so fields of this magnitude are not present. This ensures thatthere is a large current ratio difference between reading a crystalline device and reading an amorphous device. Typicallyratios above 2 orders of magnitude are observed, allowing a very fast read circuit with high noise immunity to beimplemented.

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The voltage applied to the memory array (VA) determines the maximum field that the memory element canexperience, while the row and column select circuitry controls the current passing through the device. Three modes ofoperation exist for the memory element (1) reading, (2) setting, and (3) resetting. These modes are described below:

1) To read, the electric field must be limited by applying a low voltage VA to the device. When the access transistor isactivated, only a small current will pass if the material is reset to the amorphous state. If the material is set to thecrystalline phase, the applied voltage VA and the resistance of the contact RC will limit the current through the device.

2) To set the device, the voltage VA must be high enough to ensure that the alloy will switch into a low impedance state.The access transistor must be biased to an intermediate current level that will heat the material significantly, but not meltit. The duration of the set pulse must be sufficiently long to permit nucleation and growth of crystallites.

3) To reset the device, the voltage VA must be high enough to ensure that the alloy will switch into a low impedance state.The access transistor must be biased to allow sufficient current to heat a portion of the material above its meltingtemperature. When the current is removed, the small volume of material that has melted will rapidly quench into theamorphous state. This will typically occur in less than 2ns if the thermal time constant of the device has been properlyengineered.

3. DEVICE PERFORMANCE AND SCALING

There is rising concern in the memory industry about the future scalability of memory technologies. EEPROM memorydevices have already encountered fundamental limits in their ability to scale17. DRAM technology is using increasinglycomplex cell structures to maintain cell capacitance as feature sizes continue to shrink18. All memory technologies that relyon charge storage encounter scaling problems as geometry shrinks further, since their capacitance decreases as well. Amemory approach that relies instead upon electrical resistivity circumvents this limitation altogether.

The scaling limitation of a memory device based on a phase change alloy is the minimum amount of material thatcan reliably undergo a phase transition. This limit has not been explored, but devices have been made using a film thicknessof 50 angstroms and small geometry contacts without observing significant changes in device behavior. It seems that for thenear future, the scaling limits of the addressing circuitry and the lateral isolation of the individual elements of the memoryarray will be the dominant concern.

Power scaling is a concern because of the geometrical considerations relating to isolation of the individual memoryelements. The power needed to heat the material to the melting temperature depends on the volume of material that must beheated and the insulating properties of the material surrounding this heated region. As the thermal isolation increases beyonda certain point, the cooling rate achieved (thermal time constant) becomes inadequate to quench in the amorphous state.

Figure 2. Speed power tradeoff vs. device size and insulation

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A computer simulation of this problem was developed that considers a spherical volume of chalcogenide alloysurrounded by various thermally insulating materials. The power needed to heat the volume to the melting temperature in 5nanoseconds was computed along with the time needed to cool halfway back to ambient temperature after the heating pulsewas removed, which corresponds to the quench time.

, The results of this simulation are displayed in Figure 2. Lines connect the results from simulations of constant sizeand constant thermal diffusivity. Common materials available as thermal insulators in semiconductor processing are notedalong lines corresponding to their thermal diffusivity properties. It is evident from this analysis that the power needed tooperate the memory goes down dramatically as the device size is decreased. The quenching time is roughly proportional tothe device size as well. This chart shows that these memory elements exhibit a dramatic reduction in reset power as size isreduced as well.

4. POWER LIMITATIONS OF MOSFETS

As MOS transistors are scaled down in size, their channel length and the gate oxide thickness are reduced. These changeslead to dramatic increases in current density, but they limit the potential that can be applied to the device before breakdownoccurs.

Figure 3. Maximum current and voltage controlled by a minimum sized MOS transistor

The graphs in Figure 3 show some practical values for the maximum voltage and current that are compatible withthe operation of a minimum-feature-size MOS transistor. MOS transistors are not ideal switches, since there is a potentialdrop of approximately 0.6V across the source and drain of a transistor when it is operating at its peak current. Thisintroduces a parasitic loss in the peak power that the MOS transistor can deliver from the simple product of the voltage andcurrent, as shown in Figure 3.

Figure 4 depicts the maximum power that a minimum-feature-size MOS transistor can deliver to its load.Comparing this to the power scaling of the device shown in Figure 2 makes it apparent that the region of heating needs to beconsiderably smaller than the lithographic feature size if a minimum-feature MOS transistor is going to control it.

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One possible solution to overcome this limitation is the use of bipolar transistors, which can provide higher powerdensity. This approach is undesirable, however, bipolar transistor production cost and size are both larger than a MOStransistor. Therefore, alternative solutions need to be developed, such as an improved device design.

Figure 4. Power delivered to load by minimum sized MOS transistor

5. DEVICE CONFIGURATION

Initial investigation of device performance was done using devices with the simple structure shown in Figure 5. In thisstructure, the region of melting for the chalcogenide alloy is constrained by a circular via etched through an insulating layer.Device thickness is established by the thickness of the insulating film, which is considerably smaller than the minimumfeature size. Experimental measurements showed these devices required excessively large currents to reset.

Figure 5. Early devices using via structure.

Device modeling of the structures demonstrated that excessive current was necessary to heat the low-resistancechalcogenide alloy in the presence of the heat sinking substrate and metal contacts. Alternative structures such as that shownin Figure 6 below were produced that reduced the reset current by two orders of magnitude.

The via size can be smaller than the effective minimum feature size of the process lithography, and the volume ofthis thin device is then nearly small enough to make devices that can be switched by MOS transistors.

Devices using the via structure have been produced that can be reset with less than 300 microamps of current andexhibit an on-to-off current ration of 40:1 over a wide temperature operating range. They have been rewritten greater than

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1013 times before device failure. An additional potential advantage is that the resistance of the alloy changes continuously asthe amount of crystallized material varies, allowing multilevel storage.

Figure 6. Device using thermally optimized via structure

Further reduction in current is needed to make high-density memory from this technology. Alternative devicestructures are presently being fabricated that reduce the contact area to the chalcogenide material and further improve thethermal insulation of the surrounding environment.

Figure 7. Device under investigation

Figure 7 shows one structure currently being investigated. The bottom electrode contacts the chalcogenide alloymaterial, forming a ring-shaped contact area. The chalcogenide alloy is deposited in the highly conductive crystalline phase.The region where phase transition occurs is limited to the chalcogenide material immediately adjacent to the lower electrode.This reduction in the volume of material being melted reduces the power requirement sufficiently to allow a minimum-feature-size MOS transistor to easily control the device.

Detailed modeling of the electrical, thermal, and phase-transition behavior of these device structures has suggestednumerous alternative structures that will have improved reliability and that will integrate well into a standard CMOS logic ormemory process.

6. DEVICE MODELING

The behavior of this device is complex, and a detailed model is vital to understanding how the device will function whenscaled to smaller dimensions. A three-dimensional finite difference model of the device has been developed and tested usingdata collected from devices and the bulk properties of the chalcogenide alloy.

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The crystallization dynamics of the chalcogenide alloys have been measured using Differential Thermal Analysis,annealing experiments, electrical pulsing and optical pulsing experiments, including Photo Deflection Spectroscopy. There isa large crystallization exotherm and melting endotherm that play a significant role in the device behavior. The Wiedeman-Franz relationship accounts for the difference in thermal conductivity between the phases of the material. All these physicalmeasurements show the complex interrelationship between the electric field, temperature, and phase of the material. Thismust be accounted for in accurately modeling the device behavior.

Figure 8. Modeling methodology

The model uses the approach shown in Figure 8. First, the electrical solution of the mesh is computed, and from thisthe power dissipation is found. The circuit environment surrounding the device is modeled as well to establish the actualcurrent and voltage applied to the device. Next, the heat equation is solved for a time interval. Taking too large a time stepwill limit the accuracy of the calculation, so the interval is varied to maintain accuracy, while completing the overallsimulation as fast as possible. Nonlinear changes in material properties are then computed. The phase of the alloy is treatedas a volume fraction of crystalline material at each point in the mesh. Based on the current crystal fraction, the temperatureand the elapsed time, a new volume fraction is established for each mesh point of chalcogenide alloy. Electrical conductivityvariation due to the phase of the material is computed by using a percolation model of conduction19.

This model has also been used to investigate the behavior of phase-change optical disks. In this case, instead ofpower being applied electrically, the program models light absorption in three dimensions through the optical stack of aphase change disk. Motion of the laser above the sample is simulated over the time of the analysis. The resultingtemperature distribution as well as the nonlinearities and the phase transitions in the material are computed in the samemanner for both the electrical and optical models.

7. NEAR-TERM DEVELOPMENT

Several semiconductor memory technologies currently exist, including conventional volatile technologies (i.e.,SRAM and DRAM) as well as numerous non-volatile technologies (i.e., FeRAM, EEPROM, Flash, ROM, HDD, andMRAM). Although many of these technologies are capable of supporting a variety of terrestrial applications due to the readyavailability of power grid and the easy replacement of worn-out or failed components, each of these technologies possessesserious inadequacies for implementation in space-based or missile systems. The reasons for this vary from technology totechnology but include susceptibility to extreme shock, radiation, or thermal environments; high levels of power

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consumption; high cost; low integration levels; and low cycling limitations. In contrast, resistivity-based information storageusing thin chalcogenide films implemented within a contemporary CMOS fabrication technology offers an approach thatpotentially overcomes each of the limitations of these other technologies.

As a result, the Air Force Research Laboratory has initiated a development effort to demonstrate the feasibility ofthis new, high-signal-level, chalcogenide-resistor-based, nonvolatile storage element. Under this effort, the chalcogenidememory element will be integrated into the process flow of a submicron fabrication technology capable of supporting aninitial circuit integration level of 16Mb. Test structures will be fabricated and characterized, and the thermal models will befurther refined. The effort is scheduled to begin during last quarter of 1999.

8. CONCLUSION

Chalcogenide-alloy, phase-change memories are at a point where they may now provide competitive alternatives toestablished semiconductor memory products. Additionally, chalcogenide-based memories offer nonvolatile operation,DRAM speeds, no practical cycling limitations, higher integration density, and lower manufacturing cost than any establishedtechnology. Inherent radiation hardness of the basic material makes this technology an ideal candidate for space electronicsapplications.

These memory elements are fundamentally different from other semiconductor memories; information storage isachieved through changes in electrical resistivity rather than through manipulation of exceedingly small amounts of charge.

Efforts to date have focused on reducing the power needed to switch the memory element to allow operation by asingle, minimum-feature-size MOS transistor, thereby allowing maximum memory density integration. Extensive modelingsupports the achievement of this goal. New devices are currently being fabricated to demonstrate the feasibility of integratingplanar resistive elements with MOS transistors. Device modeling suggests that these devices will meet the goal of low powerswitching and simple lithographic-dependent scalability.

9. REFERENCES

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3. S.Ovshinsky, Reversible Electrical Switching Phenomena in Disordered Structures, Phys. Rev. Lett, V. 21, no. 20, pp.1450-1453, Nov. 11, 1968.

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11. T.Ohta , K.Yoshioka, H.Isomura, T.Akiyama, R.Imanaka, High Sensitivity Overwritable Phase-Change Optical Diskfor "PD" Systems", Optical Data Storage'95, Proc. SPIE 2514, pp302-311, 1995.

12. J.Coombs, A.Jongenelis, W.van Es-Spiekman, B.Jacobs, Laser-Induced Crystallization Phenomena in Ge-Te-BasedAlloys. I. Characterization of Nucleation and Growth, J. Appl. Phys., v78 #8, pp4906-4917, 1995.

13. J.Coombs, A.Jongenelis, W.van Es-Spiekman, B.Jacobs, Laser-Induced Crystallization Phenomena in Ge-Te-BasedAlloys. II. Composition Dependence of Nucleation and Growth, J. Appl. Phys., v78 #8, pp4918-4928, 1995.

14. Y.Hsieh, M.Mansuripur, J.Volkmer,A.Brewen, Measurement of the Thermal Coefficients of Nonreversible Phase-Change Optical Recording Films", Applied Optics, v36 #4, pp866-872, Feb. 1997.

15. Z.Mao, H.Chen, A.Jung, The Structure and Crystallization of Phase Change Optical Disk Material Ge1Sb2Te4", J.Appl. Phys., v78 #4, pp2338-2342, Aug. 1995.

16. D.Adler, M.Shur, M.Silver, S.Ovshinsky, Threshold Switching in Chalcogenide-Glass Thin Films, J. Appl. Phys., v51,#6, pp103-123, 1980.

17. S.Lai, FLASH Memories: Where We Were and Where We are Going", IEEE IEDM Tech. Dig., pp.971-973, 1998.

18. A.Nitayama, Y.Kohyama, K.Hieda, Future Directions for DRAM Memory Cell Technology", IEEE IEDM Tech. Dig.,pp355-358, 1998.

19. S.Kirkpatrick, Percolation and Conduction, Reviews of Modern Physics, v45 #4, pp574-588, 1973.