Introduction to VLSI System Design · ECE425 Intro VLSI System Design Lecture Notes The lecture...

Intro VLSI System DesignECE425

Electrical Computer Engineering ECE425

Introduction to VLSI System Design

Anu AggarwalECEB3044

[email protected]

Intro VLSI System Design

Teaching Staff Dr. Anu Aggarwal

– Office hours – T, R – 5-6 pm, W- 4-5 pm

TA - Xinheng Liu– W- 9-12 noon , Lab ECEB 2022– Weeks MPs are due, F- 9-12 noon


Web, software

ECE425

Course web page: https://courses.engr.illinois.edu/ece425– Syllabus, class notes, announcements, MP & HW

materials, etc. will be posted here. Piazza: https://piazza.com/illinois/fall2019/ece425

– This is the primary means of staff-student communication outside of lecture hours and office hours.

Compass2g: https://compass2g.illinois.edu– Grades and MP submissions

Cadence Design Framework– Installed on EWS Linux workstations (ECEB2022)– Instructions will be provided in MP0


Textbooks Required Text

– Neil Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition.

Recommended Book– De Micheli, Synthesis and Optimization of Digital Circuits

Other Reference Books– Sherwani, Algorithms for VLSI Physical Design Automation– Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits:

a Design Perspective (2nd edition)

ECE425


Lecture NotesThe lecture notes will include some material not covered in the

principle textbook and will be the primary course material. However, the level of details and description in the notes will not be as complete as the information that you would find in a textbook. We will also try to include additional information to help you understand the material.

The lecture slides we will be using were prepared by Prof. Deming Chen. Some of the notes used in this course are courtesy of David Harris and Jason Cong.


Grading

ECE425

Homework assignments – 3: worth 10% of course grade– no late acceptance

Exams – mid-term and final - in class– 20%+20% of course grade

Machine Problems (4 total): 50% of course grade– MP0: 2.5%; MP1: 10%; MP2: 5%+20%; MP3: 12.5%– Due on Compass by 11:59pm on the due dates. – Submit PDF version of the report– All MPs, except MP3, are accepted up to three days late

with penalties:• 1 day: 10%; 2 days: 30%; 3 days: 50%; >3 days: 100%.


ECE425 Goals Understanding the basic building blocks of VLSI

– Transistors/Wires– Logic Gates and Layout– Datapath Blocks

Be able to optimize a design on important design metrics– Logic Optimization– Improve Testability– Power Minimization

Be able to build a system (using a subset of the tools), and learn useful algorithms and techniques for VLSI CAD

– Verilog Modeling– Synthesis– Place and Route

Understanding the constraints, tradeoffs and other issues– Delay analysis (gates and interconnects)– Clocking methodology– System integration issues


Lecture 1

Overview of VLSI Design

Readings: Weste & Harris; 1.1, 1.5.1, 1.6

Slides courtesy of Deming ChenSome slides courtesy of Ken Yang (UCLA)

and David Harris (Harvey Mudd)


Goals for today’s lecture

MotivationHistory of VLSI designFabrication and Layout: Inverter

Cross sectionDesign Partitioning


The Big Picture Want to go from an idea:


The Big Picture To actual chip:


Magnified


Why? Easier to move/control electrons than real stuff

– Electronic calculators, not mechanical – Move information, not things (phone, fax, WWW, etc.)

Building electronics:– Started with tubes, then miniature tubes– Transistors, then miniature transistors– Components were getting cheaper, but:

• There is a minimum cost of a component (storage, handling …)• Total system cost was proportional to complexity

Integrated Circuits changed that– Print a circuit, like you print a picture,

• Create components in parallel• Cost no longer depended on # of devices

– What happens as resolution goes up?


History

ECE425


Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large,

expensive, power-hungry, unreliable 1947: first point contact transistor

– John Bardeen and Walter Brattain at Bell Labs (Nobel Prize in Physics in 1956)

“We call it the Transistor,T-R-A-N-S-I-S-T-O-R, because it is a resistoror semiconductor devicewhich can amplify electrical signals as they are transferred…”

Presenter

Presentation Notes

First transistor was nearly classified as a military secret, but Bell Labs publically introduced the device the following year.


A Brief History 1958: First integrated circuit

– Flip-flop using two transistors– Built by Jack Kilby at Texas Instruments

(Nobel Prize in Physics in 2000) https://en.wikipedia.org/wiki/Comparison_of_Intel_pr

ocessors https://en.wikipedia.org/wiki/Transistor_count 53% compound annual growth rate over 50 years

– No other technology has grown so fast so long Driven by miniaturization of transistors

– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society

Presenter

Presentation Notes

10 years later Jack Kilby at Texas Instruments put two transistors together to implement a flip-flop, for which he received Nobel Prize in Physics in 2000. Fast-forward 50 years later, NVIDIA Tesla GPU consisted of 1.4 billion transistors! This corresponds to compound annual growth rate of 53% No other technology has grown at that rate in our history Most other fields of engineering involve tradeoffs between performance, power, and price. However, as transistors became smaller, they also became faster, use less power, and are cheaper to manufacture. This revolutionized the field of electronics and impacted the society at large in ways no other technology could do

https://en.wikipedia.org/wiki/Comparison_of_Intel_processors

https://en.wikipedia.org/wiki/Transistor_count


Billion-Transistor Chips

Source: Zhiru Zhang, Cornell

Presenter

Presentation Notes

Here are a few examples of billion-size transistors. The incredible miniaturization trend brought us incredibly powerful chips that power up incredible devices with performance unimaginable just a decade ago.


Annual Sales

Presenter

Presentation Notes

Here are shown annual sales in the worldwide semiconductor market. Integrated circuits became a $100B/year business in 1994. In 2007, the industry manufactured approximately 6 quintillion (6x1018) transistors, nearly a billion for every human on Earth. Thousands of engineers made their fortunes working in the field, and thousands more will do.


1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

MOS Integrated Circuits

Intel 1101 256-bit SRAM Intel 4004 4-bit µProc

Presenter

Presentation Notes

Early commercial processes used only pMOS transistors, but they suffered from poor performance, yield, and reliability. Processes using nMOS transistors became common in the 1970s. Intel pioneered the nMOS technology with its 1101 256-bit SRAM and 4004 4-bit CPU. Devices built with nMOS were less expensive and more reliable, but still consumed power when idle. Power consumption eventually became an issue in 1980s as 100s of thousands of transistors were integrated into a single die. As the result, starting from 1980s, CMOS technology replaced nMOS processes and is now the dominant process to manufacture microchips.


Moore’s Law 1965: Gordon Moore plotted transistor on each chip

– Fit straight line on semilog scale– Transistor counts have doubled every 18 months

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium IIIPentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1970 1975 1980 1985 1990 1995 2000

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates

Presenter

Presentation Notes

In 1965, Gordon Moore observed that plotting the number of transistors that can be most economically integrated on a chip as a function of time resulted in a straight line on the semi-logarithmic scale. This empirical observation became known as Moore’s Law and became a self-fulfilling prophecy for the semiconductor industry. Transistor count doubled every 18 months in the early days and doubled on Intel’s chips every 26 months since the introduction on 4004 CPU. Moore’s Law is driven primarily by the scaling down the size of the transistor, and to some minor effect by building larger chips. The level of integration of chips (the number of gates used in the chip design) has been classified as small-scale. Mid-scale, large-scale, and very large scale integration. A gate is roughly built out of a half-a dozen transistors. Electronic circuits built after 1980s are referred to as VLSI circuits due to their extremely high transistor count.


Corollaries (1) Many other factors grow exponentially

– Ex: clock frequency, processor performance

Year

1

10

100

1,000

10,000

1970 1975 1980 1985 1990 1995 2000 2005

4004

8008

8080

8086

80286

Intel386

Intel486

Pentium

Pentium Pro/II/III

Pentium 4

Clock Speed (M

Hz)

Presenter

Presentation Notes

A corollary of Moore’s Law is Dennard’s Scaling Law: As transistors shrink, they become faster, consume less power, and are cheaper to manufacture. This picture shows that Intel microprocessor clock frequencies have doubled roughly every 34 months, up until early 2000s. This frequency scaling hit power wall around 2004 and clock frequencies pretty much leveled out around 3 GHz. Of course there are higher frequency chips, such as up to 5 GHz, but they require extensive cooling to remove the heat. Computer performance, measured as time to perform the computation, has advanced even more than raw clock speed – How? Cores Logic


Corollaries (2) Cost of wafer fabrication- growing slower Cost per function- dropping exponentially. Every new generation,

– A gate costs ~ 1/2 what it did 1.5 years ago.

yearyear

diecost

ln(cost/function)

Presenter

Presentation Notes

Manufacturers introduce a new process generation every 2-3 years with 30% smaller feature size. This enables to pack roughly twice as many transistors in the same area. Since the cost of the printing process (called wafer fabrication) is growing at a slower rate, it implies that the cost per function, is dropping exponentially. At each new generation, each gate cost about 1/2 what it did 1.5 years ago. Shrinking an existing chip makes it cheaper.


Bad news: Productivity Gap

xxxxxx

x 21%/Yr. Productivity growth rate

x

58%/Yr. Complexity growth rate

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

199810

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Log

ic T

rans

isto

rs/C

hip

(K)

Tran

sist

or/S

taff-

Mon

th

Chip Capacity and Designer Productivity2003

Source: NTRS’97

Presenter

Presentation Notes

However, there are other forces that make this process more costly. This plot shows two trends: complexity growth rate measured in number of transistors per chip and the amount of time it takes to design the chip in terms of human resources, referred to as productivity growth rate. While both trends show growth, the rate is very different!


The Cost of Next Generation Product

Source: IBS Inc.

Wireless chip case

Networking chip case

0.18um 0.13um 90nm

10

20

30

40

50

0.15

Total Product Cost ($M)$30M ~ $50M @ 90nm

Presenter

Presentation Notes

This means that the cost of bringing up a new chip design to the market grows quite substantially. For example, going from 130 nm to 90 nm design nearly triples the total product cost.


The Cost of Next Generation Product

Engineering Cost – 60% up

Manufacturing Cost – 40% up

NRE/Mask Cost – 100% up

ProductCost

Respin cost – 78% up

Presenter

Presentation Notes

Although the cost of printing each transistor goes down, the one-time design costs are increasing exponentially. This means that companies are only able to afford engineering new chips that will sell in huge quantities.


Technology Scaling Number of ‘grids’ per chip

doubles every 1.5 years– more functionality per

chip– harder to design

Two problems– What do you do with all

that space -- what function?

– How do you make sure it works

2010

2004

1998

Presenter

Presentation Notes

So, what is the problem? Why this is the case? As the chip size grows, either because the transistor size shrinks or because the chip area increases, more functionality can be implemented, which adds up to the overall design cost. Two main challenges are What to do with all that space - what functionality to add to the design to both make use of all that extra space and be useful? How to make sure it actually works ? test and validation start to take a substantial amount of time


Fabrication and layout:

Overview

ECE425


What is on an Integrated Circuit?

Actually only two types of “devices”:–Wires–Transistors

Most of the area are the wires!!

Presenter

Presentation Notes

There are many layers of wires (used to have 1-2 layer of metal, now advanced processes have 13-14 metal layers). Wires have electrical properties like resistance and capacitance. (Requires insulators and contacts between layers.) There are several kinds of transistors. In this class we will study MOS ICs, so we will work with MOS transistors. These transistors can be thought of as a voltage controlled switch. The voltage on one terminal of the transistor determines whether the other two terminals are connected or not.


Physical Topology of an Integrated Circuit

The transistors are built in the silicon, and then there are lots of wiring layers deposited on top. In cross-section it looks like (abstractly):

Silicon

Many more metals

Presenter

Presentation Notes

Transistors are fabricated on a thin silicon wafer that serve both as a mechanical support and electrical common point called substrate. There are two ways we can examine the physical layout of transistors from two perspectives This is a cross-section view obtained by slicing the wafer through the middle of a transistor and looking at it edgewise. The other view is the top view On this cross-section view we can see two transistors as well as two layers of metal (wires) Transistors are built into the silicone substrate The wires are laid out on top And the space between them is filled in with an insulation material (glass) The size of the transistors and wires is set by the mask dimensions and is limited by the manufacturing process.


Another View:

Can you guess what is shown here?

Top View

Cross Section

polygate

metalwire contactdiffusion

n-well

n-well

Presenter

Presentation Notes

On the top view we can see the same transistors and wires This is an example of an inverter gate implemented with two transistors The inverter is built on p-type substrate, meaning that nMOS transistors are diffused directly into this substrate The pMOS transistors therefore require n-wells – regions of the silicone with different type of dopant pMOS transistor is diffused into the n-well region Metal wire connects terminals of the two transistors. Gate terminals are built using polycrystalline silicone (polysilicon) This used to be metal, but as of 1970s polysilicon is used instead There is an insulation layer in-between - glass


TransistorsWhat kind of Mosfet is this – nfet or pfet?

Why?

0 0.5 1 1.5 2 2.50

100

200

300

400

500

600

Vds(V)

Id

s(

uA

)

IDS

sourcedraingate

Presenter

Presentation Notes

A metal-oxide-semiconductor (MOS) structure is created by superimposing several layers of conducting and insulation materials to form a sandwich-like structure that implements transistors. Transistor operation is controlled by an electric field, therefore these devices are called field effect transistors (FETs) Each transistor consists of a stack of the conducting gate, an insulation layer of silicon dioxide (glass), and the silicon wafer, called substrate or body, or bulk. An nMOS transistor is built with a p-type body and has regions of n-type semiconductor adjacent to the gate, called source and drain. The body is typically grounded. The gate is a control input. It affects the flow of the electrons between the source and drain. When the voltage on the gate is raised, a conducting path between the source and drain is formed, called channel, allowing current to flow between them. The transistor model is often described by its current-voltage curve which shows how much current can flow between the source and drain as a function of voltage between different terminals and substrate.


A MOSFET as a Switch Three terminal device

– source, drain• two ends of conductive path

– gate• controls conductive path

– operation• conducts when gate is high• open circuit when gate is low

– caveat• passes 0s well, not 1s

source

gate

drain

This description is for nMOS transistors. For pMOS everything is reversed. The source is the higher voltage terminal, and the transistor is on when the gate is much lower than the source. More on pMOS later

Presenter

Presentation Notes

We can think about MOS transistors as electrically controlled switches. Source and drain form two ends of a conducting path Gate controls this conductive path The nMOS transistor becomes a conductor when gate voltage is high and forms a closed circuit It forms an open circuit when gate voltage is low and almost no current flows between the terminals The pMOS transistor behaves in the opposite way. The high voltage is referred to as VDD and represents logic value 1 The low voltage is referred to as GROUND, or VSS, and represents logic value 0


Layout: The Fabrication Specification

The end of the design process must create a set of drawings, one for each layer needed in the manufacturing process– Layout drawings are complicated

• There are many rules about the geometry to make sure the circuits can be reliably manufactured

– Minimum width of wire, minimum spacing between wires, alignment rules

• The layers represent transistors and wires, and need to create the correct function

• Many rectangles for each transistor and wire, and there are millions of transistors and wires.

– Different layers are represented by different colors• People used to draw the layout on mylar (10s of transistors)• But not any more, now use CAD tools (to help with abstraction,

visualization, and constrain to design rules), and pre-made cells (for partitioning, hierarchy)


Simple Layout Example of a Simple Processor

Simple example Use hierarchy to hide

complexity Pads around chip Major blocks are

shown– Design is broken

into a controller that controls dataflow.

Colored regions are really many wires

Presenter

Presentation Notes

Physical design begins with a floorplan The floorplan estimates the area of major units in the chip and determines their relative placement The floorplan is essential in determining if the proposed design will fit on the chip and to estimate wiring lengths and wiring congestions. Shown here is a floorplan for a processor. The top-level blocks are Data Path, Register File, Controller, and I/O pads around the chip There are wires between these blocks


Layout This picture is an

expanded view of a portion of the layout seen on previous slide.

The next two slides:– Controller layout

• Handle instruction inputs

– Datapath layout• Moving data

around


Controller Layout

Right half shows cells in the design

Left half has the cells expanded to show the layout layers


Datapath Layout

Wire structure is more regular.– Words are 16bits

wide.– Each path is

repeated 16x Again

– Cells on right– Expanded cells on

left Transistor density is

higher

Presenter

Presentation Notes

Shown here are parts of the datapath layout Datapath layout is typically more structured as it frequently repeats the same circuitry for some number of bits, e.g., 16-bit design in this example. Much of the standard logic can be pre-built and reused in form of a cell library. Each cell implements a particular function – AND gate, etc. Cells then can be arranged together to implement mid-scale circuits, such as MUXes, adders, etc.


A Slightly More Powerful Processor

2.2cm

Rectangles

Transistors

Gates

Functions

Architecture


Or Intel Core 2 Duo

291,000,000 transistors


Design Partitioning

ECE425


The Challenge in VLSI Design – Managing Complexity

Simplify the design problem• Can’t understand 10B transistors, or 100B rectangles• Need to make less complex (and less numerous) models

– Abstraction• Simplified model for a thing, works well in some subset of the design

space– Modeling Constraints

• To ensure that the abstractions are valid• Might work if you violate constraints, but guarantees are off

Understand the underlying technology– Provide a feeling for what abstractions and constraints are needed.– Determine efficient solutions (make the right tradeoffs).

CAD tools use the abstractions and constraints to help us manage the complexity.

– They do not replace the need to understand the technology.– In fact, we also need to understand how tools work.


Reality of VLSI Design –Juggling Tradeoffs

Bottom line is $$$$ external “constraints” are

Vary with application domain– Portables (power - performance/area)– DRAM (area - features/performance)– DSP (design time/area - performance)– Military (robustness - power/performance)

Area

Design time and resources Robustness

Performance

Power

Presenter

Presentation Notes

In reality, the design process consists of a number of decision points about tradeoffs: The bottom line is how to make a cost-effective design Which satisfies the performance requirements As well as area and power requirements While minimizing the design time And possibly making the design to be robust and reusable for other purposes So, this is a multi-dimensional optimization problem that the VLSI designers have to work with Different application domains have different design constraints


Abstractions and DisciplinesHow to Deal with 109 Transistors

Digital abstraction– signals are 1 or 0

Switch abstraction– MOSFETs as simple

switches Gate abstraction

– Unidirectional elements– Separable timing

Synchronous abstraction– Race free logic– Function does not depend

on timing

Constrain the design space to simplify the design process– strike a balance between

design complexity and absolute performance

Partition the problem(Use hierarchy)– Module is a box with pins– apply recursively

Presenter

Presentation Notes

Such a huge complexity can be only managed via multiple layers of abstraction


Design Levels Specification

– what the system (or component) is supposed to do

Architecture– high-level design of

component• state defined• logic partitioned into

major blocks Logic

– gates, flip-flops, and the connections between them

Circuit– transistor circuits to realize

logic elements Device

– behavior of individual circuit elements

Layout– geometry used to define

and connect circuit elements

Process– steps used to define circuit

elements


Design Procedure and Tools

Concept– divider

Architecture– subtract/compare

Logical Implementation– ab+bc+ac– xor

Circuit Implementation– transistors

Physical layout + Verify– mask layers (rectangles)

C-modelling

Behavior modelling– Verilog or VHDL

Logic Synthesis– Design Analyzer

(Synopsys)– Verify Synthesis

• Static Timing

Place and Route– Silicon Ensemble

(Cadence)– Verify P&R

• Dynamic Timing


A More Realistic Design Flow

Schematic Entry Cell

CharacterizationLayout Entry

Standard Cell Library

3-D RLC Modeling

Tool

Wire ModelDevice model

Layout rules

ρ,σ, µLayers

Synthesis Library (Timing/Power/Area)

C-Model Verilog Behavioral

Model Verilog Structural

RTL

Structural Model

Parasitic Extraction LibraryPlace & Route Library (Ports)

Floorplan

Global Layout

Block Layout

Floorplan

P & R

Functional

DRC/ERC/LVSStatic/Dynamic Timing

FunctionalStatic Timing

Power/Area Scan/Testability

Synthesis P&R

Clock Routing/Analysis


Summary

MotivationHistory of VLSI designFabrication and Layout: Inverter

Cross sectionDesign Partitioning


Next Lecture IC Fabrication Readings

– Text 1.3, 1.5

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