Research notes on Vlsi

RESEARCH NOTES

Annual Review Meeting of the AVLSI Consortium

2009 – 2010

Advanced VLSI Design Laboratory Indian Institute of Technology, Kharagpur

Kharagpur - 721302, INDIA

Contents Analog and Mixed-Signal Design Parallel Pipeline ADC: Sounak Roy , Prof. Swapna Banerjee 3

Random Access Analog Memory(RA2M) for Video Signal Application: Nilanjan Chattaraj, Prof. A. S. Dhar

5

Digital Design VLSI Architecture for Separable Mellin Transform: Amartya Mazumdar and Prof.

Anindya S Dhar 7

Pre-Quantization for efficient realization of Automatic Speaker Recognition System and its real time implementation: Gourav Sarkar and Prof. Goutam Saha

9

High Performance Device (Semiconductor Process) Optimization of Wide Bandgap Compound Semiconductor Heterostructure Based RF

Front end Devices: Palash Das, Sudip Kundu and Prof. Dhrubes Biswas 11

Optimization of High Speed Compound Semiconductor Heterostructure Based RF Front end Devices: Partha Mukhopadhyay, Saptarshi Pathak and Prof. Dhrubes Biswas

13

MEMS & Signal Conditioning MEMS based Capacitive Accelerometer: Sougata Kar, Prof. Siddhartha Sen, and KBM

Swamy 15

12Bit 100KSamples/s Low Power SAR ADC for MEMS Interfacing Circuit: Abhisek Dey and Prof. T.K. Bhattacharyya

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Low Offset Variable Gain Instrumentation Amplifier for Piezoresistive Accelerometer: Anupam Dutta and Prof. Tarun Kanti Bhattacharyya

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Development of Surface Micro-machined MEMS based Varactor for RF Applications: Anirban Bhattacharya and Prof. Tarun Kanti Bhattacharyya

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Development of surface micro-machined components for implementing low frequency MEMS sensor: Subha Chakraborty and Prof. Tarun Kanti Bhattacharyya

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Development of MEMS based Piezoresistive Accelerometer for Aerospace Application: Francis Oliver Vinay Gomes and Prof. Tarun Kanti Bhattacharyya

25

Power Management Design and Implementation of a Single Chip Controller for Buck Derived Double-Ended

Transformer Coupled Dual Phase Converter: Rakesh Babu Panguloori, Prof. Debaprasad Kastha, Prof. Amit Patra and Giovanni Capodivacca

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Low Voltage Embedded DC-DC Converter: Kaushik Bhattacharyya and Prof. Pradip Mandal

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On-Chip Inductor-less DC-DC Boost Converter Using NORI Scheme: Prof. Pradip Mandal and Tamal Das

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Switched-Capacitor based Buck Converter Design using Current Limiter for better Efficiency and Output Ripple: Prof. Pradip Mandal and Tamal Das

35

High Efficiency Charge-Pump for Efficient DC-DC Step Up Conversion for Thick Gate CMOS Process: Prof. Pradip Mandal and Tamal Das

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Macro Modelling of Switched-Capacitor Type DC-DC Converter: Prof. Pradip Mandal and Tamal Das

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Digital PWM Control of Switchers: Architectures for Low-Power High-Resolution Operation: Syed Asif Eqbal and Prof. Amit Patra

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Design and On-Chip Implementation of a Single-Inductor Triple-Output DC-DC Buck Converter: Pradipta Patra and Prof. Amit Patra

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Design and Implementation of a Single-Inductor Multiple-Output Switcher with Boost and Buck/Boost/Inverted Outputs: Pradipta Patr and Prof. Amit Patra

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Design and Implementation of a Solar Photovoltaic Simulator: Avneet Singh, Ashish Ranjan Hota and Prof Amit Patra

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Energy Based DC-DC Boost Converter: Amit Patra , Pawan Gupta, and Jitendra Singh Kushwah

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Estimation of On-resistance and Current Distribution Profile in On-chip Power MOSFET Layout: Jyotirmoy Ghosh, Prof. Siddhartha Mukhopadhyay, Prof. Amit Patra and Barry Culpepper

52

Verification & CAD Use of PRES+ Models in High-Level Verification: S Bandyopadhyay, Prof. C R

Mandal and Prof. D Sarkar 54

VLSI Test Design of a Chip Emulation System for Test Development of Analog and Mixed Signal

Circuits: Rahul Bhattacharya and Prof. S.Mukhopadhyay 56

Wireless & RFIC Design and Optimization of Low-Power Low-Phase-Noise 2.4/4.8 GHz CMOS

Voltage Controlled Oscillator for Short Range Wireless Transceiver: Arivazhagan Perumal and T.K.Bhattacharyya

58

Dynamics and Synchronization of Delayed Feedback Nonlinear Oscillators: Pradeep Kumar Banerjee and Prof. T K Bhattacharyya

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Low Power Transmitter for Wireless Body Area Networks: Amitava Ghosh, Prof. Achintya Halder and Prof. Anindya Sundar Dhar

61

Low Power Receiver for Wireless Body Area Networks: Arunkumar Salimath and Prof. Achintya Halder

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Active Inductor based Multi-band LNA: V. Sanjay and Prof. Achintya Halder 65

ANNUAL REVIEW MEETING OF THE AVLSI CONSORTIUM, 2009 – 2010: RESEARCH NOTES

Parallel Pipeline ADC Sounak Roy, Prof. Swapna Banerjee

#Dept. of E & ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

Abstract— This work presents a parallel pipeline Analog to Digital Converter (ADC) of moderate resolution of 8 bits and high sampling rate of 250 MSPS. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch generated charge injection error in order to maintain good overall accuracy. Simulation showed non-linearity figures of -0.3173 LSB < DNL < 0.28 LSB and -0.0373 LSB < INL < 0.7 LSB. From the sinusoid response, SNDR turns out to be 49.6 dB which yields an ENOB of 7.94 bits. Power consumed by the ADC at the highest sampling rate is 108mW using a power supply of 1.8 V. The ADC occupies an area of 2.371mm2.

Keywords— Parallel Pipeline, Digital Correction, Double sampling, Time Interleaving

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION In the recent years, the ever-growing demand of high speed DSP units with minimal power consumption as brought about a new wave of enthusiasm towards low power circuit design. In order to interface with the continuous time signals these DSP units require data converters of similar speed, resolution and power consumption. In the fields of data communication, data converters of sampling speed in excess of 100 MSPS are required. Also, in order to get satisfactory accuracy, a resolution of 8 bit or more is essential. Such high speed and resolution automatically increases the die area and power consumption. Thus, the challenge lies in designing circuits with proper optimization of its building blocks.

II. RECENT RESEARCH ACTIVITIES

FIGURE I. A typical parallel pipeline ADC showing time interleaving

In TABLE I , we summarize the comparative results between the existing approaches and the ADC of the current work.

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TABLE I: A comparison table showing some recent works

Comparison Table Sampling Rate (MSPS)

Resolution DNL (LSB) INL (LSB) Power Dissipation (mW)

Remarks

[1] 200 10 bits 0.8 0.9 280 Four parallel time inter-leaved pipeline component

[2] 52 8 bits 0.2 1 250 Two parallel time inter-leaved pipeline components, with amplifiers shared laterally

[3] 150 8 bits 0.43 0.64 71 Two parallel time inter-leaved pipeline components,

This Work

250 8 bits -0.3173 <DNL<0.28

0.7 108 Two parallel time inter-leaved pipeline components,

III. RESEARCH ACCOMPLISHMENTS 1. Sounak Roy and Swapna Banerjee, “A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier,"

in IEEE International conference on VLSI Design, 2008. 2. Sanjay Kr. Dey, Sounak Roy and Swapna Banerjee, “A 10 -bit 2.5GS/s Low-Power BiCMOS THA for High Performance ADC," in International Conference on Computers and Devices for Communication (CODEC), 2006.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION This ADC represents a parallel pipeline ADC with high gain comparators consuming substantial power. Same

architecture can be followed with low power dynamic comparators to decrease the power consumption further. Also, lateral sharing of the ADC can be done to achieve superior performance after layout.

REFERENCES [1] L. Sumanen, M. Waltari, K.A.I. Halonen, “ A 10-bit 200-MS/s CMOS parallel pipeline A/D converter," Solid-State Circuits, IEEE Journal of, vol. 36, pp.1048-1055, July 2001. [2] K. Nagaraj, H.S. Fetterman, J. Anidjar, S.H. Lewis, R.G. Renninger, “ A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers," Solid-State Circuits, IEEE Journal of, vol. 32, pp. 312-320, Mar.1997. [3] S. Limotyrakis, S.D. Kulchycki, D.K. Su, B.A. Wooley, “A 150-MS/s 8-b 71-mW CMOS Time-Interleaved ADC," Solid-State Circuits, IEEE Journal of, vol. 40,pp. 1057-1067, May 2005.

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Random Access Analog Memory(RA2M) for Video Signal Application

Prof. A. S. Dhar # and Nilanjan Chattaraj* #Dept. of E&ECE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India [email protected]

*Nilanjan Chattaraj, AVDL Takshashila building, Kharagpur, WB 721302, India

[email protected]

Abstract— This is a novel memory architecture implementing Random Access Analog Memory (RA2M) for

storing unquantized samples of video signal of maximum 5 MHz bandwidth. The architecture consists of differential signal generator, differential sampler & memory refresher, RA2M memory cell, sample reconstructor and refresher controller block. These are implemented using switched capacitor technique. Supposing a sampling frequency of 20 MHz and frame rate of 25 frames/s, the implemented design gives 6 bit resolution in standard 0.18 μm CMOS process. The absence of amplitude quantization technique in this architecture eliminates the usage of ADC and DAC in data acquisition process and thus reduces the size and cost of the memory chip.

Keywords— Random Access Analog Memory, video application, low cost memory, analog memory

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Presently we use digital memory to store data. This is discrete time and discrete amplitude type signal processing.

When we store data into digital memory, first the data is sampled in discrete time domain, and then the amplitude of the sample is quantized. But as the technology is getting advanced day by day, we need to process the signals as fast as possible. The limitation on the usage of digital memory is as follows,

In Digital memory ADC and DAC are used For 8 bit quantization this uses 8 memory cells to store a sample of a signal

So this increases access time Increases size of chip As a consequence increases cost of chip

Some methodologies were introduced to resolve these above mentioned problems of digital memory by introducing the concept of analog memory with the following benefits.

a. unused ADC and DAC as unquantized samples are stored b. Thus to design low cost memory chip c. And to reduce chip size of memory organization

But the existing analog memory doesn’t have proper memory refreshing mechanism. A typical analog memory designed with floating gate is quite well known but as the operations are based on Fowler-Nordheim tunneling process so the memory read/write operations are inherently very slow. Here is a new technique designing RA2M with proper memory refreshing mechanism. This is based on charging memory cell capacitor by switched capacitor technique intended for video application. The reduced signal processing technique increases the speed to access the memory chip as well as reduces the cost and chip size. This is suitable for low resolution video application.

II. RECENT RESEARCH ACTIVITIES The on-going research by the IITKgpResearchGroup started in 2008. We stared with the basic operational concept and now have designed the circuit of single column architecture of the RA2M. The logical view of that is shown in the figure shown below.

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Conceptual view of RA2M architecture The specification of the above mention architecture is given below in the table along with the result simulated in cadence. Parameter Targeted Specifications Simulation Results

Input video signal voltage swing 0 V to 600 mV Variable pulse range: 0 V to 100 mV Video signal band width 5 MHz pulse period 50 ns and 40% duty cycle

Sampling frequency 20MHz 20MHz Frame rate 25 frames/s 25 frames/s

Supply voltage 1.8 V 1.8 V Sample hold time into memory 40 ms 40 ms Memory refresh period 10 ms 10 ms Read signal period 40 ms 40 ms Equivalent bit accuracy 8 bit 6 bit The average power dissipation for the tabulated specification is 4.1 mW.

III. RESEARCH ACCOMPLISHMENTS A part of the above research work has already been communicated to the engineering community in the form of

following communicated conference-paper.

N. Chattaraj, A. S. Dhar, “Random Access Analog Memory (RA2M) for video signal application” IEEE International Conference on Signal Processing and Communications, 2010

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION This proposed methodology has a limitation on precision. This limitation can be eliminated by introducing

modified algorithm and memory architecture technique. Along with these, in future with the advancement of solid state device and fabrication technology, there is scope of bright prospect to this low cost analog memory chip to store almost all type of data with very good precision and keeping all other advantages untouched.

REFERENCES [1] Floating-gate CMOS analog memory cell array Harrison, R.R.; Hasler, P.; Minch, B.A.;

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Volume 2, 31 May-3 June 1998 Page(s):204 - 207 vol.2

[2] An analog memory for a QCIF format image frame storage Gerna, D.; Brattoli, M.; Chioffi, E.; Colli, G.; Pasotti, M.; Tomasini, A.; Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., 1996 IEEE International Symposium on Volume 1, 12-15 May 1996 Page(s):289 - 292 vol.1 [3] Random access analog memory for early vision Franchi, E.; Tartagni, M.; Guerrieri, R.; Baccarani, G.; Solid-State Circuits, IEEE Journal of Volume 27, Issue 7, Jul 1992 Page(s):1105 – 1109, Digital Object Identifier 10.1109/4.142610 [4] A single-chip optical sensor with analog memory for motion detection Simoni, A.; Torelli, G.; Maloberti, F.; Sartori, A.; Plevridis, S.E.; Birbas, A.N.; Solid-State Circuits, IEEE Journal of Volume 30, Issue 7, July 1995 Page(s):800 – 806

Memory

Cell

Refresher

Sample and

hold block

Differential

voltage

generator

RA2M

memory cell

Signal

reconstructor

Analog signal in Analog signal out

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VLSI Architecture for Separable Mellin Transform Amartya Mazumdar and Prof. Anindya S Dhar Department of E & ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

{amartya.mazumdar, asd}@ece.iitkgp.ernet.in

Abstract— Mellin transform (MT) due to its scale invariance property finds itself in a myriad of applications. This work introduces row column decomposition (RCD) based, area efficient MT implementation for real time scale analysis of images. The proposed CORDIC based, multiplierless and fully pipeline architecture sidesteps the transposition operation in conventional RCD method resulting in higher throughput. The critical path in the architecture is an adder and a multiplexer equivalent. The latency depends on the CORDIC depth and image size. The architecture was simulated in Matlab for functional validity and prototyped on FPGA.

Keywords— Mellin transform, Row column decomposition, CORDIC, FPGA.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Mellin transform (MT) is a signal transform, analogous to Fourier transform (FT) which is widely used in signal processing owing to its distinct properties. Mellin transform is used, in 2D pattern matching [1], [2] and digital watermarking [3], as a transformation of an image to a space which is independent of scaling; i.e. the magnitudes of MTs of an image and its scaled version are similar, while the scale information can be retrieved from the phases. In 2D, MT is implemented as log-polar transformation (LPT) followed by FT, also known as Fourier-Mellin transform(FMT). FMT involves interpolation errors and hardware implementation constraints. Herein low pass filtering operation is required, which increases computation time. Past research work in [1] and [5] attempted to address the problem with partial success. Absence of faster methods of computation similar to FFT has restrained VLSI implementation of MT for real time applications. The on-going research is currently exploring that the problem may be solved by the means of an approach of applying Mellin transform by harnessing the separability property of 2D discrete Mellin transform (DMT) to implement it using the RCD[6] method, FIGURE I. The benefits of the proposed approach of 2D DMT are: • Interpolation error can be avoided, increasing the accuracy. • Image preprocessing before the transform can be avoided. The proposed methodology is first to show that real time implementation of scale analysis (i.e. identification of scaled images of same scene), and to determine the amount of scaling involved is feasible with an initial latency but high throughput. FIGURE I

II. RECENT RESEARCH ACTIVITIES When expression for 2D DMT given in [7] is used in a naive way, (N2) arithmetic operations are required to compute each M(ωx, ωy), yielding a total cost of (N4). This can be reduced to (N3) by employing the separability of kernel of 2D DMT. The 2D DMT can be broken using RCD method wherein a series of 1D DMT operation along rows and then along the columns is done. The architecture at the block level is shown in FIGURE II. For functional validation, 2D SDMT algorithm was operated on some standard images. The simulation results from Matlab, for a 512×512 ‘car and APCs’ image [8] are discussed here. Matlab scaling functions were used to generate both reference image (I) of size 200×200,and scaled image (Is) of size 150 × 150, FIGURE III (a),(b). The 2D SDMT when applied on both images generates the Mellin magnitude and phase, shown in FIGURE III (c), (d). FIGURE III (e) shows the linear dependency of the Mellin phase difference on scale axes. The 2D SDMT architecture was prototyped using Xilinx 9.2i targeting Virtex 2P FPGA with XC2VP70 device and FF1704 package.

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FIGURE III (a) I :200x200 image, (b) Is : 150x150 image, (c) Mellin Magnitude of I, (d) Mellin Phase of I, (e) Mellin Phase difference of I and Is The only implementation of Mellin transform is given in [7], which deals with 2D DDMT. Though the latency in both 2D DDMT and SDMT implementation are same, the throughput in SDMT is (N − 1) cycles against the (N − 1)2 cycles in DDMT. Still, faster methods of implementation (similar to FFT) cease to exists because the argument of the exponential FIGURE II in the Mellin kernel is not uniformly distributed. Another advantage of SDMT is the liberty to compute upto (N× N) Mellin points without any timing overhead.

III. RESEARCH ACCOMPLISHMENTS A part of the above research work has already been disseminated to the engineering community in the form of

following conference-paper. • Amartya Mazumdar and Anindya S Dhar,“VLSI Implementation of Discrete Mellin Transform for Real Time

Scale Analysis of Images”,TENCON,2009, 23-26 November, Singapore. • Amartya Mazumdar and Anindya S Dhar,”VLSI Architecture for Separable Mellin Transform”, IEEE India

Conference, 2009, 18-20 December, Ahmedabad.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION In next year we focus our research activity on: • Improved architecture for 2D DMT in terms of speed, power and area • Append translation and rotation invariance with scale invariance to build a RST invariant system.

REFERENCES [1] S. Derrode, “Robust and Efficient Fourier-Mellin Transform Approximations for Gray-Level image Reconstruction and Complete Invariant Description,” Comp. Vis. and Image Understanding, vol. 83, pp. 57–78, 2001. [2] A. Mittal,“Number Plate Recognition Using Analytical Fourier Mellin Transform,” Novel Algorithms and Techniques in Telecommunications, Automation and Industrial Electronics., pp. 37–42, doi: 10.1007/978-1-4020-8737-0 8. [3] J. K. Joseph and T. Pun, “Rotation, Scale and Translation Invariant Digital Image Watermarking,” IEEE Int. Conf. on Image Processing ICIP1997, citeseer.ist.psu.edu/ruanaidh97rotation.html. [4] P. E. Zwicke and I. Kiss, “ A new implementation of the Mellin Transform and its application to radar classification of ships,” Transactions on PAMI, VOL. PAMI-5, No. 2, March 1983. [5]X. Guo, Z. Xu,et.al, “An applicationof Fourier-Mellin transform in image registration,” CIT’05. [6] D. Gong, Y. He and Z. Cao, “New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, 2004. [7] Amartya Mazumdar and Anindya S Dhar,“VLSI Implementation of Discrete Mellin Transform for Real Time Scale Analysis of Images”,TENCON,2009, 23-26 November, Singapore. [8] “The USC-SIPI Image Database,” http://sipi.usc.edu/database/.

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Pre-Quantization for efficient realization of Automatic Speaker Recognition System and its real time implementation

Prof. Goutam Saha# and Gourav Sarkar* #Dept. of E&ECE, Indian Institute of Technology, Kharagpur


*Gourav Sarkar, AVDL Takshashila building, Kharagpur, West Bengal 721302, India

[email protected]

Abstract — The performance of classification step of speaker identification system is mainly governed by the

feature space of the speaker, which in turn is based on the frames selected at the pre-processing stage of identification. Hence frame selection is one of the vital steps for developing robust and efficient identification system. Better frame selection will not only aid in better performance but also in significant reduction of computational complexity. Further an efficient frame selection technique can improve the overall performance of this system significantly by selecting frames containing speaker specific information that varies from frame to frame depending on spoken text and environmental conditions. In pre-quantization (PQ) we select new frame sequence that is less than the original number of frames. The target is not only to reduce the number of frames but also to maintain reasonable identification accuracy. Since all the frames do not contribute equally to speaker identification performance and in some case deteriorate the score, selecting speaker specific frames have shown high improvement in performance in our analysis and that is even much better than performance obtained with all the speech frames. To establish the validity of the proposed methods, we use two different databases, POLYCOST (telephone speech) and YOHO (microphone speech).

Keywords— Distance measure, pre-quantization, noise, speaker recognition.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Automatic Speaker Recognition (ASR) is the use of a machine to recognize a person from a spoken phrase [1], [2]. ASR systems are probably the most natural and economical methods for solving the problems of unauthorized use of computer and communication systems and multilevel access control. Speaker recognition is a challenging pattern classification task; most of the computation originates from the distance or likelihood computations between the feature vectors of the unknown speaker and the models in the database. The identification time depends on the number of feature vectors, their dimensionality, the complexity of the speaker models, and the number of speakers. Specifically, the task in the project is to concentrate on optimizing the number of test vectors by pre-quantizing the test sequence prior to feature extraction during the identification process. Various strategies and methods are applied in achieving lower data requirement, higher decision accuracy and less computation complexity. At present there are three PQ techniques: Averaging, Random selection and Decimation. These methods of pre-quantization do not follow any valid basis of selecting the feature vectors. Implementing the identification technique using a dedicated hardware could be very useful to achieve smart units. In this context, the FPGA could offer an efficient technology to realize a pattern classification strategy. Hence our other purpose is to produce an efficient hardware speaker recognition system with an FPGA [3] that will act as a processing unit capable of performing recognition at a much faster rate than the software counterpart. Speech recognition systems have been developed for many real time applications but a high performance and robust speaker recognition system is still a challenge. Our interest is to develop a prototype of ASR in FPGA to gain insight into the complexity of a hardware solution.

II. RECENT RESEARCH ACTIVITIES Various statistical distance measures are used to select the suitable frames. It is found that a selected set of fewer

frames are enough to give high identification accuracy in noisy speech utterances. The probable reason behind this is additive noise results in flattening of log energy spectra and in turn reduces the variation in the MFCC [1].

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Use of entropy, energy, frequency spectrum spread and some combined techniques as criteria of frame selection improves the performance. Model based frame selection shows better performance in case of speaker verification. In Fig. 1 we show the performance of two of the strategies applied over 138 speakers of POLYCOST database.

Fig. 1. Plot showing the result

III. RESEARCH ACCOMPLISHMENTS We investigate a number of frame selection techniques for efficient speaker recognition. The following conclusions can be drawn from our study:

Distance measure based frame selection is more effective for noisy database. Voiced segment based PQ is effective when the training is also done with voiced segment. It is not only necessary to look for better frames, removing the undesirable one can show relevant results. The efficacy of the combined techniques that we proposed is established by two different databases. It is noticed that a high level of accuracy can be obtained by selecting only those frames that are more

specific to a particular speaker by modeling based frame selection. The accuracy of verification obtained by PQ is better than accuracy obtained with taking all the frame vectors.

Pre amplification of the audio signal is required before feeding it to FPGA board. Pre-processing and feature extraction are performed on the FPGA whereas modeling is done by Matlab.

The proposed techniques of frame selection will not only reduce the number of frame count during testing but also improves the speaker identification performance making the system more robust and efficient for real time implementation.

IV. SCOPE FOR FUTURE RESEARCH Although our frame selection techniques are simple and efficient, we still think a better frame selection technique

can be devised to select frames based on speaker specific content. In case of implementation, interfacing of compact flash with FPGA is to be done to access the model parameter.

REFERENCES [1] Campbell, “Speaker Recognition: A Tutorial,” Proc. of the IEEE, vol.85, no.9, Sept 1997, pp. 1437-1462. [2] T. Kinnunen, E. Karpov, and P. Franti, “Real-Time Speaker Identification and Verification,” IEEE Trans.

Speech and Audio Process., vol 14, no. 1, pp. 277-288. Jan. 2006. [3] Elmisery F.A., Khalil A.H., Salama A.E., Algeldawy F. “Adaptation of ANN for FPGA implementation and

its application for speaker identification ,” Proceedings - 2004 International Conference on Electrical, Electronic and Computer Engineering, ICEEC'04, pp. 317-320.

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Optimization of Wide Bandgap Compound Semiconductor Heterostructure Based RF Front End Devices

Prof. Dhrubes Biswas1, Palash Das1 and Sudip Kundu1 1 Dept. of E&ECE, Indian Institute of Technology, Kharagpur


Abstract— An intense outlook of Gallium Nitride (GaN) and its alloys always creates attention towards their

application in very high power, high temperature, high frequency devices as well as these devices are also better for high linearity demands. In AlGaN/GaN heterostructure, discontinuity of the spontaneous polarization vector at the AlGaN/GaN heterointerface and the piezoelectric charge due to lattice-mismatch of AlGaN on GaN induces high channel charge to the AlGaN/GaN HEMT. Higher channel charge increases the device’s current handling capability. SiC and Sapphire are the main substrates for AlGaN/GaN HEMT devices. Comparative study of the thermal simulation of different AlGaN/GaN HEMT devices has been executed.

Keywords— GaN/AlGaN HEMT, heterointerface, 2DEG, Piezoelectric polarization, Spontaneous polarization

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Among various materials and device technologies, the AlGaN/GaN high-electron mobility transistor seems to be

the most promising device for future high frequency RF / microwave front end power amplifier applications at high-temperature environment. This is possible for the full usage of advantageous GaN properties like - large band gap, large critical field, high saturation electron velocity and high sheet carrier density. Moreover, low noise amplifier (LNA) implemented with GaN-based HEMT devices in RF / microwave receivers can potentially eliminate the need for extra voltage limiting circuitry, which tends to degrade the noise performance of the LNA and the overall system. GaN being a wide bandgap material, it has very low leakage current. It is approximately 14 times lower than that of Si or GaAs material. As a result it can extensively be used in charge-coupled devices, non-volatile digital memories, reduced dark current photo detectors and high power amplifiers, switches, diodes etc. Although the DC and RF performance achieved in AlGaN/GaN HEMT is remarkable during the last decade by means of tremendous progresses of material growth capabilities and device processing, understanding of the fundamental material and device properties of AlGaN/GaN HEMTs are still a pending issue which makes the simulation of these devices more challenging than in other material systems.

II. RECENT RESEARCH ACTIVITIES Study of 2DEG with different aluminum percentage and AlGaN barrier thickness Aluminum percentage in AlGaN changes the polarization parameters which are the main factor for 2DEG

concentration at the AlGaN/GaN interface; therefore Al percentage in the barrier layer has to be studied in detail. Thickness of the AlGaN barrier layer is also equally important for the formation of the 2DEG. Increase in barrier thickness enhances 2DEG concentration. In both the cases, the 2DEG concentration varies linearly. We have chosen AlGaN barrier layer of 25 nm thickness with Al mole fraction of 0.35 for further AlGaN/GaN HEMT research.

Study of AlGaN / GaN HEMT DC and RF Characteristics Using ATLAS TCAD tools, namely DEVEDIT as the device structure editor and ATLAS as the device simulator have been used

to characterize the DC and RF response of the AlGaN/GaN HEMT device. To perform the detail study of the characteristics of the AlGaN/GaN HEMT, SiC and sapphire both the substrates have been used. We have mainly studied the following AlGaN/GaN HEMT devices in detail for this research purpose: devices having gate length of 1 and 4 μm on SiC and sapphire substrate. Throughout this research we attempted to stay within the ranges of parametric values found in the literature whenever possible. Fermi-Dirac statistics, bandgap narrowing effect (BGN), drift-diffusion, Shockley-Read-Hall (SRH) for carrier generation / recombination, and lattice heating for thermal

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simulation were chosen. “Farahmand Modified Caughey Thomas” (FMCT) and field dependent mobility (FLDMOB) models have been used.

The output characteristics of the HEMTs showed that the saturation drain current decreases (because of mobility

degradation with increasing device temperature) with increasing drain bias because of lattice heating effect, which is known as negative differential conductivity (NDC) effect. The lattice temperature distribution of AlGaN/GaN HEMT demonstrated a hot spot near the edge of the gate in the gate-drain access regions. Considering the lattice heating effect, we can see the similar kind of effect for transfer characteristics also as we observed in the output characteristics. In this case also, the devices on SiC substrate can provide transconductance with higher peak and flatter response than the devices on sapphire substrate. The results are shown in Fig 1.

Fig 1. Comparison of (a) output characteristics, and (b) transfer characteristics for the devices having gate length of

1 μm on 100 μm SiC and sapphire substrate In frequency response we can observe that the cutoff frequencies increase with decreasing gate length. Using SiC

substrate we achieved unity current gain cutoff frequencies of 3.4 and 13 GHz for 4 μm and 1 μm gate length devices. The corresponding power gain cutoff frequencies were 8 and 24 GHz respectively. We have also studied the leakage current response of the devices. The devices on sapphire substrate are more pronounced for gate leakage current, due to huge lattice heating effect, than the devices on SiC substrate. The devices on sapphire substrate suffered almost six order higher gate leakage current than the devices on SiC substrate.

III. RESEARCH ACCOMPLISHMENTS 1. “Simulation of AlGaN/GaN HEMT on 4H-SiC substrate including self-heating effect for Ka band high power

amplifier applications”, Sudip Kundu,, Palash Das, Saptarshi Pathak, Partha Mukhopadhyay, Jasvardhan Reddy, Edward Y. Chang and Dhrubes Biswas, ICONSAT 2010, Mumbai

2. “Optimized Bandgap Engineered AlGaN/GaN HEMT for High Power Amplifier at Ku Band Applications”, Sudip Kundu,, Palash Das, Saptarshi Pathak, Partha Mukhopadhyay, Jasvardhan Reddy, Edward Y. Chang and Dhrubes Biswas, IWPSD 2009, Delhi.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION Study of compositional grading and breakdown voltage will be important area of investigation as further extension

to this research. Detailed study of the performance improvement of the AlGaN/GaN DHHEMT will also be an extremely significant future work as supplement to this thesis. The response of the AlGaN/GaN HEMTs on Si, SiCOI, GaNOI substrates can be made in depth in view of performance improvement of the AlGaN/GaN HEMT devices in a cost-effective way.

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12


Optimization of High Speed Compound Semiconductor Heterostructure Based RF Front End Devices

Prof. Dhrubes Biswas1, Partha Mukhopadhyay1 and Saptarshi Pathak1 1 Dept. of E&ECE, Indian Institute of Technology, Kharagpur; Kharagpur, WB 721302, India

[email protected]

Abstract— Superior carrier transport and other favorable electronic properties of InAlAs/InGaAs metamorphic High Electron Mobility Transistor (MHEMT) have the capability to achieve high power at very high frequency with high linearity. Optimization of barrier, channel and delta doping paves the further improvement of our MHEMT device. SILVACO based simulations are extensively being used to observe the effect of bulk doping, delta doping, Aluminum mole fraction in barrier, channel indium concentration and thickness of both barrier and channel, on the DC and RF characteristics of the device. Advanced device design of novel penta-composite channel of 0.25 μm InAlAs/InGaAs MHEMT has been reported for the first time in composite channel HEMT. Comparison between MHEMT and PHEMT has also been emphasized with respect to transconductance (gm) and drain current (ID).

Keywords— MHEMT, PHEMT, 2-DEG, composite channel, IP3, gm

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION The main objective is to achieve the uncompromised device performances by the optimization of HEMT on a metamorphic substrate. Changes in the Al percentage in the barrier and In percentage in the channel region are the main parameters for the confinement of the 2DEG charges in the channel region. Another main parameter for this confinement is the upper-lower delta-doping ratio. Use of pseudomorphic and metamorphic technique in the buffer improves the performances of the device reducing the misfit dislocation related traps which generates in the heterointerface of two semiconductor devices due to lattice mismatch. The prime motivation behind the increasing Indium mole fraction in channel is to increase conduction band discontinuity, which increases carrier confinement in the channel. Higher Indium percent in the material also has lower electron effective mass which enhances the mobility. However, higher Indium in channel results in phase in-homogeneities due to the onset of kink effect and both breakdown voltage (BV) and gm flatness degrade. This problem can be solved by using composite channel structure where multiple materials are used with linear grading in channel to increase Indium mole fraction and accommodate the lattice mismatch at the same time.

II. RECENT RESEARCH ACTIVITIES In our research we have chosen 22% Al percentage in the barrier region and 22% In percentage in the channel

region and 8 × 1012/2 × 1012 cm-2 delta-doping ratio for single channel AlGaAs/InGaAs HEMT. We have also chosen 52% Al in the barrier and 53% In in the channel for single channel, single delta-doped InP-HEMT. The output characteristics of the single channel AlGaAs/InGaAs HEMTs as shown in Fig 1 revealed that the saturated drain current and transconductance gradually increases with both increment of In percentage in channel and delta doping. In frequency response we have observed that the cut-off frequencies increase with decreasing gate length and achieved ft and fmax is 115 GHz and 175 GHz, respectively for 0.10 µm.

Extension of the above mentioned work is the advanced design of InAlAs/InGaAs metamorphic HEMT with multi-

layer channel structure and achieved high current of 1029 mA/mm and high gm of 648 mS/mm, as shown in Fig 2, while operating at high frequency, fT of 125 GHz and fmax of 250 GHz. This structure shows high drain resistance i.e. less fluctuation at high voltage and high linearity than conventional PHEMTs and MHEMTs. Our structure has gate length, Lg of 0.25 µm, which is much higher than current technology, while achieving very high fT which is remarkable. It can be attributed to the efficient device structure and choice of materials. This higher gate length leads to lower process costs with high performance devices which can be valuable for low cost wireless / space communications.

13


(a)

(b) Fig 1: Comparison of (a) transconductances and saturated drain current for different In concentration in channel (b)

saturated drain current and transconductances for different delta-doping concentration.

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III. RESEARCH ACCOMPLISHMENTS [1] “W-band Penta-Composite Channel InAlAs/InGaAs Metamorphic HEMT for High Power Application and Comparison with Pseudomorphic HEMT” 2010 International Conference On Compound Semiconductor Manufacturing Technology (CS ManTech), May 17th - 20st, 2010 Marriott – Waterfront, Portland, Oregon, USA

[2] “Five Channel InAlAs/InGaAs MHEMT for High Frequency Power Amplifier Application and Comparison over Conventional PHEMT”; IEEE-NANO–2009, Italy

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION A better future approach should integrate the superior properties of compound semiconductors with the mature

technology of silicon; which can be done by some well-developed sophisticated crystal growth techniques like molecular beam epitaxy (MBE) / metal organic chemical vapor deposition (MOCVD). A better future approach should integrate the superior properties of compound semiconductors with the mature technology of silicon; which can be done by some well-developed sophisticated crystal growth techniques like molecular beam epitaxy (MBE) / metal organic chemical vapor deposition (MOCVD). the growth of GaAs, InP epitaxial layer grown on Si substrate through relaxed metamorphic buffer. The best approach will be to grow InP active layers on silicon through GaAs layer as lattice mismatch between GaAs and Silicon is 4% which helps to generate less dislocation in heterostructure than that of InP on Si (8%).

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14


MEMS Based Capacitive Accelerometer Prof. Siddhartha Sen, Sougata Kar and KBM Swamy

Dept. of Electrical Engineering, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected], [email protected], [email protected] Abstract— Challenges in development of a surface micro-machined MEMS capacitive accelerometer are threefold: (a) successful fabrication of stiction free MEMS structure, (b) development of signal conditioning circuit to detect femto Farad level capacitance change and (c) integration and testing. This work reports the successful development of an automotive grade surface micro-machined MEMS capacitive accelerometer carried out at IIT Kharagpur. Keywords— MEMS, ASIC, Noise, Linearity, Packaging, Integration.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Micro-accelerometers alone have the second largest sales volume after micro-pressure sensors. The large volume demand for accelerometers is due to their automotive applications, where they are used to activate safety systems including air bags, to implement vehicle stability systems and electronic suspension. They are widely used in biomedical applications also for activity monitoring and in other numerous consumer applications recently.

Although considerable work is under progress around the world for micro-sensor development, the indigenous technology in this area is still lacking. In fact, little attention has been paid so far for development of smart micro-sensors with the available technologies of MEMS and integrated circuit. There are lot of design, packaging and testing related issues required to be addressed to develop a complete accelerometer system with integrated MEMS and ASIC which include:

• A standardized MEMS processes is not yet available unlike IC technology; hence separate process needs to be developed for individual devices. So care must taken to include various process related effects in the design stage using different software tools.

• The effects of Thermal and Residual stress must be considered at the time of design [1]. • Cross-axis Sensitivity is one of the critical issues in MEMS design [2]. • Stiction is one of the major problems in thin film surface micro machined devices which must be properly

addressed during the time of structural release and also during use [1]. • Detection of small capacitance in the order of few femto-farad (fF) is a challenging task while the gate-oxide

capacitance of a MOSFET is in that range [3]. • Effect of Noise must be considered to minimize the input referred noise and increase the minimum level of signal

detection [4]. • Linearity, Effect of PVT variations should be considered to improve the system performance [4]. • There is lack of knowledge on packaging and integration and testing methodologies.

II. RECENT RESEARCH ACTIVITIES A comprehensive attempt for development of a Poly-Si surface micro-machined capacitive accelerometer successfully tried in India. Poly-Si surface micro-machined MEMS sensor is designed, fabricated at MEMSCAP, France and tested at different levels. The basic configuration used is a comb type, differential capacitance structure. A capacitance transduction ASIC is designed in UMC 180nm CMOS technology and fabricated. Test results show that it is capable of detecting fF level capacitance variation generated in the MEMS structure. Different types of packaging configurations made successfully in collaboration with SCL, Chandigarh and exhaustive testing methodologies developed. Various integration schemes for MEMS and ASIC (both commercially available ASIC MS3110 and IIT ASIC) integration devised and successfully achieved. Static testing and dynamic testing have been carried out to evaluate the performance of the complete system with reference to ADXL150 accelerometer from Analog Devices.

15


Fig. 1(a): Fabricated MEMS Structure Fig. 1(b): Packaged MEMS Devices Fig. 1(c): MEMS + ASIC Hybrid Package Fig. 1(d): PCB with MEMS and IIT ASIC

Fig. 1(e): Frequency response of the MEMS structure Fig. 1(f): Dynamic Test Set up Fig. 1(g): Dynamic Test Result

III. RESEARCH ACCOMPLISHMENTS A part of the above research work has already been disseminated to the engineering community in the form of following conference-papers [5-7].

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION

Detailed characterization of the total system needs diligent attention and requires to be carried out further along with exhaustive field testing of the accelerometer. Further testing and analysis to be carried out towards understanding of some unexpected phenomena observed while testing. There is definite scope for improvement in both MEMS and ASIC design to achieve better performance. Finally more collaborative effort with industry is necessary to build the complete integrated accelerometer system.

REFERENCES

[1] Wolfgang Kuehnel, “Modeling of the mechanical behavior of a differential capacitor acceleration sensor, Sensors and actuators”, A 48, 1995, 101-108. [2] Stephen D Senturia, “Microsystem design”, Kluwer Academic Publishers, 2001. [3] Boser B.E. “Electronics for Micromachined Inertial Sensors”, International Conference on Solid State Sensors and Actuators, 1997. [4] P.E. Allen & D.R.Holberg, “CMOS Analog Circuit Design”, 2nd Edition, Oxford University Press. [5] Swamy K.B.M, T.P.Singh, S.Kar, S.Sen, “Design, Fabrication and Testing of Comb type Capacitive Acceleration Sensor”, 3rd National Conference on MEMS, Smart Structures and Materials, ISSS – 2009, CGCRI-Kolkata, Oct. 14-16, 2009. [6] Swamy K.B.M, T. Praveen Singh, S.Kar, S.Das, S.Sen, “Design of Centrally Anchored In-Plane Micro- Accelerometer”, International Conference on MEMS (ICMEMS 2009), IIT-Madras, Jan. 3-5, 2009. [7] Swamy K.B.M, T.Praveen Singh, Sougata Kar, S.Sen, “Design of Different Structural Element Configurations for applications in Micro Sensors and Actuators”, International Conference on Active/Smart materials, TCE, Madurai, Jan. 7-9, 2009. Acknowledgement: The work has been carried out under project “Development of MEMS based Capacitive Accelerometer” sponsored by Department of Information Technology, MCIT, New Delhi.

16


12Bit 100KSamples/s Low Power SAR ADC For MEMS Interfacing Circuit

Abhisek Dey1, T.K. Bhattacharyya2 #Dept. of E & ECE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India [email protected], [email protected]

Abstract — This work is based on the design of a 12bit 100KSamples/s Successive Approximation Register ADC. The ADC is a very useful component in the design of MEMS interfacing circuits. A novel switching scheme has been employed to reduce the area of the ADC significantly while making it power efficient. A new 12-bit 100 KS/s analog-to-digital converter (ADC) is proposed for low-power low-area CMOS integrated systems. This design is based on an improved capacitor array DAC with a unity gain buffer that minimizes the overall area and power consumption of the system. This design is suitable for standard CMOS technology with low-power VLSI implementation for MEMS interfacing circuits. It is well applied when embedded into system-on-chip (SoC) circuit designs.

Keywords— 12bit, SAR, ADC, MEMS Interfacing,

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Recent trend in mixed-signal ASIC design needs more functionality integrated in one chip. Analog-to-digital

converters(ADCs) are a key element in mixed-signal ICs. When looking at precision ADCs with sampling rates of less than 1 Mega-Sample-Per-Second (MSPS), there are two predominant choices - the Successive Approximation Register architecture (SAR) and the Delta-Sigma architecture. The latter one, despite having very high resolution, very good linearity, no trimming, and relaxed anti-aliasing requirements, suffers from the disadvantages of latency, larger size, and higher power consumption. So, considering the aforesaid facts, Successive Approximation Register(SAR) ADC is a suitable solution for low-power application, when the signal band is in up to about 1 MHZ and the resolution ranges between 10 to 12 bit. The existing SAR ADCs fail to give a satisfactory performance when it comes to a matter of trade-off among the area, power, speed, and resolution.

Past research works in [2] and [3] attempted to address the problem of trade-off with partial success. The on-going research activity by the Analog and Mixed signal Research Group is currently exploring that the problem may be solved by the means of an innovative approach of SAR ADC design which incorporates an intelligent switching scheme to reduce the area keeping the power, speed, and resolution within the acceptable limit.

II. RECENT RESEARCH ACTIVITIES The on-going research by the Analog and Mixed signal Research Group started in 2009. FIGURE I shows the block

diagram of the SAR ADC. A capacitive DAC samples the input voltage and together with a shift register produce an approximation of the input signal. The comparator, composed of preamps and a latch, compares the DAC output with a reference voltage and determines whether this approximation is too high or too low. The comparator output controls the output of the SA Register which, in turn, modifies the analog voltage stored by the DAC. This process is repeated until either the DAC output matches the reference voltage of the comparator or the input voltage difference of the comparator falls below the voltage specified by the 1LSB of the ADC.

A new switching scheme has been incorporated to design the CDAC of the ADC. The entire array of the caps unlike the binary weighted one is divided into two blocks i.e. MSB array and LSB array. It includes a unity gain buffer to work properly. The area is reduced significantly with this technique. Instead of using 212 C we are using effectively 27 C and a unity gain buffer. Since the cap value is proportional to the size of cap, the area reduction is remarkable, despite using a buffer which can still be a good bargain. Also, the power consumption of the whole system is expected to be within appreciable range due to the switching scheme.

17


FIGURE I. Block diagram of SAR ADC.

(a) (b)

FIGURE II. (a)Simulation result of the SAR ADC with 800mV input. (b) Magnified portion of the output for the 4 LSBs.

III. SCOPE FOR FUTURE RESEARCH COLLABORATION The comparator part of the ADC is yet to be designed. The design of the comparator is very crucial as it needs an

input offset less than 400µV. The methodology and architecture of the ADC which we demonstrated successfully for the low power application,

are expected to be working in MEMS interfacing circuits.

REFERENCES [1] IEEE Document Formatting Guidelines Document. [2] B.P. Ginsburg and A.P. Chandrakasan, “An Energy-Efficent Charge Recycling Approach for a SAR Converter With Capacitive DAC,”

IEEE. International Symposium on Circuit and Systems, Vol. 1, pp.184-187, May. 2005. [3] J.S. Lee and I.C. Park, “Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters,” Proc. Int. Symp.

on Circuits and Systems, May 2008, Seattle, WA, pp. 236-239.

18


Low Offset Variable Gain Instrumentation Amplifier for Piezoresistive Accelerometer

Prof. Tarun Kanti Bhattacharyya# and Anupam Dutta* #Dept. of E&ECE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India #[email protected]

*Advanced VLSI Design Laboratory, Takshashila building, Indian Institute of Technology, Kharagpur, WB 721302, India

*[email protected]

Abstract— This work implements a low offset Variable Gain Instrumentation Amplifier (VGIA) for MEMS based

wheat-stone bridge type sensors. The design can accommodate a input dynamic range of 92dB (peak to peak amplitude from 500nV to 20mV) with an input referred offset less then 100nV and provides a variable gain from 33dB to 120dB. Also, a pure analog module is designed and integrated with the main amplifier to dynamically cancel the temperature dependence of the sensor sensitivity and the sensor output offset. UMC 0.18 micron CMOS process technology is used to implement the design.

Keywords— signal conditioning circuit, smart MEMS, low offset amplifier, piezoresistive sensor interfacing circuit.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION The state-of-the-art fabrication technology has come up with several highly sensitive miniaturized MEMS based

sensors, like accelerometer, pressure sensor, gas sensor etc. . But the output voltage of the those high precision sensors is in the range of micro volts. Hence a very low input referred offset amplifier is required to amplify the signal in moderate milli volt range. Along with this, the temperature dependence and high tolerance of the fabricated piezoresistors cause two major disadvantages:

• Sensor sensitivity varies with temperature. • Sensor output offset varies with temperature.

Also the sensor sensitivity is directly proportional to the sensor bias voltage and one can not apply a bias voltage less then 5 volt without severely sacrificing the sensitivity. On the other hand the feature size and the maximum bias voltage of commercial CMOS process is scaling down day by day. So a new biasing scheme is to be formulated to decouple the sensitivity versus CMOS process scaling trade-off. The aim of this research is to find a low cost, user friendly, completely analog solution of the above mentioned problems.

II. RECENT RESEARCH ACTIVITIES The on-going research by the IITKgpResearchGroup started in 2009. We stared the VGIA for piezoresistive

accelerometer, which is designed to measure acceleration from 2mg to 20g, and came up with the following block diagram:

FIGURE 1. Basic block diagram of the VGIA

Chopper

4 cascaded amplifier stages with variable

gain & internal offset cancellation

Chopper

Stages of continuous time

and switched capacitor Low

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FIGURE 2. Block diagram of the total scheme

FIGURE 3. Simulation result showing a output of 120mV for an input of 200nV. Right portion is the DFT of output signal

Detail block level specification, architecture has been derived and first cut design of the VGIA is completed.

Currently, the offset correction logic block is being designed. It is expected that with-in next 4-5 months the chip will be ready for tape out.

III. SCOPE FOR FUTURE RESEARCH COLLABORATION In this design no constraint on chip area and power consumption is imposed. Though the power consumption is

expected to be less then 8mW, there is ample scope to improve these figures. Again, several specialized topology can be used to improve the applicability of the chip not only for accelerometer.

REFERENCES [1] J.F. Witte, J.H. Huijsing and K.A.A. Makinwa, A Chopper and Auto-Zero Offset-Stabilized CMOS Instrumentation Amplifier, Symposium on VLSI Circuits Digest of Technical Papers, 2009. [2] Michele Dei, Paolo Bruschi, and Massimo piotto, Design of CMOS Chopper Amplifier for Thermal Sensor Interfacing, 2008. [3] Jannik Hammel Nielsen and Erik Bruun, A CMOS Low-Noise Instrumentation Amplifier Using Chopper Modulation, Analog Integrated Circuits and Signal Processing 42, 65-76, 2005. [4] Anton Bakker, Kevin Thiele, and Johan H. Huijsing, A CMOS Nested-Chopper Instrumentation amplifier with 100-nV Offset, IEEE Journal of Solid-State Circuits, VOL. 35, NO. 12, 2000. [5] A. Bakker, K. Thiele, J. H. Huijsing, A CMOS Nested-Chopper Instrumentation Amplifierwith 100-nV offset, IEEE Journal of Solid State Circuits, Vol. 35, No. 12, pp.18877-1883, December 2000. [6] C. Menolfi, Q. Huang, A fully integrated CMOS Instrumentation Amplifier with Submicrovolt Offset, IEEE Journal of Solid State Circuits, pp. 415-420, March 1999.

sensor VGIA (Figure 1)

sensitivity and offset calculation logic for dynamic correction adder Corrected output

Feedback to the Adaptive Bridge bias

Temperature information

20


Development of Surface Micro-Machined MEMS Based Varactor for RF Applications

Anirban Bhattacharya and Prof. Tarun Kanti Bhattacharyya Dept. of E&ECE, Indian Institute of Technology, Kharagpur


Abstract— MEMS technology has already proved to be one of the most promising and efficient technology for RF

applications due to its low loss and excellent isolation properties. However, interfacing MEMS devices with the MOS based circuit components has always been an issue. This research work concentrates on the development of MEMS based varactor for different high frequency applications in telecommunication circuits such as voltage controlled oscillator (VCO) etc.

Keywords— MEMS, VCO, varactor, surface micromachining, phase noise.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION MEMS based devices are nowadays being used in several microwave applications. Examples of such kind

includes MEMS based switches, phase shifters, inductors and reconfigurable filters and antennas. But the integration of MEMS devices with the available CMOS based circuit components is still a big challenge as it always asks for expensive process customization. This research thus attempts to develop MEMS based circuit components to address this challenge. The following developments have been taken up as research problem.

• Problem #1 Development of surface micro-machined varactor. • Problem #2 Integration of this varactor in the tank circuit of a CMOS based LC tuned VCO for low phase

noise performance.

References [1] and [2] already presented works in this direction by implementing VCO using MEMS varactor. The advantages of implementing such MEMS based circuit are [1-2] are as follows

• Nearly 1.5:1 capacitance tuning ratio. • The loss of the capacitors are very low even at several GHz frequency range. • Very high Q factor (nearly 20) of the structures. • Very low power dissipation. • Low phase noise performance.

II. RECENT RESEARCH ACTIVITIES The varactor has been designed and simulated following the PolyMUMPs process flow using CoventorWare

software. PolyMUMPs is basically a multi-user surface-micromachining process with three polysilicon layers. This device is essentially a parallel plate varactor, with comparatively low actuation voltage and low cross-axis sensitivity. The bottom electrode has been implemented in the Poly0 layer and the movable proof-mass in the Poly1 layer. Several holes are introduced to reduce the squeezed film damping effect as well as to facilitate the etching of the sacrificial oxide layer between the two polysilicon layers. Four dimples are also added to the proof-mass structure to avoid stiction during the release of the structure.

Fig. 1 shows the SEM image of the varactor. In fig. 2, the measured vibration spectrum in LDV is shown. Fig. 3 shows the measured C-V curve of the structure.

A low phase noise CMOS VCO with LC tank circuit has been designed in UMC 130nm RFCMOS technology where provision has been kept to incorporate the MEMS varactor in the tank circuit using wire bonding technique. The bond wire parasitics have been taken into account while designing the VCO. In fig. 4, the layout of the VCO is shown.

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Fig. 1: SEM image of the varactor

Fig. 3: Measured C-V curve

Fig. 2: : LDV spectrum at 27.5 kHz

Fig. 4: Layout of the VCO


following conference-papers. • Conference papers [3-4].

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION After the tapeout of the VCO structure, we propose a wire bonding method where two such varactor structures are

to be wire bonded to the VCO tank to complete the MEMS based VCO circuit. Then, testing and characterization of the entire system is to be done.

REFERENCES [1] A. Dec and Ken Suyama, “Microwave MEMS-Based Voltage Controlled Oscillators”, IEEE Transactions on Microwave Theory and

Techniques, Vol. 48, no. 11, pp. 1943 – 1949, Nov. 2000. [2] A. Dec and Ken Suyama, “Micromachined Electro-Mechanically Tunable Capacitors and Their Applications to RF IC’s”, IEEE

Transactions on Microwave Theory and Techniques, Vol. 46, no. 12, pp. 2587 – 2596, Dec. 1998. [3] A Bhattacharya, R. Ray Chaudhuri, A. Ray Chaudhuri, S. Chakraborty and T.K. Bhattacharyya, “Reduced Order Macromodel Extraction of

MEMS Based Varactor and Its System Level Simulation for RF Applications”, 4th International Conference on Computers and Devices for Communication (CODEC 09), pp. 1-4, Dec. 2009.

[4] Anirban Bhattacharya, Ritesh Ray Chaudhuri, Ashesh Ray Chaudhuri, Subha Chakraborty and T.K. Bhattacharyya, “Squeezed-Film Damping Performance Comparison of Perforated and Non-perforated Surface Micromachined Quad-beam Structures”, Third National Conference on MEMS, Smart Structures and Materials (ISSS – 2009), pp. 118-121, Oct. 2009.

22


Development of Surface Micro-Machined Components for Implementing Low Frequency MEMS Sensor

Subha Chakraborty and Prof. Tarun Kanti Bhattacharyya Dept. of E&ECE, Indian Institute of Technology, Kharagpur


Abstract— MEMS technology has already proved to be one of the most promising and efficient technology for

sensor applications. However interfacing the sensor block with the immediately following signal conditioning block has always been an issue. This research work therefore concentrates on development of MEMS based circuit elements for very low frequency signal conditioning applications in MEMS sensors. The aim of the research is oriented about development of MEMS based digital blocks and voltage comparator blocks, which are essentially the most fundamental element in digital and mixed signal stages.

Keywords— MEMS, surface micromachining, cantilever, binary, comparator.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION MEMS sensors are nowadays widely used in many low frequency signal transducing applications. But the

integration of MEMS sensor with the immediately following signal conditioning circuit has always been an challenge. Although hybrid or even monolithic integration of MEMS with CMOS based circuit is available, it always asks for expensive process customization. This research thus attempts to develop MEMS based circuit components to address this challenge. The following developments have been taken up as research problem.

• Problem #1 Development of surface micro-machined binary logic implementation • Problem #2 Development of surface micro-machined voltage comparator for mixed signal stages

References [1] and [2] already present works in this direction by implementing digital logic using MEMS

technology. The advantages of implementing such MEMS based circuit are [1-2] are as follows • Intrinsic integrity with standard MEMS sensors • Can be fabricated with the sensor block in the same MEMS process • Very low power dissipation and leakage issues • Utility in very low frequency applications such as automobile or spacecraft accelerometer, electro-

physiological signal

Apart from proposing and fabricating these structures this research work attempts to develop a complete analytical method for behavioural modelling and performance evaluation of the structures.

II. RECENT RESEARCH ACTIVITIES Digital inverter and universal gate have been designed and fabricated using PolyMUMPs surface micromachining

process [5,6]. The basic principle of operation of the structures is electrostatic actuation of surface micro-machined cantilevers to make and brake electronic switches. The structures have been designed for three different specifications of operating voltages.

• 5 volt, the cantilevers are nearly 400 μm long, 10 μm wide and 2 μm in thickness • 3.3 volt, the cantilevers are nearly 170 μm long, 10 μm wide and 1.5 μm in thickness • 1 volt, the cantilevers are nearly 340 μm long, 10 μm wide and 1.5 μm in thickness

A comprehensive analytical methodology has been adopted for designing the structures to meet the voltage specifications. The theoretical results were validated and fine-tuned using finite element method based simulation in CoventorWare simulation platform. Further system level simulation were carried out to create macro-models of the beams in Saber Architect for further and larger digital block implementation. The devices were fabricated using PolyMUMPs surface micromachining technology. Initial vibration characterization and static switch performance

23


evaluation have already been performed on the structures in the wafer level, using wafer prober, Laser Doppler Vibrometer. Fig. 1 shows the SEM image of the fabricated 3.3 volt operating voltage inverter and fig. 2 shows the experimentally observer fundamental mode shape of the same.

FIGURE I. SEM image of the fabricated MEMS inverter (3.3 volt version)

FIGURE II. Fundamental mode shape of the beam as observed in LDV


following conference-papers. • Conference papers [3-6].

IV. SCOPE FOR FUTURE RESEARCH The digital blocks are yet to be functionally characterized for their transient response and voltage transfer

characteristics. The devices will be wire bonded on a custom made printed circuit board and thorough testing will be carried out in near future. The comparator design and development have been initiated, but an extensive performance evaluation is yet to be performed. Works in these directions will be reported in near future.

REFERENCES [5] Sae-Won Lee, Robert Johnstone and Ash M. Parameswaram, “MEMS mechanical logic unit: Design and fabrication with Micragem and

PolyMUMPs”, IEEE Canadian Conference on Electrical and Computer Engineering, 1–4 May, 2005, pp 1513–1516. [6] Chun-Yin Tsai, Wei-Ting Kuo, Chi-Bao Lin and Tsung-Lin Chen, “Design and fabrication of MEMS logic gates”, Journal of Micromech.

Microeng, vol. 18, 045001 (10pp), April 2008. [7] Subha Chakraborty, Ashesh Ray Chaudhuri, Tarun Kanti Bhattacharyya, “Design and Analysis of MEMS Cantilever Based Binary Logic

Inverter”, in International Conference on Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09, 28-29 Dec. 2009 pp:184 – 188.

[8] Subha Chakraborty, Ashesh Ray Chaudhuri, T. K. Bhattacharyya, “Transient Analysis of MEMS Cantilever based Binary Inverter and Design of a Ring Oscillator”, in 4th International Conference on Computers & Devices for Communication, CODEC’ 09, 14-16 Dec. 2009.

[9] Subha Chakraborty and Tarun Kanti Bhattacharyya, “Development of MEMS based Universal Gate for Signal Processing Circuit in Low Frequency Sensor Applications”, accepted in IEEE Students' Technology Symposium 2010 to be held from 3rd-4th April, 2010 at Indian Institute of Technology, Kharagpur., India.

[10] Subha Chakraborty and Tarun Kanti Bhattacharyya, “Development of Surface-micromachined Binary Logic Gate for Low Frequncy Signal Processing in MEMS based Sensor Applications”, accepted in Microtech 2010 Conference and Expo, to be held from 21st June to 25th June, 2010 at Anaheim, CA, USA.

24


Development of MEMS Based Piezoresistive Accelerometer for Aerospace Application

Francis Oliver Vinay Gomes1, Tarun Kanti Bhattacharyya2 1Advanced Technology Development Center, Indian Institute of Technology, Kharagpur

2Dept of E&ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected], [email protected]

Abstract— A CMOS compatible bulk micromachined piezoresistive accelerometer [1] presented in this paper

consists of four flexures supporting a proof mass. Four pairs of boron-diffused piezoresistors are located at maximum stress points on the flexures near the proof mass and frame ends. Because of the opposite nature of stress at the two ends, these piezoresistors can be connected to form a Wheatstone bridge such that the off-axis responses are practically cancelled while the on-axis (along perpendicular to proof mass) response is maximized. The device is simulated using CoventorWare. In the fabrication process, DRIE will be used for dry etching. The fabrication is thus CMOS compatible. The accelerometer exhibits good linearity over 0–15 g.

Keywords— Silicon Piezoresistive Accelerometer, CMOS, DRIE

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION The Quad-beam Piezoresistive Accelerometer has several major problems in the area of designing and

fabrication, which can be summarized as follows : • Cross-Sensitivity needs to be minimised and Prime axis sensitivity needs to be maximised through proper

optimization • Temperature dependence of Piezoresistors formed using boron doping

Past research work in [2] and [3] attempted to address the problem with partial success. The on-going research activity by the IITKgp MEMS Design Group is currently exploring that the problem may be solved by:

• Proper Optimization and Wheatstone bridge configuration • Using a doping concentration of 3 x 1018 atoms/cm3 for Piezoresistors

II. RECENT RESEARCH ACTIVITIES The work taken up for the Initial Phase by the IITKgp MEMS Design Group involves: • Analytical Foundation • Design of Piezoresistive Accelerometer for Low Cross-Axis Sensitivity • Simulation for Mechanical behaviour (FEM based CoventorWare) • Development of CMOS compatible process Sequence

In FIGURE I, we show the quad- beam structure simulated using a FEM based software called CoventorWare.

The maximum stresses are located at the frame-end and the proof mass–end. The piezoresistors are placed at these locations and connected to form a wheatstone bridge such that off-axis sensitivity is minimised.

25


FIGURE I. Showing the Mises stress formed at the frame-end and the proof mass-end at 13g acceleration

III. SCOPE FOR FUTURE RESEARCH COLLABORATION The parts of the problem yet to be solved requiring further improvement are as follows, on which we shall focus

our research activity next year: • Testing and Characterization • Development of the ASIC

The device which we will fabricate will be tested and characterised for the application of Low Combat Aircraft.

REFERENCES [1] Minhang Bao, Analysis and Design Principles of MEMS Devices, Elsevier, 2005 [2] R Mukhiya and T K Bhattacharyya, Squeeze Film Air Damping Analysis of MEMS Piezoresistive Accelerometer, ICSE 2008 Proc. 2008, Johor Bahru, Malaysia. [3] S. Kal, S. Das, D.K. Maurya, K. Biswas, A. Ravi Sankar, S.K. Lahiri, “A CMOS compatible bulk micromachined silicon piezoresistive

accelerometer with low off-axis sensitivity,” IIT Kharagpur, West Bengal, Microelectronics Journal 37 (2006) 22–30.

26


Design and Implementation of a Single Chip Controller for Buck Derived Double-Ended Transformer Coupled Dual

Phase Converter Rakesh Babu Panguloori#, Prof. Debaprasad Kastha #, Prof. Amit Patra# and Giovanni Capodivacca *

#Dept. of EE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected], 1{kastha, amit}@ee.iitkgp.ernet.in

* Infineon Technologies, Padova [email protected]

Abstract— The duty cycle of the conventional multi-phase buck converter becomes extremely small as the output voltage becomes lower and lower. The operation of multi-phase buck converters with small duty cycle results in lower efficiency, limited controllability and poor ripple current cancellation. This work presents a hybrid power circuit architecture, consisting of an isolated full bridge current doubler rectifier (FBCDR) converter in parallel with an auxiliary buck converter, to improve the efficiency as well as the dynamic performance of the voltage regulator (VR). Even though this solution improves the dynamic response, the dynamic power loss in the auxiliary buck converter becomes an important issue with increasing frequency of the load transient. A control scheme to minimize both the power loss in the auxiliary converter and the effect of the auxiliary converter operation on the main converter control loop response is proposed. The concept has been verified on a 9~19 V input, 1 V/30 A output, 500 kHz system through simulation and experimentation. The results show that the proposed control scheme significantly improves both the dynamic performance and the energy efficiency of the VR

Keywords— Voltage Regulator (VR), Full-Bridge Current Doubler Rectifier (FBCDR); Hysteretic constant turn-off

control; Adaptive Voltage Positioning (AVP)

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Today’s laptop CPU Voltage Regulator uses multiphase (2~4) interleaving synchronous buck topology, which

has major problems such as: • Narrow duty cycle: More switching loss, poor current ripple cancellation and limited controllability. • Limited dynamic performance: Demands more number of passive bulk capacitors, which are not only

expensive but also occupies more valuable space on the motherboard. To extend the duty cycle, the transformer based topologies [1], such as Tapped-inductor buck converter [2],

Active-clamp couple-buck converter [3], Forward converter [4], Push-Pull converter [5], non-isolated Half-Bridge [6] and non-isolated Full-Bridge converters [7] are developed. Some of them needs three level drivers, some has poor magnetic utilization and some need resetting winding/ snubbers. In addition to those, all the transformer based topologies have common drawback of limited dynamic response. Ref [8] uses two stage approach, which needs more no. of power switches at high current levels to keep reasonable efficiency.

This work presents control and power circuit architecture to improve efficiency as well as dynamic performance of the VR. The benefits of the proposed solution are:

• Extends duty cycle to improve the efficiency over conventional multiphase buck converters • Replaces some of the passive filter by an active filter to improve dynamic response, to save cost and space. • Proposed control scheme optimizes the power loss in the auxiliary buck converter thereby improves the

energy efficiency of the VR.

II. RECENT RESEARCH ACTIVITIES The on-going research on voltage regulator modules by the IITKgp Power Management Group started in 2006.

Past Contributions: • Suitable power circuit architecture was chosen to extend the duty cycle • A control scheme was proposed to improve the energy efficiency of the Voltage Regulator • Completed system level simulation using SABER to verify the operation principle of the control circuit

27


Work done in the past one year: • Designed and fabricated a prototype of 9~19 V input, 1 V/30 A output, 500 kHz system on a 8-layer PCB. • Complete experimental verification was performed • Documentation of the research work

60

64

68

72

76

80

84

6 9 12 15 18 21 24 27 30 33

Load current (A)

Effic

ienc

y (%

)

Vin = 12 V

Vin = 19 V

FIGURE I. Prototype of the proposed solution FIGURE II. Complete test setup FIGURE III. Power efficiency@500kHz

Vo

24 A

190 mV

25 µs

istep

Vo

24 A

78 mV

36 µs

istep

40

45

50

55

60

65

70

75

80

85

0.01 0.1 1 5 10 50

FLT (kHz) E

nerg

y Ef

f (%

)

FBCDR

FBCDR + Buck

Two-phase Buck

Proposed solution

FIGURE IV. Load transient response FIGURE V. Load transient response FIGURE VI. Energy efficiency vs. with FBCDR converter with the proposed solution load transient frequency FIGURE I and FIGURE II show the photographs of the developed power circuit prototype and the complete test

setup. The measured efficiency curves for the FBCDR converter are shown in FIGURE III. Maximum efficiency of 81.4% with 12V input voltage and 80.08% with 19V input voltage are achieved experimentally at a switching frequency of 500 kHz. The load transient response with the FBCDR converter and with the proposed solution are shown in FIGURE IV and FIGURE V respectively. The proposed solution also offers significantly improved energy efficiency up to 10 kHz load current transient frequency when compared with a similarly rated two-phase buck converter as depicted in FIGURE VI.


following conference-paper, journal-publication and invention disclosure. • RakeshBabu Panguloori, Debaprasad Kastha and Amit Patra, “A Control Scheme to Minimize the Dynamic

Power Loss in an Unbalanced Voltage Regulator Module and its Method of Operation”, is filed as Indian patent with filing number 1003/KOL/2009.

• RakeshBabu Panguloori, D. Kastha, Amit Patra and G. Capodivacca, “High Voltage Regulator for High Step-Down DC-DC Conversion”, IEEE Industrial Electronics Conference, IECON-2008, Florida, USA, pp. 761-765.

• RakeshBabu Panguloori, Debaprasad Kastha and Amit Patra, “Inductor Coupling Scheme to Enhance the Dynamic Performance of Half-Bridge DC-DC Converter”, IEEE Region 10 Conference, TENCON-2008, Hyderabad, INDIA, Nov-2008, pp. 1-6.

• RakeshBabu Panguloori, D. Kastha and Amit Patra, “Control Scheme to Improve the Dynamic Performance and Energy Efficiency of a Hybrid Voltage Regulator”, communicated to Journal of IET Power Electronics.

28


IV. SCOPE FOR FUTURE RESEARCH COLLABORATION The performance of the proposed solution can further be improved with the following implementations: • The current references in the auxiliary buck converter are chosen judiciously to meet the worst load transient

case. However, the current references can be made adaptive to the output voltage deviation so that the dynamic power loss in the auxiliary buck converter can be reduced even further.

• The present work used discrete components to implement the control scheme, an integrated IC solution of the complete control circuit can offer better transient response due to reduced controller action delays.

• Integration of all the magnetic components improves the performance of the power circuit.

REFERENCES [1] J.Wei, K.Yao, M.Xu, and F.C. Lee, “Applying Transformer Concept to Non-Isolated Voltage Regulators Significantly Improves the

Efficiently and Transient Response,” in Proc. IEEE Trans. on Power Electronics Specialties Conf. (PESC), 2003, pp. 1599-1604. [2] Kaiwei Yao, Mao Ye, Ming Xu and Fred C. Lee, “Tapped-Inductor Buck Converter for High Step-Down DC-DC Conversion,” in Proc.

IEEE Trans. on Power Electronics, Vol. 20, July 2005, pp.775-780. [3] P.Xu, J. Wei and F. C . Lee, “The active-clamp couple-buck converter-A novel high efficiency voltage regulator modules,” APEC’01. [4] J. Guo, “High performance forward converter in non-isolated configurations,” IEEE, INTELEC’03. [5] P.Xu, J. Wei and F. C . Lee, “A high efficiency topology for 12V VRM-push-pull buck and its integrated magnetics implementation,”. [6] Zhihua Yang, Sheng Ye, Yanfei Liu, “A Novel Non-Isolated Half Bridge DC-DC Converter,” IEEE 2005, pp. 301-307. [7] J.Wei, F.C. Lee, “Two Novel Soft Switched, High Frequency, High Efficiency, Non-Isolated Voltage Regulators- The Phase Shift Buck

Converter and the Matrix-Transformer Phase-Buck Converter,” in Proc. IEEE Trans. on Power Electronics,Vol.20, No. 2, march 2005. [8] Jia wei, Fred C. Lee, “Two-Stage Voltage Regulator for Laptop Computer CPUs and the Corresponding Advanced Control Schemes to

Improve Light-Load Performance,” in Proc. IEEE 2004, pp. 1294-1300.

29


Low Voltage Embedded DC-DC Converter Kaushik Bhattacharyya and Prof. Pradip Mandal

Dept. of E&ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

{Kaushik, pradip}@ece.iitkgp.ernet.in

Abstract— Switch capacitor-Linear regulator based Hybrid dc-dc converter is an emerging topology for high

dropout application. In an embedded hybrid DC-DC converter, the charging capacitors and the load capacitor are small. Because of this, its output ripple is alarmingly high. Here we have used two new techniques for output voltage ripple reduction of an embedded switching capacitor –linear regulator based hybrid DC-DC converter. The first one is to improve the power supply rejection ratio (PSRR) of the linear regulator and there by attenuates the ripple originated from the switching capacitor circuit module. The output ripple is further reduced by introducing a synthesized counter ripple through the linear regulator. The proposed converter circuit was designed in 0.18μ process for 3.3V to 1.35V conversion. With two switching capacitors of 150pF each, for more than 12mA of load current and 80pF load capacitor. A test chip of above mentioned embedded converter is fabricated with a standard 0.18-μm digital CMOS n-well process to demonstrate the efficacy of the proposed techniques. It is found that the measured results are consistent with the simulation results. The measured peak power efficiency of the proposed converter is 11% more than the existing converter.

Keywords— Charge Recycling, Embedded Hybrid DC-DC converter, High Dropout Regulation, , Low Voltage Ripple,

PSRR of Linear Regulator, Ripple Synthesizer

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION

In recent years, low Voltage, DC-DC converters are achieving a remarkable attention because the most effective way to reduce the power of the active circuits is by operating at a lower power supply voltage, (Vdd). There is a constant endeavor to build up a highly efficient-converter with small size and weight for a long time. Buck converter which uses an inductor to step down the supply voltage, is the first choice to make a highly efficient converter. However, the main disadvantage of a buck converter is that it requires a bulky inductor. In addition, it introduces high ripple at the output voltage. For this reason its application for analog and mixed signal is limited. On the other hand, linear regulator is compact and its output voltage is free from ripple. A fast dynamic response is also provided by this regulator. These features make linear regulator suitable for analog and embedded application. However its power efficiency reduces linearly with the increase of input and output voltage difference. This becomes major concern for battery operated system, where battery voltage remains same while the required internal voltage reduces with progress of technology. Inductor-less switch-capacitor converter topologies are very much attractive to improve the efficiency. It posses the advantages of reduced size and weight. A considerable amount of switching ripple restricts its analog application while the ripple can be reduced by using large capacitor(s) (may be of the order of nano-or micro Farad) [1], [2] but at that time it is difficult to use it as an embedded regulator. There is a recent trend of combining a switching regulator (inductor based or capacitor based) with a linear regulator to achieve good power efficiency with low output ripple. For instance, combining a switch-capacitor converter and a linear regulator [1] gives a high dropout converter with good power efficiency. In these hybrid converters the output ripple is kept low by using external capacitor [1]. There is an attempt in this research project to offer a hybrid converter topology which can be implemented on-chip (without external capacitor) with good power efficiency still maintaining its output ripple within acceptable level. In the proposed topology, along with a linear regulator a switch able capacitor is used to recycle charge for improving power efficiency [3]. On the other hand the linear regulator helps to reduce the output ripple that is introduced by the switching circuit. Ripple reduction which is provided by the linear regulator is analyzed and optimized [4]. Here we propose Dual-Switch capacitor Circuits instead of using the fixed charge storing capacitor [5]. The second equal size flying capacitor is switching in opposite phase of that of the first one. This type of switching-capacitor configuration helps to reduce peak-peak ripple at the output of the Switching Circuit module.

30


The output ripple is further automatically reduced by introducing a synthesized ripple in opposite phase through the linear regulator. A detailed analysis and the necessary condition to minimize the output ripple are carried out. Finally, two switching circuits with appropriate phase difference are combined and fed to the linear regulator to provide a steady supply current to the linear regulator [6].

Fig.1 Block Diagram of the Hybrid DC-DC Converter

II. RECENT RESEARCH ACTIVITIES A transistor level implementation of the proposed embedded DC-DC converter including the proposed ripple reduction techniques has been simulated for 3.3V to 1.35V conversion with in the range of 1.5 mA to 12.8 mA load current. It is found that the ripple reduction factors from the two techniques are 0.50 and 0.34 respectively. A test chip is fabricated with a standard 0.18-μm with a standard digital CMOS n-well process to demonstrate the efficacy of the proposed techniques. It is found that the measured results are consistent with the proposed theory. The sample measured waveforms are given in Fig.2 and Fig. 3. It is transparent from Fig. 2 that the peak to peak ripple at the hybrid converter output is attenuated with the proposed techniques. Much more attenuated form of ripple can be obtained if there would be scope for internal probing (because it is an embedded DC-DC converter).

Fig.2 Measured output Voltage of the Embedded DC-DC converter [top] , Switching Circuit module [middle], and

the Ripple Synthesizer [bottom]

31


Fig.3 Measured clock output of the internal clock generator required for Switching Circuit module

III. RESEARCH ACCOMPLISHMENTS A part of the above research work has already been disseminated to the engineering community in the form of following conference-papers. Some papers are under review process.

• Kaushik Bhattacharyya and Pradip Mandal, “A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor

Based Hybrid DC-DC Converter”, IEEE 21st International Conference On VLSI Design (VLSI Design 2008), Hyderabad, India, January 2008 pp. 661-666

• Pradip Mandal and Kaushik Bhattacharyya, “A Low voltage, Low ripple on Chip Hybrid DC-DC

Converter”, IEEE International Symposium on Integrated Circuits 2007(ISIC-2007), Singapore, 26-28 September 2007, pp. 442-445

REFERENCES [1] George Patounakis, Yee William Li, and Kenneth L. Shepard, “A Fully integrated On-Chip DC-DC Conversion and Power Management System”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 3, March 2004, pp. 443-451 [2] Yogesh K. Ramadass and Anantha P. Chandrakasan, “Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low Power On- Chip Applications”, IEEE 2007 Power Electronics Specialists Conference, 17-21 June 2007, pp. 2353-2359 [3] Pradip Mandal and Kaushik Bhattacharyya, “A Low voltage, Low ripple on Chip Hybrid DC-DC Converter”, International Symposium on Integrated Circuits 2007(ISIC-2007), Singapore, 26-28 September 2007, pp. 442-445 [4] Vishal Gupta and Gabriel A. Rincon Mora, “A Low Dropout, CMOS Regulator with High PSR over Wideband Frequencies”, IEEE International Symposium on Circuit and Systems, Vol.5, May 2005, pp. 4245-4248 [5] J.G. Ryan, K. J. Carroll, and B.D. Pless, “A four chip implantable defibrillator/pacemaker chipset”, in proc. Custom Integrated Circuits Conference, 1989, pp. 7.6/1-7.6/4 [6] Kaushik Bhattacharyya and Pradip Mandal, “A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter”, 21st International Conference On VLSI Design (VLSI Design 2008), Hyderabad, India, January 2008, pp. 661-666

32


On-Chip Inductor-less DC-DC Boost Converter Using NORI Scheme

Prof. Pradip Mandal# and Tamal Das* #Dept. of E&ECE, Indian Institute of Technology, Kharagpur


*Senior Project Assistant Advanced VLSI Design Lab, IIT Kharagpur

[email protected]

Abstract— An architecture of inductor-less DC-DC boost converter for high efficiency and low output ripple is

proposed. Output ripple is reduced by splitting flying capacitors into a number of smaller elements and using a new switching scheme called Non-Overlapped Rotational-Interleaving (NORI). The proposed switching scheme also helps to eliminate reversion and shoot through current hence improves the power efficiency. The proposed converter is designed in 0.18µM CMOS thick gate process having 440pF total flying capacitance. The target specification of load current is 1mA-23mA for 5V-6.5V output voltage from an input supply of 3.3V . The achieved peak power efficiency is 89% at 10mA load current as compare to 83% peak power efficiency obtained from the best existing architecture designed in same technology. The output ripple at 20mA load current is 5mV in presence of only 50pF load capacitance.

Keywords— shoot through current, non-overlapped rotational interleaving.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION On-chip inductor-less DC-DC boost converters is nothing but cross-coupled charge-pump i.e. switched-capacitor

voltage doubler. The load current it can supply is proportional to flying capacitance, supply voltage and switching frequency. For on-chip solution one has to increase the switching frequency, but there are some critical problems which not only decrease overall power efficiency also increase the output ripple as well as power line switching noise. The worst thing is their solutions always create a close trade-off.

• Shoot through current: simultaneous transition • Non-overlapped clock:

o Solution to shoot through loss o Increases the output ripple dip

• Interleaving: o Increases the ripple frequency: decreases the size of output capacitance o Shoot through current decreases the overall efficiency

In recent literatures ( [1] & [2])there are different off-chip as well as on-chip solution but none of them is able to break the trade-off. In [3] partially the trade-off is broken but not applicable for on-chip solutions. We in this project introduces a clocking scheme called non-overlapped rotational interleaving scheme through which one can rule out the trade-off for any type of SC DC-DC converter. The benefits of the scheme are:

• Non-overlapped clock: erases the shoot through loss • Interleaving clock: increase the ripple frequency • Non-overlap rotational-interleaving: decreases the in-rush peaks, increases switching noise frequency as

well. The novelty of the whole architecture (Cross-coupled charge-pump using NORI scheme) are as follows:

• Due to this scheme one can distribute a pair of big flying capacitance and switches through out the chip • No trade off among shoot-through current, in-rush current, output ripple dip as well as its frequency


33


We designed the proposed converter to supply 5.5V regulated output with load driving capability of 1mA-23mA in 0.18µCMOS n-well process. The post-layout simulation results are shown in TABLE I. FIGURE I shows the efficiency variation of the converter with proposed scheme.

FIGURE I: Efficiency Variation with Load at Fs=25 & 50 MHz

TABLE I: Performance of Proposed DC-DC Converter Performance Parameter Simulated

Supply Voltage 3.3V±10% Output Voltage 5-6.55V Unregulated

5.5V Regulated output Total Capacitance Flying Capacitance: 440pF

Output Capacitance: 50pF Load Current 0-30mA with unregulated output

Output Ripple <10mV Load Regulation ±5mV/ mA Power Efficiency Peak efficiency 80% (17mA)(Unreg.)

Switching Frequency 45-80MHz


following conference-paper, journal-publication and invention disclosure. • Tamal Das, Pradip Mandal, “On-Chip Inductor-less DC-DC Boost Converter with Non-Overlapped

Rotational-Interleaving Scheme” International Conference on VLSI Design, IEEE, 2010.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION In the above designed to generate the NORI clock-phase we have used DLL. It can be replaced by ring-oscillator

type VCO. The switching frequency can be changed dynamically according to load variation to extract approximately flat efficiency with respect to load.

REFERENCES [1] H. Lee and M. P.K.T, “Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler,” Solid-

State Circuits, IEEE Journal, vol. 40, pp. 1136– 1146, May 2005. [2] F. L. D. Ma, “Robust multiple-phase switched-capacitor dc-dc power converter with digital interleaving regulation scheme,” Very Large Scale Integration (VLSI) Systems, IEEE Journal of, vol. 16, June 2008. [3] C. Y. T. Feng Su, W. H. Ki, “Regulated switched capacitor doubler with interleaving control for continuous output regulation,” JSSC, IEEE, vol. 44, April 2009.

34


Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple




[email protected]

Abstract— In this note we are addressing power efficiency and output ripple of an embedded switched-capacitor

based DC/DC Buck Converters. Here we propose to use current pump based switched-capacitor circuit in buck converter. The current pump circuit limits transition current of the switched-capacitors and hence, improves power efficiency and reduces output ripple. A transistor level implementation of the proposed buck converter in 0.18µm technology is provided. For a load current of 8mA (maximum) the achieved power efficiency is 72.7% and the output ripple is 27mV. The flying capacitors in the converter are 2x108pF and the load capacitor is 125pF.

Keywords—Switched-Capacitor Converter, DC-DC Buck Converter, Current Regulation, Current Limiter, Load

Regulation.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION DC-DC buck converter using switched-capacitor circuits is a recent trend for high dropout regulation [1]. Power

efficiency and output ripple of this converter, however, are the concern specifically for embedded applications where sizes of its flying capacitors and load capacitor are limited by chip area. Cascading switched-capacitor with a linear regulator is an approach for the ripple reduction. As all other SC converters the basic problem with this is:

• Shoot through current during switching transitions which directly affects the i. Output ripple

ii. Power efficiency For cross-coupled charge-pump this shoot through current problem during pumping is addressed in [2] and is

reduced and not only that this current limiter is controlled through a closed loop to obtain good load regulation. This same current limiter can also be used for SC step down converters but during the charge sharing time this limiter is to be switched off. We have proposed a fully differential SC step down converter with current limiter which will provide VDD/2 in open loop. The main novelty with this topology are:

• Output ripple is much less than any present topology with such small flying capacitance • Power efficiency is also comparable with existing topology

The proposed topology has following inventiveness (FIGURE 1a): • Current limiter at both end (charge refreshing state and charge sharing state) • Current limiter from the ground. • One can have any output voltage level (within a specified limit) just changing the reference voltage.

II. RECENT RESEARCH ACTIVITIES We have designed the proposed topology (Figure 1b) in CMOS9 process for 3.3V supply with 1.35V output and

8mA load current. The output ripple at maximum load is 27mV with more than 72% efficiency. In FIGURE 2 the dynamic performance is shown where it is seen that the system has two dominant poles. The

settling time depends on phase margin of the system which is totally given by the output pole of the error-amplifier.

35


FIGURE 1. (a)Proposed Topology; (b) Dynamic Performance (3mA-8mA step)

FIGURE 2 shows output ripple variation with load. TABLE I shows the performance improvement over hard-switched SC buck converter:

TABLE I: A sample graph showing the result / architecture / flow-chart / etc

Load Current (mA) Power Efficiency (%) Output Ripple (mV) Hard Switching With Current Limit Hard Switching With Current Limit

8 64 72.7 100 27


following conference-paper. • Das, T.; Mandal, P., “Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better

Efficiency and Output Ripple”, VLSI Design, 2009 22nd International Conference on 5-9 Jan. 2009 Page(s):181 - 186

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION There are some unaddressed problems with this topology: • As we have designed this with N-well CMOS process the during switching the diode current of lower NMOS

(current limiter) will directly affect the output at higher current level. • Interleaving with non-overlap clock may improve the performance at a better level.

Now we are working with this problems and have solved almost with far better performance.

REFERENCES [1] P. Mandal, K. Bhattacharya, “A Low Voltage, Low Ripple On Chip Hybrid DC-DC Converter,” International Symposium on Integrated

Circuits,2007. [2] Soon-Kyun Shin et.al, ”A High Current Driving Charge Pump with Current Regulation Method” IEEE Custom Integrated Circuits

Conference(CICC), 2005.

Vdd

−

+

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36


High Efficiency Charge-Pump for Efficient DC-DC Step Up Conversion for Thick Gate CMOS Process




[email protected] Abstract— The charge-pump voltage doublers for DC-DC converters are not new, depending upon different

applications different versions of topology have come in the world of charge pumps. For some applications only high output voltage level is necessary (FLASH Memory, EEPROM etc.), for some other applications high load driving capability is more important (LCD drivers, LED drivers, USB OTG etc), again in some cases though the driving capability is not concern but a high output voltage level is required from a very low supply voltage (Bias supply for MEMS Resonators). For high capacitive load charge-pump-pass switches need to have better conduction efficiency. We have proposed a high efficiency charge-pump based voltage doubler for thick gate CMOS process where the conduction efficiency of the pass switches is increased by driving their gate by 0-2Vdd swing.

Keywords—DC-DC converter, Switched-Capacitor Converter, Charge-Pump, Conduction efficiency, Conversion Ratio

( efficiency).

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION All the voltage multipliers operate in a manner similar to a Bucket-Brigade delay line, by pumping packets of

charge along the diode chain as the coupling capacitors are successively charged and discharged during each half clock cycle. In [1] an experimental DRAM design the cross-coupled charge-pump is firstly introduced as a static word-line driver.

Though it is very attractive topology for efficient embedded application due to its current efficiency several problems may arise for this cross-coupled charge-pump voltage doubler for low voltage and high frequency operation.

• Conduction efficiency of the series switches limit the output load capacitance. • For voltage doublers are used in cascade (Voltage multiplier) whole converter’s speed is limited by the

Conduction efficiency of the series switches • Gate-Oxide Break Down Voltage

Past research work in [2], [3] and [4] attempted to address the problem with partial success. But using the advancement of the semiconductor technology we have addressed these problems with following novelty and inventiveness.

• Novelty i. High conduction efficiency of the pass switches

ii. Low settling time 70% reduction in rise time from power off mode

iii. Better conversion efficiency (ideally it is 2 ) It can operate for lower supply voltage retaining acceptable conversion efficiency

iv. Better power efficiency Shoot through current is reduced

Switching loss can also be reduced v. Smaller area

Lower component count with respect to available architecture

• Inventiveness: i. Internally generating 0-2VDD swing as a control signal for pass switches (to get higher

conduction efficiency) ii. Gate of the pass switches will be driven by 0-2VDD swing but for drain

37


we may have VDD-2VDD swing or, 0-2VDD swing combination of both


FIGURE I. Variation of conversion efficiency and settling time with respect to supply voltage

By using thick-gate CMOS process we have designed our proposed topology and Figure1 is showing its

performance for 0.18μ CMOS thick gate process with Cf=120pF. We have also achieved different advantages with respect to previously proposed remedies [2]-[4].


following invention disclosure. • Patent #2 (optional) [2]

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION There are some more aspects which need to be addressed such as: • Performance of this charge-pump in cascading mode to obtain voltage multiplier • Attach some control loop to obtain better load/line regulation

REFERENCES [1] Y. Nakagome ET. Al, “An Experimental 1.5-V 64-Mb DRAM” by Nakagome et al., IEEE Journal of Solid State Circuits, Vol. 26, No. 4,

April [2] S P. Favrat, P. Deval, M.J. Declercq, “ A High Efficiency Voltage Doubler”; IEEE Journal of Solid State Circuit, Vol. 33, No. 3, 1998. [3] US6198340, High Efficiency CMOS Pump Circuit, Ting et al [4] US6975161, Charge Pump and Voltage Doubler Using the Same, Yen

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100

200

300

400

500

600

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38


Macro Modelling of Switched-Capacitor Type DC-DC Converter




[email protected]

Abstract— We have proposed an equivalent macro model for some switched-capacitor type of current pump based

step-up or step-down converters in closed loop which would help to get a better essence of the closed loop stability of the system and would reveal clearly trade-offs among load current, flying capacitance and clock frequency.

Keywords—Switched-Capacitor DC-DC converter, Charge-Pump, Buck Converter, Current Regulation, Macro Model

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION The switched-capacitor dc-dc converters of the type [1], [2] are though purely analog design problem but it is

non-linear circuit the stability analysis is not straight forward. As all other switched-capacitor circuits the capacitors can not be replaced by 1/Cf (f, switching frequency).

This type of problem of stability analysis is addressed in many previous work using state-space averaged and sampled-data modelling but equivalent resistance for switched capacitance is not addressed yet. We have proposed a macro modelling technique which not only solves the stability analysis problem but the voltage dependency on the equivalent resistance.

The proposed methodology is first to show that • Voltage dependency on equivalent resistance of switched-capacitor

II. RECENT RESEARCH ACTIVITIES The main logic behind this methodology is to analyse some specific node voltage waveform and from that

information one can easily calculate the equivalent resistance of the switched-capacitor. For this macro-model we have replace the actual topology with resistance and dc voltage source whose values are straight forward from the node voltage analysis. As all this switched capacitor converters are fully differential the macro models are strong enough to represent the actual topology.

In FIGURE I we are showing our approach for the topology proposed in [2]. The equivalent resistance evaluated from the methodology is given by:

The mismatch of the current limiter is also captured through this methodology and modelled to another equivalent

resistance:

The proposed methodology can also be used to calculate optimum flying capacitance for a given specification.

The TABLE I shows the strength of the methodology applied for the [2]. After obtaining this macro model one can easily do the small signal analysis to observe its stability.

121 14

ds

p L

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( )0 1d s d s

L

V VR

I−

′ =

39


FIGURE I. (a) Waveform at specific node voltages; (b) Macro Model

TABLE I: Strength of Macro Model

Maximum Load Current (mA) Cp (F) Output Voltage (V) Macro Model Actual Model Macro Model Actual Model Macro Model Actual Model

4.00 4.00 50p 53p 1.35 1.35 6.00 5.99 75p 78p 1.35 1.3499 8.00 7.99 100p 108p 1.35 1.34999


following conference-paper. • Das, T.; Mandal, P., “Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better

Efficiency and Output Ripple”, VLSI Design, 2009 22nd International Conference on 5-9 Jan. 2009 Page(s):181 - 186

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION The methodology which we demonstrated successfully for current regulation or current limiter, it can be extended

for other control techniques also which specifically having differential mode. We are trying the same thing for adjustable resistive control of cross-coupled charge-pump.

REFERENCES [1] Soon-Kyun Shin et.al, ”A High Current Driving Charge Pump with Current Regulation Method” IEEE Custom Integrated Circuits

Conference(CICC), 2005. [2] Das, T.; Mandal, P., “Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple”,

VLSI Design, 2009 22nd International Conference on 5-9 Jan. 2009 Page(s):181 - 186

(VA)avg

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40


Digital PWM Control of Switchers: Architectures for Low-Power High-Resolution Operation

Syed Asif Eqbal* , Prof. Amit Patra# *Advanced Tech. Development Centre, #Dept. of Electrical Engineering, Indian Institute of Technology, Kharagpur


Abstract— This work proposes three new architectures of digital pulse width modulator (DPWM) for silicon-

based, low-power, high-resolution dc-dc converters. The proposed solutions have been evaluated in terms of linearity, power and the ease of digital implementation. The case has been presented for only single-phase buck converter, but the concept can be extended to multi-phase systems or to other converter topologies as well.

Keywords— Dc-dc converter, digital PWM, digital control, limit cycle

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION In digitally controlled dc-dc converters, for the precise regulation of the output voltage and in order to avoid

quantization related problems, DPWM with high degrees of resolution is necessary. Low power consumption and high linearity are two associated requirements. The state of the art [1] still leaves much to be developed as the current solutions either meet the requirement in a partial way or do it through analog-heavy designs. Past attempts [2] and [3] respectively suffer from variable switching frequency and analog heavy design. [4] uses sigma-delta modulation technique which is an external method to add resolution to a given DPWM, but this method doesn’t improve the core DPWM resolution. The present work proposes following three new architectural approaches to improve DPWM resolution:

• Hysteretic-overlap architecture • Redundancy based architecture • Dynamic element matching (DEM) approach

II. RECENT RESEARCH ACTIVITIES The on-going research by Power Management Group (AVDL, IITKGP) started in Sept. 2008. In the past we have

demonstrated the following: • Vernier based DPWM architecture on an FPGA board • Limitations of Vernier based and Multiplier based architectures

Within the past six months, we developed the aforementioned three new approaches. Of these, the hysteretic-

overlap architecture is a novel concept, whereas idea of redundancy based architecture and DEM approaches have been borrowed from data converter domains.

The benefits of the proposed approaches can be summarized as: • Pure digital implementation is possible. • Low power under dynamic condition • No power consumption while not switching • Fixed frequency operation

In FIGURE 1, we show the delay selection algorithm for the hysteretic-overlap architecture.

41


FIGURE I. Delay selection algorithm in hysteretic-overlap architecture

In TABLE I, we summarize the comparative results between the existing approaches and the methodology developed by Power Management Group (AVDL, IITKGP).

TABLE I: Comparison of existing and proposed architectures

DNL Power Digital Implementation Fixed Freq.

[2] Low Low Yes No [3] Low Moderate No Yes Hysteretic -overlap architecture Low Low Yes Yes Redundancy based architecture Moderate Low Yes Yes DEM architecture Low Low Yes Yes

III. RESEARCH ACCOMPLISHMENTS A part of the research output has been shared with our collaborative research partner Infineon Technologies

during our first year of research.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION As for future work, the three new architectures have to be fully developed and verified using ASIC/FPGA.

REFERENCES [1] Syed A., Ahmed E., Maksimović D., and Alarcón E., “Digital Pulse Width Modulator Architectures,” Power Electronics Specialists

Conference, PESC ‘04, pp. 4689-4695, 2004. [2] Li J., Lee F. C., and Qiu Y., “New Digital Control Architecture Eliminating the Need for High Resolution DPWM”, Power Electronics

Specialists Conference, PESC ’07, pp. 814-819, 2007. [3] Trescases O., Wei G., and Ng W. T., “A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS,” IEEE

Conference on Electron Devices and Solid-State Circuits, pp. 367-370, 2005. [4] Lukić Z., Rahman N., and Prodić A., “Multibit Σ-Δ PWM Digital Controller IC for DC–DC Converters Operating at Switching

Frequencies Beyond 10 MHz,” IEEE Transactions on Power Electronics, Vol. 22, No. 5, Sept. 2007. [5] Saggini S., Mattavelli P., Ghioni M. and Redaelli M., “Mixed-Signal Voltage-Mode Control for DC-DC Converters with Inherent Analog

Derivative Action,” IEEE Transactions on Power Electronics, Vol. 23, No. 3, pp. 1485-1493, May 2008.

42


Design and On-Chip Implementation of a Single-Inductor Triple-Output DC-DC Buck Converter

Pradipta Patra*, Prof. Amit Patra# * ATDC, #Dept. of EE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India {[email protected], [email protected]}

Abstract— the work comes up a priority based control scheme for single-inductor multiple-output dc-dc switching converter generating buck outputs from a single supply. The control scheme ensures system stability even during transient operation and minimized cross regulation amongst the outputs. Keywords— DC–DC converter, multiple output, single inductor, single inductor–multiple output (SIMO), switching supply, cross regulation

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Conventional implementation of dc-dc converters in Power Management Units of various low power applications having N output voltages may consist of N independent converters or employ a transformer that has N secondary windings to distribute the energy into the various outputs. On the contrary, Single-Inductor Multiple-Output (SIMO) topology for dc-dc converter brings down the number of components viz., switches and inductors. With the reduction in components the power losses and electromagnetic coupling amongst the magnetic components is also eliminated. However, implementation of these types of converters comes with the coupling effects amongst the outputs which might lead to destabilization of the system primarily during load transients. Recent work shows that these are operated in discontinuous conduction mode (DCM) to avoid the cross regulation amongst the outputs. However, this fails for high loads as the peaks of inductor current increases a lot.

II. RECENT RESEARCH ACTIVITIES This work comes up with a control strategy which focuses on the cross regulation, amongst the coupled outputs and enables a continuous conduction mode (CCM) operation. The converter has been modeled, the cross regulation factors evaluated and finally a priority based voltage-mode control scheme designed to control these converters successfully. Finally, a Single-Inductor Triple-Output Buck Converter has been designed and implemented in 1.5µ BiCMOS process of National Semiconductor. The chip has been fabricated and has been tested and functionally verified. Lastly, to overcome the limitations of a voltage mode control scheme, current mode priority based control scheme has been incorporated though in system level simulation only. Unlike current mode control for single output switcher system instability occurs for even lower duty cycles and a compensating ramp is needed early on. However, with a compensating ramp the performance is supposed to better over the voltage mode scheme.

43


Applications:

Any system working from a single supply and requiring multiple step-down voltage levels is a potential application

area. Examples include:

1. Portable applications (modems, cell phones, PDA’s etc.) 2. Automotive Systems

Novelty and Advantages:

1. Independent Control of each one of the outputs. 2. Single inductor switcher implementation. 3. Minimum number of external capacitors. 4. Reduced number of on-chip power switches.

Challenges and Limitations: 1. Reduction of cross regulation amongst the outputs and maintaining system stability throughout the

operating zone. 2. Realizing accurate dead time amongst the switches so as to maintain the power switches within operating

condition. 3. Efficiency of the system can be sacrificed based on the dead time adjustment of the switches or if the

inductor is freewheeled.

Features:

1. Magnetic coupling is eliminated 2. Component count (especially power switches) & cost is reduced. 3. Independently closed loop control 4. Priority Based Control Scheme to reduce cross regulation. 5. Voltage control scheme is stable but the system dynamics are slow due to the same ramp for the three EA’s 6. With current control scheme system stability loses for duty cycles less than 0.25

44


Publications:

1. Pradipta Patra, Susovon Samanta, Souvik Chattopadhyay, Amit Patra and D. Kastha. "A Novel Control Technique for Single-Inductor Multiple-Output DC-DC Buck Converters". Accepted in International Conference on Industrial Technology, Mumbai, Dec, 2006.

2. Pradipta Patra, Amit Patra and D. Kastha. "On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter Topology ". Accepted in International Conference on VLSI Design, Bangalore, Jan, 2007.

45


Design and Implementation of a Single-Inductor Multiple-Output Switcher with Boost and Buck/Boost/Inverted

Outputs Pradipta Patra*, Prof. Amit Patra#

* ATDC, #Dept. of EE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

{[email protected], [email protected]} Abstract— This work proposes a single-inductor multiple-output switcher that can generate bipolar step-up and

step-down outputs from a single supply with one of the outputs being a boost. Each of these outputs is independently controlled. The cross regulation amongst the outputs can be minimized by a optimally designed control scheme. Keywords— Single-Inductor Multiple-Output switcher, buck boost output, cross regulation

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Regulated DC power supplies are an important requirement in present day battery driven electronic

applications. The same battery is required to serve numerous applications, each requiring a different input voltage. Applications might require step-down, step-up or at times even a bipolar supply (flat panel LED displays). Bipolar supply also finds a wide range of application in OLED’s (Organic Light Emitting Diode). Conventionally, a Power Management Unit (PMU) is designed which comprises of may be step-up, step-down, buck-boost (to generate negative supply) and/or linear regulators to meet the different supplies for the various circuits in any electronic device (PDA, Cell Phones and Laptop etc). Using a Single-Inductor Multiple-Output topology can be an effective solution if it can generate bipolar buck and boost outputs.

II. RECENT RESEARCH ACTIVITIES The proposed scheme is a single inductor multiple output switcher working from a single supply. One of

the outputs is always a positive boost, and the rest of the outputs can be anything from among the positive buck, the positive boost, the negative buck and the negative boost. All of these outputs can be independently controlled. Operating points corresponding to various duty cycles of a two output switcher have been shown in the adjacent figures for two different modes of operation.

46


Applications: Any system working from a single supply and requiring multiple bipolar step-up/step-down voltage levels is a potential application area. Examples include:

1. OLED 2. Automotive Systems 3. Portable Devices 4. Wireless Sensors

Novelty and Advantages:

1. Generates simultaneous boost and buck/boost/inverted outputs 2. Wide ranges of buck, boost, and inverted operation 3. Independent Control of each one of the outputs 4. Single inductor switcher implementation 5. Minimum number of external capacitors 6. Reduced number of on-chip power switches

Challenges and Limitations:

1. One of the outputs has to be a positive boost 2. Output current capacity is relatively low for negative outputs 3. Efficiency is relatively low for negative output operation 4. Cross regulation amongst the outputs

Objectives of the Work:

1. Mathematical Model of the Executable Steady-state Operating Region 2. Detailed Analysis and Modeling of the Switcher 3. Advanced control schemes and Compensator Design to improve the steady-state and transient cross-

coupling between different outputs. 4. Efficiency Characterization and Modeling

REFERENCES [1] Chang-Seok Chae, Hanh-Phuc Le, Kwang-Chan lee, Gyu-Ha Cho and Gyu-Hyeong Cho, “A Single-Inductor Step-Up DC-DC Switching

Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels”, Solid-State Circuits, IEEE Journal of , VOL. 44, No. 2,

February 2009

[2] Hanh-Phuc Le, Chang-Seok Chae, Kwang-Chan Lee, Gyu-Hyeong Cho, Se-Won Wang, Gyu-Ha Cho and Sung-il Kim, “A Single-Inductor

Switching DC–DC Converter With Five Outputs and Ordered Power-Distributive Control ”, Solid-State Circuits, IEEE Journal of , Vol. 42, No.

12, December 2007

[3] Suet-Chui Koon, Yat-Hei Lam and Wing-Hung Ki, “Integrated Charge-Control Single-Inductor Dual-Output Step-Up/Step-Down Converter”,

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, Vol. 4, May 2005 pp: 3071- 3074

[4] Ming-Hsin Huang and Ke-Horng Chen, “Single-inductor dual-output (SIDO) DC–DC converters for minimized cross regulation and high

efficiency in soc supplying systems ”, Springer Science + Business Media, LLC 2008, July, 2008

47


Design and Implementation of a Solar Photovoltaic Simulator

Avneet Singh, Ashish Ranjan Hota, Prof Amit Patra †Dept. of EE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India {[email protected], [email protected], [email protected]}

Abstract— A solar panel is a device that converts light into electricity. Manufacturers of solar electric equipment need solar panels for testing their product like maximum power trackers for power quality, protection, safety issues, etc. It is important, therefore, to devise experimental facilities and procedures which are more compact, cost-effective, and flexible than actual array configurations for testing purposes. Moreover, environmental conditions, such as solar radiation and temperature, affect strongly the performance of PV systems and testing in a natural environment presents difficulties in achieving a full range of these environmental parameters. This work presents a programmable solar photovoltaic simulator which can eliminate the need for using actual solar panels for testing and development of solar electric equipment. Keywords— Solar panel, simulator, microcontroller, loop compensation.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION To be able to harness the solar photovoltaic power in an efficient manner calls for extensive research and development of power conditioning elements that can make it available in a usable form. To test the power processing units developed requires the use of photovoltaic modules. Also, solar photovoltaic panels are large and heavy to handle. These panels must be exposed to sunlight and the behavior of these panels depends heavily on the sunshine availability and climatic conditions like temperature and wind. This makes the testing process very slow and inefficient. Moreover, to test at different voltage current and power ratings one must use different panels each of which are very expensive and their performance and behavior deteriorates with aging. To overcome these problems, a photovoltaic module simulator must be developed which will mimic the electrical characteristics of solar photovoltaic modules and arrays at a fast rate while being cheap, light and easy to handle. Applications:

1. Testing and development of solar electric equipment, 2. As an aid for demonstration or laboratory experiments on solar photovoltaic panels.

Challenges: 1. Ensure flexibility of the I-V characteristics being simulated. 2. Fast time response of the analog section to enable study of transient phenomenon. 3. Isolation of switching noise from power circuit to analog circuit. 4. Minimization of power loss. 5. Accuracy, stability and reliability of the digital controller.

II. RESEARCH ACCOMPLISHMENTS A. A programmable simulator with 16x2 LCD display and user interface. B. A 100 KHz buck converter prototype is designed with L=10uH and C= 50µF. C. Measured crossover frequency= 7.1 kHz and phase margin=65.2 degrees º. D. A fast settling time of 200μs has been observed.

48


REFERENCES

[1] G. Vachtsevanos, K. Kalaitzakis, “A Hybrid Photovoltaic Simulator for Utility Interactive Studies” IEEE Transactions on Energy Conversion, Vol. EC-2, No. 2, June 1987. [2] Wang kui, Li Yongdong, Rao Jianye, Sun Min, “Design and Implementation of A Solar Array Simulator” IEEE Conference, Page(s): 2633 – 2636, 2008. [3] Cham Yew Thean, Jia Junbo, Au Wing Kong Eric. “An Embedded Microchip System Design for Programmable

Figure-1a: This plot shows the Synchronous buck

converter tracking the reference voltage.

Figure 1b: This plot shows the dynamic response of the

buck converter.

49


Energy Based DC-DC Boost Converter

Amit Patra , Pawan Gupta, and Jitendra Singh Kushwah #Dept. of EE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India [email protected] ; [email protected] ; [email protected]

Abstract— This work presents a new energy-based switching scheme for DC-DC boost converter. In this scheme, converter works in three modes depending on different conditions and these conditions will be derived by energy balance equations. These energy balance equation will give adjustable current and voltage reference. So when inductor current and output voltage will meet these references, converter will switch from one mode to another by controller of the converter which we call logic based switch controller will switch the converter in any of these three modes. The adjustable current and voltage references are the function of input voltage, output voltage and load current. So whenever there will be line or load transient, these reference will change in such a way that output voltage will remain unchanged. This scheme can be applied in DCM as well as in CCM mode also. We have verified both DCM and CCM schemes in hardware as well as in Pspice simulation and shown the advantage of the proposed control schemes. The state trajectories have been shown to reach a hybrid limit cycle already proved to be super stable.

Keywords— CCM mode, DCM mode, Phase Plane, Limit cycle, Sensitivity matrix, RHP zero, Bandwidth, energy balance, inductor current reference, output voltage reference.

I. RESEARCH PROBLEM: SCOPE AND MOTIVATION

As we know the average state space model of a boost converter in CCM mode contain a right half plane zero because of this converter has limited bandwidth and transient response is also poor. So to overcome this problem we can force the converter to work in DCM mode by choosing proper parameter (inductor, output capacitor, and load resistance), inductor current and output voltage references. As this scheme is variable frequency so we cannot find the transfer function but we have done the phase plane analysis which gives stable limit cycle, multiple Lyapunov function analysis which says system is asymptotic stable and Sensitivity Matrix analysis which verifies that system is super stable. But now if we want to use this converter for high load applications we have to run it in CCM mode then to remove the RHP zero we can place a switch across the inductor thus inductor will not go to zero in mode three but it will be having constant current above zero and if the duration of mode three is not constant then there will not be any RHP zero in the boost converter. The advantages of the proposed control scheme over the existing control scheme are given below-

• There is no chaos or sub-harmonic in the inductor current. • The average value as well as ripple value of the output voltage is controlled. • The transient response is quite good with respect to line and load disturbances.


The ongoing research on “Energy Based Switching Control of DC-DC Power Converters” in IITKgp started in 2003-2006 and then in 2009 again started by power management group. Contribution made so far:

• Energy based switching control for boost converter in DCM mode for possibility of rhp zero elimination. • Energy based switching control for boost converter in CCM mode using a switch across inductor for

possibility of RHP zero elimination. • Pspice simulation completed for both DCM as well as CCM mode.

Work done in past one year: • Design and fabrication of power circuit. • Design and fabrication of control circuit for DCM mode of operation. • Design and fabrication of control circuit for CCM mode of operation.

50


Fig.1 Inductor Current and Output Voltage Fig.2 Effect of Load Transient on output Fig. 1 shows the inductor current and output voltage for DCM mode of operation founded experimentally and Fig.2 shows effect of load transient on output voltage in Pspice ORCAD simulation.. Applications:

• +12V Flash memory programming supplies • +12V PCMCIA supplies • Solid state disk drives, palmtop computers & compact +12V op-amp supplies

III. RESEARCH ACCOMPLISHMENTS

A part of the above research work has already been disseminated to the engineering community in the form of following conference-paper, journal-publication and invention disclosure.

• Pawan Gupta and Amit Patra, “Hybrid Mode-Switched Control of DC-DC Boost Converter Circuits”, IEEE Trans. on Circuits and Systems-II, Vol 52, Nov. 2005, pp 734-738.

• Pawan Gupta and Amit Patra, “Super-Stable Energy Based Switching Control Scheme for DC-DC Buck Converter Circuits ”, IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, 2005, pp. 3063-3066.

• Pawan Gupta and Amit Patra, “A Stable Energy Based Control Strategy for DC-DC Boost Converter Circuits”, Proc. of IEEE Power Electronics Specialist Conference (PESC), Aachen, Germany, 2004, pp 3642-3646.


• Inductor current reference in DCM mode is a square root expression which is difficult to design so it could be changed.

• Output voltage reference is a constant reference so this could be changed.

REFERENCES [1] W. C. Wu, R. M. Bass, and J. R. Yeargan, “Eliminating the effects of right-half plane zero in fixed frequency boost converters”, in Proc.

IEEE PESC’98, vol. 1, 1998, pp.362-366. [2] K. Viswanathan, R. Oruganti and D. Srinivasan, “A Novel Tri-State Boost Converter With Fast Dynamics”, IEEE Transactions on Power

Electronics, Vol. 17, No. 5, pp.677-683, Sept 2002 [3] K. Viswanathan, R. Oruganti and D. Srinivasan, “Dual-Mode Control of Tri-State Boost Converter for Improved Performance”, IEEE

Transactions on Power Electronics, Vol. 20, No. 4, pp.790-797, July 2005. [4] Santanu Kapat, Amit Patra and Soumitro Banerjee, “A Current-Controlled Tristate Boost Converter with Improved Performance Through

RHP Zero Elimination”, IEEE Trans. on Power Electronics, Vol 24, NO. 3, MARCH 2009, pp776-786.

51


Estimation of On-resistance and Current Distribution Profile in On-chip Power MOSFET Layout

Jyotirmoy Ghosh*, Prof. Siddhartha Mukhopadhyay*, Prof. Amit Patra* and Barry Culpepper# *Dept. of Electrical Engineering, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India {[email protected], [email protected], [email protected]}

#National Semiconductor Corporation, Santa Clara, USA. {[email protected]}

Abstract— This work presents an accurate technique for estimation of the steady state behaviour of large lateral power MOSFET switches typically used in on-chip DC-DC converters, namely, the on-resistance (RDS(on)) and current distribution profile in MOSFET switch layout. In the proposed approach, an extracted netlist is generated which contains the parasitic resistances in lumped form extracted from the metal interconnects along with the MOS device fingers present in the layout. This approach is modular and exploits the highly symmetric and repetitive patterns of power MOSFET layouts to generate the resistance netlist with significant speed-up in the extraction process. The extracted resistance values in the interconnects are computed from the geometric parameters of the metal polygons without the requirement of solving complex EM field equations. The wide MOS fingers are decomposed into parallel devices to estimate the channel resistance with an accurate distribution of channel current over the width. Comparison of results with an industry standard EM solver tool as well as experimental measurements amply demonstrates the computational efficiency and accuracy of the approach establishing its applicability for industrial power array design.

Keywords— power MOSFET, layout, lumped network model, RDS(on) , current distribution profile

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION On-chip power MOSFET switches used in DC-DC converters have large channel (W/L) ratios, typically of the order of 104 to 107 and can carry currents up to several amperes. The layout of power MOSFETs are popularly known as ‘power array’ which have a complex metal interconnect structure. Since the power MOSFETs dissipate more power than other devices in the DC-DC converter circuit, it is important to design power switches with the lowest possible losses to ensure a high efficiency. Thus, selection of width to length (W/L) ratio of a switch depends on the accurate modeling and calculation of switch losses. For a power MOSFET, operating near full load, conduction loss is a significant part of the total losses in the switch, which is directly proportional to the RDS(on) of the MOSFET. Thus, determination of the switch losses accurately depends on accurate estimation of on-resistance.

The power switches are also required to be designed with highest current rating within a given area to meet high switch power density requirement. This means that the current distribution profile over the entire area should be uniform and formation of high current concentration zones, which may lead to electromigration and formation of hot-spots during the operation of the device, should be avoided. Thus, profiling of current distribution pattern is also important to verify whether the current in the metal layers is crossing the maximum allowable current density specified for that layer.

The main challenges in this work:

• EM field solving techniques like Finite Element Method (FEM) or Boundary Element Method (BEM) are computationally highly expensive both in terms of run time and memory overhead for large and complex power arrays. In many cases it is not possible to generate mesh and converge to the result given the system processor and memory constraints.

• It is not possible for the commercially available extraction tools to produce result with the accuracy level required by the designers tools due to the limitations in polygon fracturing technique of wide metal layers with dense vias/contacts connected in rows and columns, and resolution with which wide MOS fingers are extracted.

•

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II. RECENT RESEARCH ACTIVITIES The research on resistance extraction by the network modelling technique has been started in IITKgp in 2005.

We have demonstrated an automated circuit extraction technique that can use the advantages of the symmetry of power arrays to build computationally efficient network models for lateral power arrays and provide end-to-end solution (GDS file to extracted netlist). The level of accuracy achievable by this technique has been depicted in the following results:

• Estimation of RDS(on)

• Generation of current distribution profile:

Figure 1: Generated current distribution profile in Metal-2 layer of a 13500µ/0.5µ power array

III. RESEARCH ACCOMPLISHMENTS [1] J. Ghosh, S. Mukhopadhyay, A. Patra, B. Culpepper and T. Mei, “A New Approach for Estimation of On- resistance and Current Distribution in Power Array Layouts,” in Proc. 21st IEEE International Conference on VLSI Design, pp. 331-336, 2008. [2] J. Ghosh, S. Mukhopadhyay, A. Patra, B. Culpepper and T. Mei, “A New Approach for Estimation of RDS(on) of Power Arrays: Extensions and Experimental Results,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 3010-1013, 2009.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION The scope of future research activities are as follows:

• Extend the proposed technique for the power MOSFETs generated by vertical diffusion (VDMOS). • Extraction of parasitic capacitance formed in the metal interconnects of power MOSFET layout in order to

estimate the transient current distribution pattern in the power array and develop an accurate model of the post layout switching power losses in the power MOSFETs.

53

Use of PRES+ Models in High-Level Verification

S Bandyopadhyay C R Mandal D SarkarDepartment of Computer Sc & Engg

Indian Institute of Technology, KharagpurWB 721302, INDIA

{soumyadip, chitta, ds}@cse.iitkgp.ac.in

March 22, 2010

Abstract

The objective of this work is to model embedded system for behavioural verification. In this note, we have used a PRES+ modelas an extension of the classical Petri net model that captures concurrency and timing behaviour of an embedded system. Equivalencechecking method is widely used for behavioural verification of system. No equivalence checking method has been reported in theliterature for Petri net models. We seek to devise an algorithm to translate PRES+ models to FSMD models. Equivalence checkingmethods exists of FSMD models; we intend to use one such method by by translating the Petri net models into FSMD models. Areal life example of a Diamond Like Carbon (DLC) controller which captures all the features of PRES+ models except the timingbehaviour has been used to illustrate PRES+ models.

Keywords: Petri nets, Embedded systems, PRES+, Diamond Like Carbon.

1 Research Problem: Scope and MotivationIn this note we focus on some aspects related to modeling and formal verification of embedded systems. Many models have beenproposed to represent embedded systems [1] [2]. These models encompass a broad range of style, characteristics, and applicationdomain and in clude the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this note,we have used the class of PRES+ models as an extension of the classical Petri net models that captures concurrency and timingbehaviour of embedded systems; it allows systems to be represented in different levels of abstraction and improves expressivenessby allowing the tokens to carry information. This modeling formalism has a well defined semantics so that it supports a preciserepresentation of a system. As a first step, we have taken an untimed PRES+ model which captures all the features of PRES+ modelexcept the time behaviour.

A typical synthesis flow of complex systems like VLSI circuits or embedded systems comprises several phases. Each phasetransforms/refines the input behavioural specification (of the systems to be designed) with a view to optimise time and physicalresources. Behavioural verification involves demonstrating the equivalence between the input behaviour and the final design whichis the output of the last phase. In computational terms, it is required to show that all the computations represented by the inputbehavioural description and exactly those, are captured by the output description.

Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concur-rency. However, to the best of our knowledge, there is no equivalence checking method reported in the literature for PRES+ models.In contrast, equivalence checking method for FSMD models exist [3]. As a first step, we seek to devise an algorithm to translatePRES+ models to FSMD models. DLC controller is a machine which automatically control the reaction of DLC formation. DLCcontroller is combination of three controller such as pressure controller, temperature controller and soft rate controller. In this notewe have mentioned the mechanism of pressure controller only.

2 Recent Research ActivitiesThe translating algorithm which have been reported in the previous report has been implemented. Now we apply it on the exampleof the DLC controller. Basic operation of this controller is to coat a subtrate with DLC material. DLC is produced by mixing of thedifferent gases like nitrogen, oxygen and several gas catalysts like methane and hydrozen or some combination of amorphous carbon,each under some specified pressure which have been converted from sp2 hybridised carbon atom to sp3 hybridised carbon atom. Thecontroller need to capture concurrency because it controls pressure of the four gases chambers concurrently.

MKS 651C pressure controller is connected with 4 gas chambers. Every gas chambers are associated with valves and chambersthen it leads to a common chamber. Gas pressure is controlled with the position of valve. Pressure controller maintains a lookuptable which gives the information about chamber pressure vs valve position. Whenever we set the pressure of each gas chamber,in same pressure differnet amount of gas flow occurred. Then it mix in a separate chamber then controller checks wheather the setpressure value is equal to the chamber pressure value. If is is equal then gases are transfered to main reaction chamber by openingof the valve totally and mixed together. Otherwise, control signal goes to those gas chambers whose chamber pressure do not matchwith set pressure. Then reaction goes on in presence of particular pressure and particular number of moles of gases As the reactionis exothermic so controller also control the system temperature also. But for this simplicity we have modelled only the pressurecontroller part.

1

54

set pointExternal

Valve Position

Gas

Pressure Tranducer Scaling

Feedback

Look up Table

Figure 1: Control model for Pressure controller

Transfer set point value

[L< Value | L>Value]

L = F − Value

Request{(Initial+Value)*Set Point}

F = Request{(Initial+Value)

Scaling = F /1000

Set point}

L = F − Initial

System Pressure Value

Initial Value Set point

Set point value

[L == Value]

Feedback1

Pressure

Valve Controller

P1P2 P3

P4

P5

P6

P7

P8

P9

P10

t1t2

t3

t4

t5

t6

*Set point }

Command{(Initial+Value)*

Figure 2: PRES+ model for Pressure controller

3 Plan of Future work• Refinement of real life example which is discussed above.

• Generalisation of Timed FSMD model.

• Translation algorithm from PRES+ to Timed FSMD.

• Equivalence checking of Timed FSMD models.

References[1] Stephen Edwards, Luciano Lavagno, Edward A. Lee, and Alberto Sangiovanni-Vincentelli. Design of embedded systems:

Formal models, validation, and synthesis. In Proceedings of the IEEE, pages 366–390, 1997.

[2] P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop. Scheduling of conditional process graphs for the synthesis of embeddedsystems. In DATE ’98: Proceedings of the conference on Design, automation and test in Europe, pages 132–139, Washington,DC, USA, 1998. IEEE Computer Society.

[3] Chandan Karfa, Dipankar Sarkar, Chitta Mandal, and P. Kumar. An equivalence-checking method for scheduling verification inhigh-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(3):556–569, 2008.

55


Design of a Chip Emulation System for Test Development of Analog and Mixed Signal Circuits

S.Mukhopadhyay# and Rahul Bhattacharya* #Dept. of EE, Indian Institute of Technology, Kharagpur

WB 721302, India [email protected]

*Rahul Bhattacharya,AVDL Takshashila building,Kharagpur,WB 721302 India

[email protected]

Abstract—The objective of this paper is to propose a test emulation platform of AMS circuits based on Field Programmable Gated Array (FPGA).In this proposed platform, FPGA will act as a prototype of the circuit as well as a virtual DUT (Design Under Test) which can be used for test development of analog and mixed signal circuit. The proposed methodology exploits fixed-point modelling and DSP implementation technique facilitated by latest FPGAs to model the AMS circuits. In this approach, initially SPICE model(or behavioral model) of AMS circuits are developed using PSPICE(Cadence or MATLAB-Simulink).Later these floating-point model is mapped into fixed-point FPGA implementation using Xilinx-System Generator in Simulink environment. During this mapping word lengths are searched to minimize total hardware cost without degrading the system performance. This model is then programmed onto an FPGA,

Keywords— FPGA, Emulation, Virtual DUT.

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION The state-of-the-art technology has several major problems in the area of analog and mixed-signal circuit testing,

which can be summarized as follows : • Test planing starts towards the end of the design. • Test program debug after design of load board and silicon. • Test engineer and designer interaction mainly for debug.

Past research work in [2],[3],[4] and [5] attempted to address the problem with partial success. The on-going research activity by the IITKgpVLSI Test Group has shown that the problem may be solved by the means of an innovative approach of designing a test emulation platform for AMS circuits. The benefits of the proposed approach of designing a test emulation platform are:

• Test planing can start parallelly along with the design. • Test program debug much earlier before the design of load board and silicon. • Test engineer and designer interaction in the intermediate stages of the design and test flow.

The proposed methodology is first to show that • Mixed signal IC test development can be made efficient enabling the test engineer to emulate the test

environment and debug the test programs before silicon.

II. RECENT RESEARCH ACTIVITIES The on-going research by the IITKgpVLSI Test Group started in 2007. In the past we have demonstrated the

technique of discrete time modelling utilizing Xilinx-System Generator blocks in Matlab-Simulink platform. Using this technique we have modelled a 100KHz linear analog PLL and 200KHz current program controlled DC-DC buck converter, implemented on FPGA and shown that the FPGA emulation result is matching with the behavioural/Spice simulation of those AMS circuits.

Further we have developed an word-length optimizer which will search an optimum word-length to minimize the FPGA resource without degrading the desired system performance. The algorithm is validated on a first order low pass butterworth filter. It shows that

• Different set of word-length is allocated for different system performance metric and the resource is minimized.

• A quick estimate of the word-length can be achieved without degrading the performance metric .

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In FIGURE I, we show the basic steps of the new flow to design the chip emulation system based on FPGA

FIGURE I. Basic Steps of the proposed flow

III. SCOPE FOR FUTURE RESEARCH COLLABORATION The parts of the proposed flow requiring further improvement are as follows, on which we shall focus our

research activity next year: • Developing a timing estimate to determine the maximum sampling frequency, supported by the FPGA so that

system performance can be much better as well as to avoid timing failure while mapping onto FPGA.

REFERENCES [1] IEEE Document Formatting Guidelines Document [2] Boray S. Deepaksubramanyan, Priyank Parakh, Zhenhua Chen, Hussam Diab, Duane Marcy and Fred H. Schlereth,”An FPGA-Based

MOS Simulator” in 48 th Midwest Symposium on Circuits and Systems. [3] Brian Richards, Pierre-Yves Droz, Chen Chang, John Wawrzynek, Bob Brodersen, an article on “SCORE: System on a Chip Real-time

Emulation”. [4] Veikko Loukusa,“Behavioral Test Generation Modeling Approach for Mixed-signal IC Verification” in Microelectronics Journal Volume

34,Issue 10, October 2003,Pages 907-912. [5] Martine Dufils, Jean-Louis Carbonero, Philippe Planelle , Philippe Raynaud,” Mixed-Signal Simulation & Test Generation” in

International Conference on Design and Test of Integrated Systems in Nanoscale Technology,2006.

Design Specification

Verilog A/Simulink

/SPICE model

Fixed-pt DT modeling

using System Generator

Bit file generation and

FPGA programming

Test Stimulus Response

Word-length optimizer

Virtual DUT

(FPGA in place real DUT)

Timing Analyzer

Improve Design

If timing failure

HDL compiler/RTL

Generation ATE

57


Design and Optimization of Low-Power Low-Phase-Noise 2.4/4.8 GHz CMOS Voltage Controlled Oscillator for Short

Range Wireless Transceivers

Arivazhagan Perumal1, T.k.Bhattacharyya2

1,2Dept. of E&ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

Abstract

A 1-V 2.4/4.8-GHz 5.67 mW Quadrature Voltage Controlled Oscillator (QVCO) has been designed in 0.18 µm CMOS technology. All-pMOS LC-VCO followed by static frequency divider, CML buffer and bandgap reference are chosen for to generate a quadrature signals. The advantages of proposed QVCO are optimized and analyzed in terms of phase noise, power and suppress the higher order (≥3) harmonics through linearization. The best overall performance is displayed by the inversion mode pMOS varactor. The proposed QVCO is tuned from 2.39 to 2.51 GHz with a tuning voltage varying from 0 to 1 V, additional 80 MHz increased by switched capacitor array (SCA). Compared to the other types of QVCO, the proposed QVCO shows good 1/f3 close-in phase noise. The sensitivity of the divider is simulated from 50 to 510 mV to achieve the operating frequencies of 3.3 to 6.2 GHz.

Keywords — QVCO, SCA, varactor.

58


Dynamics and Synchronization of Delayed Feedback Nonlinear Oscillators

Pradeep Kumar Banerjee#, Dr. T K Bhattacharyya*, #Dept. of E&ECE, Indian Institute of Technology, Kharagpur

Kharagpur, WB 721302, India 1{pradeep.banerjee}@gmail.com

*Dept. of E&ECE, Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected]

Abstract— The response of a nonlinear optical oscillator subject to a delayed broadband bandpass filtering

feedback is studied numerically, and analytically. The oscillator uses electrooptic modulation and fiber optic transmission and the oscillation loop is characterized by a high cutoff frequency with a response time ~10 ps and by a low cutoff frequency with a response time ~1 us. Moreover, the optoelectronic feedback also consists of a significant delay TD of the order of 100 ns. Depending on two key physical parameters, the loop gain and the nonlinearity operating point, a large variety of multiple time scale regimes are reported, including slow or fast periodic oscillations with different waveforms, regular or chaotic breathers, slow time envelope dynamics, complex and irregular self-pulsing, and fully developed chaos. We also consider two such oscillators that are coupled to one another, and we identify the conditions under which they will synchronize. The large variety of oscillatory regimes of our broadband bandpass delay electrooptic oscillator is attractive for applications requiring rich optical pulse sources with different frequencies and/or wave forms (chaos-based communications, random number generation, chaos computing, and generation of stable multiple GHz frequency oscillations).

Keywords— multiple time scale dynamics, synchronization, optoelectronic oscillator, delay differential equations

I. RESEARCH PROBLEM : SCOPE AND MOTIVATION Time-delayed feedbacks are responsible for diverse phenomena such as regenerative chatter between the machine

tool and the workpiece, sudden changes in the qualitative dynamics of physiological processes, and laser pulsating outputs caused by optical feedback from a distant mirror. A popular way to describe these effects is to formulate delay differential equations (DDEs) where the state of a variable at time t depends on its value at time t− TD. However, DDEs are mathematically difficult to analyze and much of the recent understanding of their possible solutions essentially results from detailed computer simulations. This is particularly the case in optics where the effects of optical and optoelectronic feedback are studied in detail leading to systematic comparisons between experiments and theory. Delayed feedback enables such systems to generate a wide variety of waveforms, with differing degrees of complexity that depend on the parameters used. In particular, the time-delay, feedback strength, and filter parameters can be tuned to produce highly stable periodic waveforms [1] as well as complex waveforms that are characteristic of robust, high-dimensional chaos [2].

In this paper, we consider the case when the characteristic time scales of the system are separated by an order of magnitude. Dynamical systems with multiple time scales (also called singularly perturbed systems and slow-fast systems). The theory of systems with multiple time scales has been approached from at least three complementary viewpoints: nonstandard analysis, "classical" asymptotic methods, and geometric methods that have come to be called geometric singular perturbation theory. The research has been shaped both by a few seminal examples and a desire to characterize typical or generic behavior in these systems. These efforts have been limited by difficulty in computing unstable trajectory segments, called canards, and by difficulty in comprehending the complex geometry of solutions. In this research, we investigate delay induced canards in the Electroptic oscillator in which we have a nearly equally distributed logarithmic spacing of the different time constants.

59


II. RECENT RESEARCH ACTIVITIES The on-going research started in 2009. In the past we have demonstrated delayed feedback in a first order phase

locked loop gives rise to extremely complex dynamics, viz, delay induced desynchronization, cycle slips, etc. Further to that, we presented a detailed bifurcation analysis of desynchronization transitions in a system of two coupled phase oscillators with delay. The coupling between the oscillators combines a delayed self-feedback of each oscillator with an instantaneous mutual interaction. The delayed self feedback leads to a rich variety of dynamical regimes, ranging from phase-locked and periodically modulated synchronized states to chaotic phase synchronization and finally desynchronization via a crisis bifurcation (see FIGURE I).

FIGURE I. A Phase portrait showing Phase slips of the phase difference for K = 4.035 just after a

desynchronization transition via a crisis bifurcation

III. RESEARCH ACCOMPLISHMENTS A major contribution to understand the design principles and dynamics of complex networks was the proposal to

decompose such structures into the small repeating patterns of interconnectedness that conform the network, the so-called network motifs. We have also studied systems including coupled neurons, lasers as well open chains of phase oscillators to evaluate the influence of coupling delay and symmetry.

IV. SCOPE FOR FUTURE RESEARCH COLLABORATION The parts of the problem yet to be solved / parts of the proposed algorithm/architecture/etc requiring further

improvement are as follows, on which we shall focus our research activity next year: • Multiple time scale dynamics of the Electrooptic oscillator • Algorithms for Numerical continuation of solutions.

REFERENCES [1] Yao, X.S. & Maleki, L. 1996 Optoelectronic microwave oscillator. J. Opt. Soc. Am. B. 13, 1725–1735. [2] Peil, M., Jacquot, M., Chembo, Y.K., Larger, L. & Erneux, T. 2009 Routes to chaos and multiple time scale dynamics in broadband bandpass nonlinear delay electro-optic oscillators. Phys. Rev. E 79, 026208..

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ANNUAL REVIEW MEETING OF THE AVLSI CONSORTIUM, 2009-2010: RESEARCH NOTES

Low Power Transmitter for Wireless Body Area Networks Amitava Ghosh1, Dr. Achintya Halder2 and Dr. Anindya Sundar Dhar3

Dept. of Electronics & EC Eng., Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected]; {achintya

2, asd

3}@ece.iitkgp.ernet.in

Abstract— An ultra-low power transmitter operating in the Medical Implant Communications Service (MICS)

band is being designed. A group of transmitter chips will carry biomedical data (coming from sensors attached to human body) to the controller receiver(s), where the individual transmitter has the requirement of minimizing the energy transmitted per bit. The transmitter uses Binary/Gaussian Frequency Shift Keying (BFSK / GFSK) modulation and supports multiple data rates consistent with the sensors’ data acquisition speed. Top-down optimization of the architectural level down to the circuit level and circuit innovations are used so that circuit power consumption is reduced without compromising overall system Bit Error Rate (BER).

Keywords—Wireless body area network, Ultra-low power wireless transmitter, Uncertain-IF wireless transceiver

architecture, MICS band, Biotelemetry


Several transceivers have been proposed for using in the MICS band, which was commissioned by the Federal Communications Committee (FCC) in 1999. However, the requirement of lowering the circuit power consumption still exists for body area network. Past research work in [1], [2] and [3] have attempted to address this requirement with partial success. While aiming at lower power-consumption in CMOS process based implementation, a few of the existing schemes have tried to do away with any frequency synthesizer and attempted to run the RF carrier generation block in open-loop. However, because of the frequency stability issues, these implementations suffer from low BER obtained from simpler modulation schemes and low maximum data-rate.

The on-going research activity by the research group under Dr. Achintya Halder is currently exploring a different architectural level and circuit-level solution of the problem for CMOS process based implementation. In this architecture, the constant frequency spacing of the two tones of FSK is exploited for data transmission and the VCO frequency can vary (within a certain limit), so that only a coarse tuning of the VCO is needed, precluding the need for a fully-blown frequency synthesizer. The benefits of the above approach are:

The absence of a synthesizer would significantly reduce circuit power consumption in the transmitter. The VCO frequency can vary without sacrificing BER.

In addition, the proposed methodology aims to: be compliant with the MICS frequency band allocation and effective radiated power specification top-down (architectural level down to circuit level) system optimization for the design. circuit design of the transmitter and integration of the transmitter into body-area-network, while satisfying

the need for significantly lowering the power consumption. The architecture of the entire communication system is shown in FIGURE I. Each of the transmitter nodes (2a,

2b, …) interfaces with sensor electronics (A, B, C, …) and acquires the sensor-data (representing various vital signatures, e.g. blood pressure, ECG data, etc.) from one or more sensors. The transmitter subsequently sends out the buffered data to the data-receiver and controller node (4) of the body-area-network (5), upon request from the controller.

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FIGURE I. Network Architecture Block Diagram


The architecture of the transmitter system is given in FIGURE II. The transmitter RF front-end and baseband circuitry are normally asleep, until the transmitter receives a wake-up / transmit / data-collect requests through wake-up receiver section (not shown) within the transmitter architecture.

FIGURE II. Simplified Architecture of the Transmitter

From the inception of the project (August 2009), the following has been achieved: Architectural level modelling of the individual transmitters consisting of internal modules (PA, VCO, pulse-

shaping, etc.) Theoretical analysis and modelling of the block-level non-idealities (non-linearity, phase noise, etc) on system

performance The design of the algorithm for the synthesizer-less, low on-time/duty-cycle frequency calibrator


Current accomplishments are described in the previous section of this research-note, which will be put forward in detail in future for peer review and publication.


Our upcoming research activity will focus on: Finalizing the top-down optimization algorithm and circuit-to-system back annotation of the specification Realization and integration of the transmitter sub-modules in silicon

The proposed architecture can be deployed in other wireless sensor networks, where system power dissipation is the main bottleneck, and will subsequently help in significantly reducing the energy consumed per transmitted bit.

REFERENCES [1] D. Panescu, “Emerging Technologies wireless communication systems for implantable medical devices”, IEEE Engineering in Medicine

and Biology Magazine, Volume 27, Issue 2, 2008, Page(s) 96-101 [2] A. Tekin, M. R. Yuce and W. Liu, “Integrated VCOs for medical implant transceivers”, Hindawi Publishing Corporation VLSI Design

Volume 2008, Article ID 912536, DOI: 10.1155/2008/912536 [3] T. Tanzawa, H. Shibayama, R. Terauchi et al., “A Temperature Compensated CMOS LC-VCO enabling the direct modulation architecture

in 2.4 GHz GFSK transmitter”, Custom Integrated Circuits Conference, 2004, Lille France, Proceedings of the IEEE 2004, Page(s) 273-276.

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Low Power Receiver for Wireless Body Area Networks Arunkumar Salimath1, Dr. Achintya Halder2

Dept. of Electronics & EC Eng., Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected], [email protected]

Abstract— This research aims to develop an ultra-low power receiver for biotelemetry and wireless body area

network (WBAN) applications. The 402–405 MHz Medical Implant Communication Service (MICS) band, which has reasonable signal propagation characteristics through human body, providing higher data rate and longer range. Binary/Gaussian Frequency Shift Keying (BFSK / GFSK) modulation scheme, supporting multiple baseband data rate up to 1 MBps is used. An uncertain Intermediate Frequency (IF) architecture is chosen owing to the low power requirement.

Keywords—Wireless body area network, Ultra-low power wireless receiver, Uncertain-IF wireless transceiver

architecture, MICS band, Biotelemetry.


The state-of-the-art technology in the area of low-power RF communication link used in biomedical applications has several open-ended problems [1], the primary ones of which can be summarized as follows:

Need for ultra low power consumption considering the battery life Need for higher data rates whenever required Need for longer range of operating distance

Past research work in [2] and [3] have attempted to address the problem. However, the use of sliding IF architecture by [2] and direct down conversion architecture by [3] has resulted in the clock generation and calibration blocks consuming major part of the total power. Moreover, the maximum data rate achieved is limited to ~ 50 kbps. The attempt to use dual band in [2] has resulted in reduced sensitivity and operating range.

The on-going research activity by the research group lead by Dr. Achintya Halder is currently exploring the solution by the means of an innovative approach of uncertain-IF architecture for the receiver. The benefits of the proposed approach are:

Employing an uncertain intermediate frequency largely relaxes the phase noise and frequency accuracy specifications, allowing the use of oscillator with reduced calibration.

The resulting receiver architecture can be realized without using full-fledged synthesizer and therefore reducing the overall receiver power consumption.

The proposed receiver architecture is going to be used in wireless body-area-network application, a high-level scheme of which is shown in FIGURE I. The transmitter nodes (2a, 2b, …) located at various sensor-sites (3a, 3b, 3c, …) of the human body acquire sensor data (representing various vital signatures, e.g. blood pressure, ECG data, etc.) and send wirelessly over the body-area-network (5) to the controller/receiver (4). The proposed receiver architecture resides within (4).

FIGURE I. Network Block Diagram

63



Since the beginning of this research activity in August 2009, we have reviewed and analysed the state of the art and the subsequent improvement areas that were identified are:

Conventional Zero-IF and Low-IF architectures, being the special cases of superheterodyne, require high-degree of accuracy of the RF front-end oscillators and, hence, their excessive power floor.

The tuned front-end RF architectures are limited by the requirement of narrow-band filtering directly at the RF front-end and the limited RF gain, resulting in poor receiver sensitivity.

Considering these facts and the required specifications, uncertain-IF architecture tends to be a suitable trade-off between the two. In FIGURE II, we show the proposed architecture.

FIGURE I. Uncertain-IF architecture for the receiver


As a part of the above research work, a detailed theoretical analysis of the different architectures has been carried out. The first order frequency planning for the uncertain IF has been carried out. Low power envelope detector topologies and the passive mixer based detectors offering a high conversion gain are being studied. The design is targeted to achieve a sensitivity of -100 dBm and BER of 10-3, consuming 10 mW of power from a 1 V supply. The analysis and further circuit implementations are going to be put forward in future for peer review and academic dissemination.


The set of problems associated with the proposed architecture, on which we shall focus our research activity next year, are as follows:

Detailed mathematical modelling and simulation of the proposed architecture and comparison with the results from the state of the art.

Silicon implementation of the architecture using low power circuit techniques, while maintaining the data integrity.

REFERENCES [1] Didier Sagan, “RF Integrated Circuits for Medical Applications”, http://stf.ucsd.edu/presentations/2007-08%20STF%20-

%20Zarlink%20ULP%20transceivers.pdf [2] A.Wong et. al., “A 1 V Wireless transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications”, IEEE J. Solid State Circuits,

vol. 43, no.7, pp.1511-1521, Jul. 2008. [3] N. Cho et. al. “A 10.8 W Body Channel Communication / MICS Dual-band Transceiver for a Unified Body Sensor Network Controller”,

IEEE J. Solid State Circuits, vol. 44, no.12, pp. 3459-3468, Dec. 2009.

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Active Inductor based Multi-band LNA V. Sanjay, Achintya Halder

Dept. of Electronics and EC Eng., Indian Institute of Technology, Kharagpur Kharagpur, WB 721302, India

[email protected], [email protected],

Abstract— In the present and the emerging wireless standards there is a strong motivation of using a single radio system, which can support multi-band and multi-standard communication for lowering the hardware cost and enabling concurrent access to different services. In such a multi-standard RF system, one of the most critical requirements is the design of front-end low noise amplifier (LNA). A LNA with active inductor load has been designed with a quality factor over 150, which can be tuned anywhere between 1.5 GHz to 3 GHz. The LNA is designed for differential mode of operation and post layout simulation shows a gain of greater than 30 dB for the entire frequency of operation with Noise Figure less than 5 dB. The differential LNA has been designed using current reuse technique thereby reducing the power requirement. The LNA requires a supply voltage of 1.8 V and consumes a power of less than 7 mW for its operation. The LNA has been evaluated in 0.18 micron CMOS process.

Keywords- CMOS, High-Q Active Inductor, Multi-band, Low Noise Amplifier (LNA).


Active inductor is now becoming a highly attractive choice for CMOS wireless communication systems [1] to [3]. It has unique advantages over spiral inductors viz. it occupies smaller die area, it is tunable and has higher quality factor than passive on chip inductors.


An improved differential source degenerated LNA with tunable active inductor and using current reuse technique has been designed. The s21 (forward gain) and Noise figure plots for various frequencies between 1 GHz to 3.5 GHz is shown in Figure I and Figure II respectively. The s21 plots clearly show a gain of more than 35 dB for frequency range of 1.5 GHz to 3 GHz. The LNA could also be tuned for frequencies below 1 GHz also, however the gain is around 20 to 25 dB.

Figure I: S21 plots for Post layout simulation

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FIGURE II: Noise Figure plots for Post layout simulation


The LNA is reconfigurable, more power efficient and cost effective compared to the parallel architecture in present day multi-standard RF receivers, thus will prove to be of significant use to the Communication industry. A comparison with the sate-of-the-art is shown below:

Sl No. Figure of Merit [2] [5] [6] [7] This work

1 Gain 26 dB 25 dB 19 dB 26 dB > 30 dB 2 Freq of operation 2.4G 2.4G – 5.5G 4G 6.8 -20G 1.5G - 3G 3 Frequency Tuning Fixed Tunable Fixed Tunable Tunable 4 Narrow band operation BW 200M 500M 500M 1400M 10M

5 Power Consumption 12 mW

(Single ended) 5 mW

(Single ended) 8 mW

(single ended) 27.3 mW

(Differential) 7 mW

(Differential) 6 Noise Figure 2.5 dB 2.2 dB 4.3 dB 3.3 dB < 3.5 dB 8 IIP3 +10 dBm -3.2 dBm -12 dBm -7 dBm >-5 dBm 9 S11 -10 dB -12 dB -15 dB -13 dB -15 dB

11 Technology 0.18 um 0.13 um 0.13 um 0.18 um 0.18 um


As the next step, we shall focus our research activity next year on: • Validating the above multiband LNA design using prototype measurements • Extending the existing design for Medical Implant Communication Service (MICS) band (402–405 MHz), for tuned

front-end type architecture.

REFERENCES

[1] M. J. Wu, Y. H. Lee, Y. Y. Huang, Y. M. Mu, J. T. Yang, “A CMOS Multi-band Low Noise Amplifier Using High-Q Active Inductors”, International Journal of Circuits, Systems and Signal Processing, Issue 2, Vol. 1, 2007 [2] J. Y. Li, C. S. Chang, W. J. Lin, H. J. Chen, L. S. Chen, M. P. Houng, “A 2.4 GHz Highly Linear Image rejection Low Noise Amplifier By Using An Active Inductor”, Wiley Periodicals, Inc. Microwave Opt Techno Lett 51: 1570–1573, 2009. [3] A. Pascht, J. Fischer, M. Berroth, “A CMOS Low Noise Amplifier at 2.4 GHz With Active Inductor Load”, Topical Meeting on Digest of Papers. Sep 2001. [4] R. Venkatesh, “Design of a Low power 5GHz CMOS Radio frequency Low Noise Amplifier”, Link: http://www.eng.auburn.edu /~vagrawal/ course/ e6270_spr09/ project/ rakshith/ rf _project _ report . pdf [5] C. T. Fu, C. L. Ko, C. N. Kuo, “A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multi standard Wireless Receiver”, IEEE Transactions on Microwave Theory and Techniques, Volume 56, Issue 12, Part 1, Dec 2008. [6] S. Joo, T. Y. Choi, J. Y. Kim, B. Jung, “A 3-to-5 GHz UWB LNA with a low-power balanced active balun”, IEEE Symposium on Radio Frequency Integrated Circuits, Jun 2009. [7] Y. S. Hwang, S. F. Wang, J. J. Chen, “A differential multi-band CMOS low noise amplifier with noise cancellation and interference rejection” Intl. J. Electron. Commun, Jun 2009.

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