Complete Vlsi Notes

JAIN University – Regulations, Scheme & Syllabi B.E (Electronics & Communication Engineering). 2009-10

7

Semester –VI Digital VLSI Design

Subject Code: EC 64 Total No. of Hrs: 48 Credits: 4 Hours per week: 4 MOS Transistor Theory Introduction, MOS device design equations, Complementary CMOS Inverter-DC characteristics, Static Load MOS Inverters, Differential Inverter, Transmission Gate, Tristate Inverter, Bipolar devices CMOS Processing Technology Silicon semiconductor technology An overview, basic CMOS technology, CMOS process enhancements, Layout Design rules, Latchup, Technology related CAD issues Circuit Characterization and performance Estimation Resistance Estimation, Capacitance Estimation, Inductance, Switching Characteristics, CMOS gate transistor sizing, Power dissipation, sizing routing conductors, charge sharing, Design Margining, Yield, reliability Scaling of MOS circuits Scaling principles, Interconnect layer scaling, Scaling models and scaling factors, scaling factors for device parameters, some discussion on scaling, and limitations of scaling. CMOS Circuit and Logic Design Introduction, CMOS Logic Gate Design, Basic Physical Design of Simple Logic Gates, CMOS Logic Structures Clocking Strategies, I/O Structures, Low power Design CMOS Subsystem Design I Introduction, Data path operations- Addition/ subtraction, Parity Generators, Comparators, Zero/one detectors, Binary counters, Boolean operations-ALUs, Multiplication, Shifters CMOS Subsystem Design II Memory Elements, Control-FSM, Control Logic Implementation

Reference Books: 1. Principles of CMOS VLSI design – Neil Weste & Kamaran Eshraghian 2. CMOS Digital Integrated Circuits Analysis and Design- Sung-mo-kang & Yusuf

Leblebici

Digital VLSI Design, ECE Dept.SET,JU. Page 1

MOS Transistor Theory

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Introduction

The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the fundamental

building block of MOS and CMOS digital integrated circuits. Compared to the bipolar junction

transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication

involves fewer processing steps. These technological advantages, together with the relative

simplicity of MOSFET operation, have helped make the MOS transistor the most widely used

switching device in VLSI and VLSI circuits.

The MOSFET is a four terminal device. The voltage applied to the gate terminal

determines if and how much current flows between the source and the drain ports. The body

represents the fourth terminal of the transistor. Its function is secondary as it only serves to

modulate the device characteristics and parameters.

At the most superficial level, the transistor can be considered to be a switch. When a voltage is applied to the gate that is larger than a given value called the threshold voltage VTh, a conducting channel is formed between drain and source. In the presence of a voltage difference

between the latter two, current flows between them. The conductivity of the channel is

modulated by the gate voltage—the larger the voltage difference between gate and source, the

smaller the resistance of the conducting channel and the larger the current.


� A conducting channel will eventually be formed through applied gate voltage in the

section of the device between the drain and the source diffusion regions. The distance

between the drain and source diffusion regions is the channel length L, and the lateral

extent of the channel (perpendicular to the length dimension) is the channel width W.

� Both the charnel length and the channel width are important parameters which can be

used to control some of the electrical properties of the MOSFET.

� The thickness of the oxide layer covering the channel region, tox, is also an important

parameter.

ENHANCEMENT-mode and DEPLETION-mode MOSFET.

1. ENHANCEMENT-mode MOSFET:

A MOS transistor which has no conducting channel region at zero gate bias is

called 'an enhancement-type (or enhancement-mode) MOSFET.

MOSFET diagram

n-channel and p-channel enhancement MOSFET normally OFF, below Threshold

and above VTh on + VGS in n-MOSFET and - VGS in p-MOSFET

Symbol:

2. DEPLETION-mode MOSFET :

If a conducting channel already exists at zero gate bias, on the other hand, the device is called a depletion-type (or depletion-mode) MOSFET.


MOSFET diagram

n-channel and p-channel Depletion MOSFET normally ON, Pinch off on –VGS in n-MOSFET and + VGS in p-MOSFET Symbol

MOSFET Explanation

In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device with p-type substrate is called an n-channel MOSFET.

In a MOSFET with n-type substrate and with p+ source and drain regions, on the

other hand, the channel is p-type and the device is called a p-channel MOSFET.

The device terminals are: G for the gate, D for the drain, S for the source,

and B for the substrate (or body).

In an n-channel MOSFET, the source is defined as the n region which has

a lower potential than the other n region, the drain.

By convention, all terminal voltages of the device are defined with respect to the

source potential. Thus, the gate-to-source voltage is denoted by VGS, the drain-to-

source voltage is denoted by VDS, and the substrate-to-source voltage is denoted

by VBS.


Consider first the n-channel enhancement-type MOSFET shown in Figure. The simple operation

principle of this device is: control the current conduction between the source and the drain,

using the electric field generated by the gate voltage as a control variable. Since the current flow

in the channel is also controlled by the drain-, to-source voltage and by the substrate voltage, the

current can be considered a function of these external terminal voltages. In order to start current

flow between the source and the drain regions, however, we have to form a conducting channel

first.

Region of Operation

I. Cut off Region When gate-to-source voltage is less than threshold voltage i.e., VGS <VTh . There will be

no channel across the surface and no current between source and drain i.e., ID=0 as show in

above figure.


II. Resistive/Linear Operation (Active Region)

Now assume that the gate-to-source voltage is further increased. The conducting n-type

layer will form between the source and the drain diffusion regions as shown in below figure.

This channel now provides an electrical connection between the two n+ regions, and it allows

current flow, as long as there is a potential difference between the source and the drain terminal

voltages. The bias conditions for the onset of surface inversion and for the creation of the

conducting channel are therefore very significant for MOSFET operation.

Now VGS > VTh and that a small voltage, VDS, is applied between drain and source. The voltage difference causes a current ID to flow from drain to source. Using a simple analysis, a first-order expression of the current as a function of VGS and VDS can be obtained.

At a point x along the channel, the voltage is V(x), and the gate-to-channel voltage at that point equals VGS – V(x). Under the assumption that this voltage exceeds the threshold voltage all along the channel, the induced channel charge per unit area at point x can be computed.

Qi(x) = –Cox[VGS – V(x) – VTh]--------------------1.1 Cox stands for the capacitance per unit area presented by the gate oxide, and equals


With ox = 3.97o = 3.5 10-11 F/m the oxide permittivity, and tox is the thickness of the oxide.

The current is given as the product of the drift velocity of the carrier’s n and the available charge. Due to charge conservation, it is a constant over the length of the channel. W is the width of the channel in a direction perpendicular to the current flow.

----------------------- 1.2

The electron velocity is related to the electric field through a parameter called the mobility (expressed in m2/V s). The mobility is a complex function of crystal structure, and local electrical field. In general, an empirical value is used.

--------------------------------1.3

---------------1.4 Substitute equations 1.1 and 1.3 in 1.2 yields Integrating the equation over the length of the channel L yields the voltage-current relation of the transistor with boundary conditions x=0 to L and V=0 to VDS along the channel

------------------------------------------1.5 Where kn

’, is called the process transconductance parameter and equals

-------------------------------1.6 The W and L parameters in Equation the effective channel width and length of the transistor respectively.


III. The Saturation Region

As the value of the drain-source voltage is further increased, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold. This happens

when VGS V(x) < VTh. At that point, the induced charge is zero, and the conducting channel

disappears or is pinched off. Figure shows that the current is not valid beyond the linear region/ saturation region

boundary, i.e., for

VDS DSAT = V

GS- V

Th-------------------------1.7 Also, drain current measurements with constant VS show that the current ID does not show much

variation as a function of the drain voltage. VDS beyond the saturation boundary, but rather remains

approximately constant around the peak value reached for VDS = VDSAT .This saturation drain current level can be found simply by substituting Eq.5 in Eq.4

------------1.8


MOSFET Current-Voltage Characteristics

Figure shows the typical drain current versus drain voltage characteristics of an n-channel MOSFET, as described by the current equations (4) and (6). The parabolic boundary between the linear and the saturation regions is indicated here. The current-voltage characteristics of the MOS transistor can also be visualized by plotting the drain current as a function of the gate voltage, as shown in Fig. This ID Versus VGS transfer characteristic in saturation mode (VDS > VDSAT) provides a simple view of the drain current increasing as a second-order function of the gate-to source voltage The current is obviously equal to zero for any gate voltage smaller than the threshold voltage VT


Body effect on Threshold Voltage

As the gate voltage increases, the potential at the silicon surface at some point reaches a

critical value, where the semiconductor surface inverts to n-type material. This point marks the

onset of a phenomenon known as strong inversion and occurs at a voltage equal to twice the Fermi Potential.

---------1.9 Further increases in the gate voltage produce no further changes in the depletion layer width, but

result in additional electrons in the thin inversion layer directly under the oxide. These are drawn

into the inversion layer from the heavily doped n+ source region. Hence, a continuous n-type

channel is formed between the source and drain regions, the conductivity of which is modulated

by the gate-source voltage. In the presence of an inversion layer, the charge stored in the

depletion region is fixed and equals

------------1.10 This picture changes somewhat in case a substrate bias voltage VSB is applied (VSB is

normally positive for n-channel devices). This causes the surface potential required for strong inversion to increase and to become |–2 F + VSB|. The charge stored in the depletion region now is expressed by

----------1.11 The value of the gate-to-source voltage VGS needed to cause strong surface inversion (to create the conducting channel) is called the threshold voltage VTh. VTh is a function of several components, most of which are material constants such as

the difference in work-function between gate and substrate material,

the oxide thickness,

the Fermi voltage,

the charge of impurities trapped at the surface between channel and gate oxide, and

The dosage of ions implanted for threshold adjustment.

From the above arguments, it has become clear that the source-bulk voltage VSB has


an impact on the threshold as well. We rely on an empirical parameter called VT which is the threshold voltage for VSB = 0, and is mostly a function of the manufacturing process. The threshold voltage under different body-biasing conditions can then be determined in the following manner,

-----------1.12 The parameter (gamma) is called the body-effect coefficient, and expresses the impact of changes in VSB.

----------------1.13 Substrate Bias Effect

Note that the derivation of linear-mode and saturation-mode current-voltage characteristics in the previous pages has been done under the assumption that the substrate potential is equal to the source potential, i.e., VSB = 0. Consequently, the zero-substrate bias threshold voltage VTh has been used in the current equations. In many digital circuit applications, on the other hand, the source potential of an nMOS transistor can be larger than the substrate


potential, which results in a positive source-to-substrate voltage VSB > 0. In this case, the influence of the nonzero VSB upon the current characteristics must be accounted for.

We can simply replace the threshold voltage terms in linear-mode and saturation-mode current equations with the more general VTh(VSB) term.

Channel Length Modulation

We will examine the mechanisms of channel pinch-off and current flow in saturation mode. Consider the inversion layer charge Qi that represents the total mobile electron charge on the surface. The inversion layer charge at the source end of the channel is

Q(X=0 ) = -COX (VGS-VTh)

and the inversion layer charge at the drain end of the channel is

Q,(x= L) = -CoX (VGS - VTh - VDS))------1.14 Note that at the edge of saturation, i.e., when the drain-to-source voltage reaches VDSAT,

VDS = VDSAT = VGS - VTh The inversion layer charge at the drain end becomes zero according to Eq. 1.14.In reality, the channel charge does not become exactly equal to zero but it indeed becomes very small.

CMOS (COMPLEMENTARY MOSFET) MOS INVERTERS: STATIC CHARACTERISTICS

The logic symbol and the truth table of the ideal inverter are shown in Figure, In MOS

inverter circuits, both the input variable A and the output variable B are represented by node

voltages, referenced to the ground potential. Using positive logic convention, the Boolean (or

logic) value of "1" can be represented by a high voltage of VDD, and the Boolean (or logic)

value of "0" can be represented by a low voltage of 0. The DC voltage transfer characteristic

(VTC) of the ideal inverter circuit is shown in Figure.


The voltage Vth is called the inverter threshold voltage. Note that for any input voltage

between 0 and Vth = VDD/2 , the output voltage is equal to VDD (logic" 1 ). The output switches

from VDD to 0 when the input is equal to Vth. For any input voltage between Vth and VDD, the

output voltage assumes a value of 0 (logic "0"). Thus, an input voltage 0 < Vin. < Vth is

interpreted by this ideal inverter as a logic "0," while an input voltage Vth <Vin < VDD is

interpreted as a logic “1." The VT characteristics of the ideal Inverter shown in below Figure.

Noise Immunity and Noise Margins To illustrate the effect of noise on the circuit reliability, we will consider the circuit

consisting of three cascaded inverters, as shown in below Figure. Assume that all inverters are

identical, and that the input voltage of the first inverter is equal to VOH, i.e., logic “1." By

definition, the output voltage of the first inverter will be equal to VOL corresponding to a logic

"0" level.

VIL is the maximum allowable voltage at the input of the second inverter, which is low

enough to ensure a logic "1" output VIH is the minimum allowable voltage at the input of the third inverter which is high

enough to ensure a logic "0" output. These observations lead us to the definition of noise tolerances for digital circuits, called noise

margins and denoted by NM. The noise immunity of the circuit increases with NM. Two noise

margins will be defined: the noise margin for low signal levels (NML) and the noise margin for

high signal levels (NMH). For a gate to be robust and insensitive to noise disturbances, it is

essential that the “0” and “1” intervals be as large as possible. A measure of the sensitivity of a

gate to noise is given by the noise margins

LOW noise margin NML=VIL-VOL HIGH noise marginNMH=VOH-VIH


VOH: Maximum output voltage when the output level is logic “1”

VOL: Minimum output voltage when the output level is logic “0”

VIL: Maximum input voltage which can be interpreted as logic "0"

VIH: Minimum input voltage which can be interpreted as logic "1"


CMOS inverter Now, we will turn our attention to a radically inverter structure, which consists of an

enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in

complementary mode. This configuration is called Complementary MOS (CMOS). The circuit

topology is complementary push-pull in the sense that for high input, the NMOS transistor drives

(pulls down) the output node while the PMOS transistor acts as the load, and for low input the

PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.

Consequently, both devices contribute equally to the circuit operation characteristics.

The CMOS inverter has two important advantages over the other inverter configurations.

The first and perhaps the most important advantage is that the steady-state power

dissipation of the CMOS inverter circuit is virtually negligible, except for small power

dissipation due to leakage currents.

The other advantages of the CMOS configuration are that the voltage transfer

characteristic (VTC) exhibits a full output voltage swing between 0 V and VDD, and that

the VTC transition is usually very sharp. Thus, the VTC of the CMOS inverter resembles

that of an ideal inverter.


VTC curve and output Voltage at different region of operation


Region A:

Region B:


Region C: PMOS, NMOS: saturation

EQUATION-B


Region D:

Region E:

EQUATION-D


Beta Ratio Effects

kR= ܖܘ

=

We have seen that for kp = kn, the inverter threshold voltage Vth is VDD/2. This may be

desirable because it maximizes noise margins and allows a capacitive load to charge and

discharge in equal times by providing equal current source and sink capabilities. Inverters with

different beta ratios kR= kn /kp are called skewed inverters

If kR < 1, the inverter is HI-skewed.

If kR >1, the inverter is LO-skewed.

If kR = 1, the inverter has normal skew or is unskewed.

A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD /2, we

would expect the output will be greater than VDD /2. In other words, the input threshold must be

higher than for an unskewed inverter. Similarly, a LO-skew inverter has a weaker pMOS

transistor and thus a lower switching threshold.


Static Load MOS Inverters The figure shows a NMOS inverter with resistive load or a constant current source. For resistor

load, if we superimpose the resistor load line on VI characteristics of Pull down transistor as in

figure B, we can see that at VGS=5 volts, the output is some small VDS(VOL).when

VGS=0volts,VDS rises to 5 volts.

As resistor load is made larger, the VOL decreases and current flowing when inverter is

turned on decreases.

As resistor load is made smaller, the VOL increase and on current increases

Selection of resistor value would seek compromise between VOL, the current drawn and the

pull up speed

Note that the driver MOSFET is initially in saturation, since its drain-to source voltage. (VDs = V0ut=VDD) is larger than (Vin - Vth) =VGS-Vth VDs>> VGS-Vth NMOS Saturation current is given by

IR =kn(௩ି௩)మ

ଶ


With increasing input voltage, the drain current of the driver also increases, and the output voltage Vout starts to drop. Eventually, for input voltages larger than Vout + Vth, the driver transistor enters the linear operation region. At larger input voltages, the transistor remains in linear mode, as the output voltage continues to decrease.

i.e., Vin> Vout + Vth Vout< Vin-Vthn VDS< VGS-Vth,n


The Pseudo nMOS Inverter The Pseudo nMOS Inverter uses a p device pull up or load that has its gate is

permanently grounded. An n-device pull down or driver is driven with the input signal. This is

roughly equivalent to use of load in nMOS technology and is thus called “pseudo-nMOS”

When driver is turned on, constant DC current flows in the circuit. This is to contrasted with

CMOS inverter in which no DC current flows when the input is either the terminal high or low

state. The importance of whether DC current flows, and hence whether one can use pseudo

nMOS inverter, depends on application

Derivation of output voltage equation and n/ p

Consider PMOS


Consider NMOS

PMOS always in ACTIVE region

for VGS <VTh,p

NMOS in Saturation region

for VGS >VTh,n and VDS> VGS-VTh,n Vout> Vin-Vthn

Equating both the current equations


DC transfer characteristics


Transmission gate The strength of a signal is measured by how closely it approximates an ideal voltage

source. In general, the stronger a signal, the more current it can source or sink. The power

supplies, or rails, (VDD and GND) are the source of the strongest 1s and 0s

An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it

passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage

level is somewhat less than VDD; NMOS transistors pass ‘0’s well but 1s poorly. We are now

ready to better define “poorly.” Figure shows an nMOS transistor with the gate and drain tied to

VDD. Imagine that the source is initially at Vs = 0. Vgs > VTh, so the transistor is ON and current

flows. If the voltage on the source rises to Vs = VDD – Vth, Vgs falls to Vth and the transistor

cuts itself OFF. Therefore, nMOS transistors attempting to pass a 1 never pull the source above

VDD – Vth

Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source drops below |Vtp|,

the transistor cuts off. Hence, pMOS transistors only pull down to within a threshold above

GND, as shown in Figure


When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it as a pass

transistor. By combining an nMOS and a pMOS transistor in parallel. We obtain a switch that

turns on when a 1 is applied to g, in which 0s and 1s are both passed in an acceptable fashion.

We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be

passed, the appropriate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS

device. Note that both the control input and its complement are required by the transmission

gate. This is called double rail logic. Some circuit symbols for the transmission gate are shown

in Figure.

Thus, the nMOS transistors only need to pass 0s and the pMOS only pass 1s, so the

output is always strongly driven and the levels are never degraded. This is called a fully

restored logic gate and simplifies circuit design considerably.


TRISTATE INVERTERFigure shows symbols for a tristate Inverter. When the enable input EN is 1, the output

Y equals the input complement of A, just as in an ordinary inverter. When the enable is 0, Y is left

floating (‘Z’ value).


Figure shows a tristate inverter. The output is actively driven from VDD or GND, so it is a

restoring logic gate. The tristate inverter does not obey the conduction complements rule because

it allows the output to float under certain input combinations.

When EN is 0, both enable transistors are OFF, leaving the output floating. When EN is 1, both enable transistors are ON. They are conceptually removed from the circuit,

leaving a simple inverter.

Tristate were once commonly used to allow multiple units to drive a common bus, aslong as exactly one unit is enabled at a time. If multiple units drive the bus, contentionoccurs and power is wasted. If no units drive the bus, it can float to an invalid logic levelthat causes the receivers to waste power. Moreover, it can be difficult to switch enablesignals at exactly the same time when they are distributed across a large chip. Delay between different enables switching can cause contention. Given these problems, multiplexers are now preferred over tristate busses.


Differential Inverter All of the that we hace examined so far is single ended;that is.they have single end input

and produces single output. Now an inverter that uses two differential inputs and produces two

differential outputs is as shown in figure,

Two n transistors have their sources commoned and fed by a constant current

source that in turn connected to ground

The drains of each n transistor are connected to resistor load that are connected to

the supply voltage.

Now we make some analysis, if the input voltage is applied ie., Vleft= VA= VRight then

each transistor has VGS=VA-VN, where VN is the voltage accrossthe constant current source. Thus

is IDS is same for both the MOSFET and also Vout1=Vout2 .

Now increase the Vleft and VRight equally,then VN also rises to maintain the constant

current through the current source. The ouput voltages Vout1 and Vout2 will stay at same value.


Applying common signal to both the inputs therefore results no gain(ideally). This gain is

reffered as Common mode gain.

Now Vleft is increased by right is decreased by ,then current in N1 increases

by and Vout1 decreases by out2 increases by

Thus is the differential gain from Vleft to Vout

gm is / V transconductance of the driver transistor

Vout1=VDD- (Isource *Rload)/2

BIPOLAR DEVICES

1. DIODE

2. BJT

3. BiCMOS


BiCMOS Inverter

BiCMOS Inverter Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement- type devices)

The MOS switches perform the logic function & bipolar transistors drive output loads Vin = 0 :

T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to VDD - VBE (of T4)

Note: VBE (of T4) is base-emitter voltage of T4. (Pull-up bipolar transistor turns off as the output approaches 5V - VBE (of T4))

Vin = VDD : T2 is off. Therefore T4 is non-conducting. T1 is on and supplies current to the base of T3 T3 conducts & acts as a current sink to discharge load CL towards 0V. Vout falls to 0V+ VCEsat (of T3) Note: VCEsat (of T3) is saturation Voltage from T3 collector to emitter


T3 & T4 present low impedances when turned on into saturation & load CL will be

charged or discharged rapidly

Output logic levels will be good & will be close to rail voltages since VCEsat is quite

small & VBE 0.7V. Therefore, inverter has high noise margins

Inverter has high input impedance, i.e., MOS gate input

Inverter has low output impedance

Inverter has high drive capability but occupies a relatively small area

However, this is not a good arrangement to implement since no discharge path exists for

current from the base of either bipolar transistor when it is being turned off, i.e.,

when Vin=Vdd,T2 is off and no conducting path to the base of T4 exists

when Vin=0, T1 is off and no conducting path to the base of T3 exists

This will slow down the action of the circuit

The impedances Z1 and Z2 are necessary to remove the base charge of the bipolar

transistors when they are being turned off. For instance, during a high-to-low transition

on the input, T2 turns off first. To turn off T4, its base charge has to be removed. This

happens through Z1. Adding these resistors not only reduces the transition times, but also

has a positive effect on the power consumption. There exists a short period during the

transition when both T3 and T4 are on simultaneously, thus creating a temporary current

path between VDD and GND. The resulting current spike can be large and has a

detrimental effect on both the power consumption and the supply noise. Therefore,

turning off the devices as fast as possible is of utmost importance.

The conventional BiCMOS Inverter Two additional enhancement-type nMOS devices have been added (T5 and T6). These transistors provide discharge paths for transistor base currents during turn-off.

Without T5, the output low voltage cannot fall below the base to emitter voltage VBE of T3.

Vin = 0 : T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T5 is turned on & clamps base of T3 to GND. T3 is turned off.


T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to Vdd - Vbe (of T4) Vin = Vdd : T2 is off T1 is on and supplies current to the base of T3 T6 is turned on and clamps the base of T4 to GND. T4 is turned off. T3 conducts & acts as a current sink to discharge load CL towards 0V Vout falls to 0V+ VCEsat (of T3)

Again, this BiCMOS gate does not swing rail to rail. Hence some finite power is dissipated when driving another CMOS or BiCMOS gate. The leakage component of power dissipation can be reduced by varying the BiCMOS device parameters

Advantage:

BiCMOS devices offer many advantages where high load current sinking and sourcing

is required. The high current gain of the NPN transistor greatly improves the output

drive capability of a conventional CMOS device.

It follows that BiCMOS technology goes some way towards combining the virtues of

both CMOS and Bipolar technologies.


Design uses CMOS gates along with bipolar totem-pole stage where driving of high

capacitance loads is required.

Improved speed over purely-CMOS technology

Lower power dissipation than purely-bipolar technology (simplifying packaging and

board requirements)

Flexible I/Os (i.e., TTL, CMOS or ECL) –

BiCMOS technology is well suited for I/O intensive applications.

ECL, TTL and CMOS input and output levels can easily be generated with no speed or

tracking consequences.

Large circuits can impose severe performance penalties due to simultaneously switching

noise, internal clock skews and high nodal capacitances in critical paths - BiCMOS

has demonstrated superiority over CMOS in all of these factors.

High performance analogue

Latchup immunity

Main disadvantage:

Greater process complexity compared to CMOS

Results in a 1.25 1.4 times increase in die costs over conventional CMOS.

Taking into account packaging costs, the total manufacturing costs of supplying a

BiCMOS chip ranges from 1.1 1.3 times that of CMOS.


CMOS Processing Technology

CMOS processing steps can be broadly divided into two parts. Transistors are formed in

the Front-End-of-Line (FEOL) phase, while wires are built in the Back-End-of-Line (BEOL)

phase. This section examines the steps used through both phases of the manufacturing process.

Wafer Formation The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm to 300

mm in diameter and less than 1 mm thick. Wafers are cut from boules, cylindrical ingots of

single-crystal silicon that have been pulled from a crucible of pure molten silicon. This is known

as the Czochralski method and is currently the most common method for producing single-

crystal material.

Photolithography

The regions of dopants, polysilicon, metal, and contacts are defined using masks. For

instance, in places covered by the mask, ion implantation might not occur or the dielectric or

metal layer might be left intact. In areas where the mask is absent, the implantation can occur, or


dielectric or metal could be etched away. The patterning is achieved by a process called

photolithography

The primary method for defining areas of interest (i.e., where we want material to be

present or absent) on a wafer is by the use of photoresists. The wafer is coated with the

Photoresist and subjected to selective illumination through the photomask. A photomask is

constructed with chromium (chrome) covered quartz glass. A UV light source is used to expose

the Photoresist. Below Figure illustrates the lithography process.

The photomask has chrome where light should be blocked. The UV light floods the mask from

the backside and passes through the clear sections of the mask to expose the organic Photoresist

(PR) that has been coated on the wafer. A developer solvent is then used to dissolve the soluble

exposed or unexposed Photoresist

Silicon Dioxide (SiO2) Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere.

The following are some common approaches:

Wet oxidation––when the oxidizing atmosphere contains water vapor. The temperature is

usually between 900 °C and 1000 °C. This is also called pyrogenic oxidation when a 2:1

mixture of hydrogen and oxygen is used. Wet oxidation is a rapid process.

Si+2H2O SiO2+2H2

Dry oxidation––when the oxidizing atmosphere is pure oxygen. Temperatures are in the

region of 1200 °C to achieve an acceptable growth rate. Dry oxidation forms a better

quality oxide than wet oxidation. It is used to form thin, highly controlled gate oxides,

while wet oxidation may be used to form thick field oxides.


Si+O2 SiO2 CMOS TECHNOLOGIES

CMOS provides an inherently low power static circuit technology that has the capability

of providing a lower-delay product than comparable design-rule nMOS or pMOS technologies.

The four dominant CMOS technologies are:

n-well process

P-well process

twin-tub process

Silicon on Insulator process

The n-well process

A common approach to n-well CMOS fabrication is to start with moderately doped p-type substrate (wafer), create the n-type well for the p-channel devices, and build the n-channel transistor in the native p-substrate. The processing steps are,

Note: (Here I have not mentioned or drawn any Mask layer during this processing but in exam you have to mention)

Step1:

Process starts with a moderately doped (1015 cm-3) p-type substrate (wafer) An initial oxide layer is grown on the entire surface (barrier oxide)

Step2:

N-Well mask - defines the n-Well regions • Pattern the oxide • Implant n-type impurity atoms (phosphorus) - 1016cm-3 • Drive-in the impurities (vertical but also lateral redistribution - limits the density )

Field Oxide


Step3: • Active area mask - define the regions in which MOS devices will be created • LOCOS process to isolate NMOS and PMOS transistors • Grow gate oxide (dry oxidation) - only in the open area of active region

Step4:

• Polysilicon mask - define the gates of the MOS transistors • Polysilicon is deposited over the entire wafer (CVD process) and doped (typically n-type) • Pattern the polysilicon in the dry (plasma) etching process • Etch the gate oxide

Step5:

Thin oxide of 500Å

Mask


• n-Select mask - define the n+ source/drain regions of NMOS transistors • Define an ohmic contact to the n-well • Implant n-type impurity atoms (arsenic) • Polysilicon layer protects transistor channel regions from the arsenic dopant

Step6: • Complement of the n-select mask - define the p+ source/drain regions of PMOS

transistors • Define the ohmic contacts to the substrate • Implant p-type impurity atoms (boron) • Polisilicon layer protects transistor channel regions from the boron dopant

Step7:

• In the n-well two p+ and one n+ regions are created • After source/drain implantation a short thermal process is performed (annealing): • moderate temperature • drive the impurities deeper into the substrate • repair some of the crystal structure damage • lateral diffusion under the gate: overlap capacitances • Next the SiO2 insulated layer is deposited over the entire wafer area using a CVD

technique • The surface becomes nonplanar: impact on the metal deposition step


Step8:

• Contact mask - define the contact cuts in the insulating layer • Contacts to polysilicon must be made outside the gate region (avoid metal spikes

throughthe poly and the thin gate oxide)

Step9:

• Metallization mask - define the interconnection pattern • Aluminum is deposited over the entire wafer (evaporation) and selectively etched • The step coverage in this process is most critical (nonplanarity of the wafer surface) •

The P-well process


The twin-tub process:

Twin-tub CMOS technology provides the basis for separate optimization of the p-type

and n-type transistors, thus making it possible for threshold voltage, body effect, and the gain

associated with n-and p-devices to be independently optimized. Generally the starting material is

either an n+ or p+ substrate with a lightly doped epitaxial or epi layer, which is used for

protection against latch-up. The aim of epitaxy is to grow high purity silicon layers of controlled

thickness with accurately determined dopant concentrations distributed homogeneously

throughout the layer. The electrical properties for this layer are determined by the dopant and its

concentration in the silicon. The process sequence, which is similar to the p-well process apart

from the tub formation where both p-well and n-well are utilized.

The following steps

Tub formation

Thin oxide etching

Source and drain implantations


Contact cut definition

Metallization.

Since this process provides separately optimized wells, better performance n-transistors

(lower capacitance, less body effect) may be constructed when compared with a

conventional p-well process. Similarly the p-transistors may be optimized. The use of

threshold adjust steps is included in this process.

Flow diagram of twin-tub process


Silicon on insulator process: Silicon on insulator (SOI) CMOS processes has several potential advantages such as

higher density, no latch-up problems, and lower parasitic capacitances. In the SOI process a thin layer of single crystal silicon film is epitaxial grown on an insulator such as sapphire or magnesium aluminate spinel. The steps involves are:

1) A thin film (7-8 μm) of very lightly doped n-type Si is grown over an insulator. Sapphire is a

commonly used insulator.

2) An anisotropic etch is used to etch away the Si except where a diffusion area will be needed.

3) The p-islands are formed next by masking the n-islands with a photoresist. A p-type dopant (boron) is then implanted. It is masked by the photoresist and at the unmasked islands. The p-islands will become the n-channel devices.

4) The p-islands are then covered with a photoresist and an n-type dopant, phosphorus, is implanted to form the n-islands. The n-islands will become the p-channel devices.

5) A thin gate oxide (500-600Å) is grown over all of the Si structures. This is normally done by thermal oxidation.

6) A polysilicon film is deposited over the oxide.

7) The polysilicon is then patterned by photomasking and is etched. This defines the polysilicon layer in the structure.

8) The next step is to form the n-doped source and drain of the n-channel devices in the p-islands. The n-island is covered with a photoresist and an n-type dopant (phosphorus) is implanted.

9) The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant. The polysilicon over the gate of the n-islands will block the dopant from the gate, thus forming the p-channel devices

10) A layer of phosphorus glass is deposited over the entire structure. The glass is etched at

contact cut locations. The metallization layer is formed. A final passivation layer of a phosphorus glass is deposited and etched over bonding pad locations.

The advantages of SOI technology are:


Due to the absence of wells, denser structures than bulk silicon can be obtained.

Low capacitances provide the basis of very fast circuits.

No field-inversion problems exist.

No latch-up due to isolation of n- and p- transistors by insulating substrate.

As there is no conducting substrate; there are no body effect problems

Enhanced radiation tolerance.

But the drawback is due to absence of substrate diodes, the inputs are difficult to protect. As

device gains are lower, I/O structures have to be larger. Single crystal sapphires are more

expensive than silicon and processing techniques tend to be less developed than bulk silicon

techniques.


CMOS Process Enhancements Note:(In this topic just know this and if question asked in exam just head lines are enough)

a) Using Multiple Threshold Voltages and Oxide Thicknesses

b) Silicon on Insulator (SOI)

c) Using High-k Gate Dielectrics MOS transistors need high gate capacitance to attract charge to the channel. This leads to

very thin SiO2 gate dielectrics (e.g., 10.5–12 Å, merely four atomic layers, in a 65 nm

process)

Gate leakage increases unacceptably below these thicknesses, which brings an end to

classical scaling

Simple SiO2 has a dielectric constant of k = 3.9, so gates could use thicker dielectrics and

hence leak less if a material with a higher dielectric constant are available

Example, Hafnium oxide (HfO2) has k 20.

d) Using Higher Mobility Increasing the mobility (u) of the semiconductor improves drive current and

transistor speed. One way to improve the mobility is to introduce mechanical strain

in the channel. This is called strained silicon.

e) Using Plastic Transistors MOS transistors can be fabricated with organic chemicals. These transistors show

promise in active matrix displays, flexible electronic paper, and radio-frequency ID

tags because the devices can be manufactured from an inexpensive chemical

solution.

f) Using High-Voltage Transistors

High-voltage MOSFETs can also be integrated onto conventional CMOS processes

for switching and high-power applications. Gate oxide thickness and channel length

have to be larger than usual to prevent breakdown.

g) Interconnect

Interconnect has advanced rapidly. While two or three metal layers were once the

norm, CMP has enabled inexpensive processes to include seven or more layers.

Copper metal and low-k dielectrics are almost universal to reduce the resistance and

capacitance of these wires.


i. Copper Damascene Process While aluminum was long the interconnect metal of

choice; copper has largely superseded it in nanometer processes. This is primarily due

to the higher conductivity of copper compared to aluminum.

Copper atoms diffuse into the silicon and dielectrics, destroying transistors.

The processing required to etch copper wires is tricky.

Copper oxide forms readily and interferes with good contacts.

Care has to be taken not to introduce copper into the environment as a pollutant.

Barrier layers have to be used to prevent the copper from entering the silicon

surface. A new metallization procedure called the damascene process was invented

to form this barrier.

ii. Low-k Dielectrics SiO2 has a dielectric constant of k = 3.9–4.2. Low-k dielectrics

between wires are attractive because they decrease the wire capacitance. This reduces

wire delay, noise, and power consumption.

LAYOUT DESIGN RULES Design rules include width rules and spacing rules. Mead and Conway developed a set of

simplified scalable λ -based design rules, which are valid for a range of fabrication technologies.

In these rules, the minimum feature size of a technology is characterized as 2 λ. All width and

spacing rules are specified in terms of the parameter λ. suppose we have design rules that call for

a minimum width of 2λ, and a minimum spacing of 3λ. If we select a 2 um technology (i.e., λ= 1

um), the above rules are translated to a minimum width of 2 um and a minimum spacing of 3 um.

On the other hand, if a 1 um technology (i.e., λ= 0.5 um) is selected, then the same width and

spacing rules are now specified as 1 um and 1.5 um, respectively.

LAMBDA RULE (λ=1um)

LAYER TYPE OF RULE VALUE

POLY Minimum Spacing 2λ

Minimum Width 2λ

ACTIVE Minimum Spacing 3λ

Minimum Width 3λ


NSELECT/

PSELECT Minimum Spacing 3λ

Minimum Width 3λ

METAL1 Minimum Spacing 3λ

Minimum Width 3λ

i. POLY

Minimum Spacing 2λ

Minimum Width 2λ

2λ 2λ

2λ

ii. ACTIVE

Minimum Spacing 3λ

Minimum Width 3λ

iii. METAL1

Minimum Spacing 3λ

Minimum Width 3λ


3λ 3λ

3λ

iv. NWELL

Minimum Spacing 6λ

Minimum Width 10λ

Minimum Spacing between different layers

i. POLY to ACTIVE 1λ


Butting contact: The layers are butted together in such a way the two contact cuts become

contiguous. Metallization is used to establish the contact between poly and diffusion. We can

better under the butting contact from figure

Poly

Metal1

Buried contact: The contact cut is made down each layer to be joined and it is shown in figure


MOSFET LAYOUT RULES RULE Meaning VALUE

POLY Overlap Minimum Extension over ACTIVE 2λ

POLY-ACTIVE Minimum Spacing 1λ

MOSFET Width Minimum N+/P+ MOSFET (W) 3λ

ACTIVE CONTACT Exact Size

Minimum Space to Active Edge

2λ x 2λ

2λ

POLY CONTACT Exact Size

Minimum Space to Active Edge

2λ x 2λ

2λ


SCHEMATIC AND LAYOUT OF BASIC GATES using CMOS Logic (Note: Here I have not consider any design Rule while drawing Layout and also I left

out Bulk/Body terminal in Layout) 1. INVERTER


2.


Implement the following using CMOS logic with minimum number of transistor and also draw Layout

3.

4. 5. 2- INPUT NAND 6. 2- INPUT NOR


Latch up in Bulk CMOS

A byproduct of the Bulk CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to the base of the other transistor in a positive feedback structure. A phenomenon called latch up

It can occur when

(1) Both BJT's conduct, creating a low resistance path between VDD and GND

(2) The product of the gains of the two transistors in the feedback loop, beta1 x beta2, is greater than one.

The result of latch up is at the minimum a circuit malfunction, and in the worst case, the destruction of the device.

Cross section of parasitic transistors in Bulk CMOS


Latch up may begin when Vout drops below GND due to a noise spike or an improper circuit

hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn

on Q2 (I Rsub > 0.7 V), this will draw current through Rwell. If the voltage drop across Rwell is

high enough, Q1 will also turn on, and a self-sustaining low resistance path between the power

rails is formed. If the gains are such that beta1 x beta2 > 1, latch up may occur. Once latch up has

begun, the only way to stop it is to reduce the current below a critical level, usually by removing

power from the circuit.

The most likely place for latch up to occur is in pad drivers, where large voltage transients and

large currents are present.

Preventing latch up(Fab/Design Approaches)

1. Reduce the gain product beta1 x beta2

o move n-well and n+ source/drain farther apart increases width of the base of Q2

and reduces gain beta2 also reduces circuit density

o buried n+ layer in well reduces gain beta1 of Q1

2. Reduce the well and substrate resistances, producing lower voltage drops

o higher substrate doping level reduces Rsub

o reduce Rwell by making low resistance contact to GND

o Guard rings around p and/or n-well, with frequent contacts to the rings, reduces

the parasitic resistances.


Technology related CAD issues

The mask database is the interface between the semiconductor manufacturer and the chip

designer. Two basic checks have to be completed to ensure that this description can be turned

into a working chip.

First, the specified geometric design rules must be obeyed.

Second, the interrelationship of the masks must, upon passing through the

manufacturing process, produce the correct interconnected set of circuit elements.

To check these two requirements, two basic CAD tools are required: a Design

Rule Check (DRC) program and a mask circuit extraction program.

a. Design Rule Checking (DRC)

Although we can design the physical layout in a certain set of mask layers, the actual

masks used in fabrication can be derived from the original specification. Similarly, when we

want a program to determine what we have designed by examining the interrelationship of the

various mask layers, it may be necessary to determine various logical combinations between

masks.

b. Circuit Extraction

Now imagine that we want to determine the electrical connectivity of a mask database..

An output statement might then be used to output the extracted transistors in some netlist format.

The extracted netlist is often used to compare the layout against the intended schematic, Pre

versus Post.

BASIC CIRCUIT DESIGN CONCEPTS

We have already seen that MOS structures are formed by the super imposition of a

number conducting, insulating and transistor forming material. Now each of these layers has

their own characteristics like capacitance and resistances. These fundamental components are

required to estimate the performance of the system. These layers also have inductance

characteristics that are important for I/O behavior but are usually neglected for on chip devices.


The issues of prominence are

1. Resistance, capacitance and inductance calculations.

2. Delay estimations

3. Determination of conductor size for power and clock distribution

4. Power consumption

5. Charge sharing

6. Design margin

7. Reliability

8. Yield

RESISTANCE ESTIMATION

Integrated Circuit (IC) chips contain many types of materials such as polysilicon, oxide,

various diffusions of basic CMOS transistors, and metal. A popular resistor material is

polysilicon, also known as poly.

The concept of sheet resistance is being used to know the resistive behavior of the layers

that go into formation of the MOS device. Let us consider a uniform slab of conducting material

of the following characteristics.


R - Resistance (ohms)

L - Length

W -width

-sheet resistivity (ohms-per-square)

We know that the resistance is given by RAB= L/A. The area of the slab considered above is given by A=Wt.

RAB= L/Wt. If the slab is considered as a square then L=W. therefore RAB=/t which is called as sheet

resistance represented by Rs.The unit of sheet resistance is ohm per square. It is to be noted that Rs is independent of the area of the slab. Hence we can conclude

that a 1um per side square has the same resistance as that of 1cm per side square of the same material.

SHEET RESISTANCE OF MOS TRANSISTORS

2λ

2λ

The N transistor above is formed by a 2λ wide poly and 2λ n+ diffusion.

The L/W ratio is 1. Hence the transistor is a square,

Therefore the resistance R is 1sqxRs ohm/sq i.e. R=1x104.

If L/W ratio is 4 then R = 4x104.


If it is a P transistor then for L/W =1, the value of R is 2.5x104.

CAPACITANCE ESTIMATION

Parasitics capacitances are associated with the MOS device due to different layers that go

into its formation. Interconnection capacitance can also be formed by the metal, diffusion and

polysilicon in addition with the transistor and conductor resistance. All these capacitances

actually define the switching speed of the MOS device.

Understanding the source of parasitics and their variation becomes a very essential part of

the design specially when system performance is measured in terms of the speed. The various

capacitances that are associated with the CMOS device are

1) Gate capacitance - due to other inputs connected to output of the device

2) Diffusion capacitance - Drain regions connected to the output

3) Routing capacitance- due to connections between output and other inputs

MOS Device Capacitance

The gate to channel capacitance formed due to the sio2 separation is the most profound of the

mentioned three types. It is directly connected to the input and the output. The other capacitance

like the metal, poly can be evaluated against the substrate. The gate capacitance is therefore

standardized so as to enable to move from one technology to the other conveniently.

The standard unit is denoted by Cg. It represents the capacitance between gate to channel with

W=L=min feature size. Here is a figure showing the different capacitances that add up to give

the total gate capacitance

Cgd, Cgs = gate to channel capacitance lumped at the source and drain

Csb, Cdb = source and drain diffusion capacitance to substrate


Cgb = gate to bulk capacitance

Total gate capacitance Cg = Cgd+Cgs+Cgb

Parameter Off Active Saturation

C gb Ɛo At ox

0 0

C gs 0 Ɛo A2 t ox

2Ɛo A3 t ox

C gd 0 Ɛo A2 t ox 0

Ct= C gb+ C gs+ C gd Ɛo At ox

Ɛo At ox

2Ɛo A3 t ox

Area Capacitances of Layers

The fabrication process illustrates that the conducting layers are apparently separated from the

substrate and other layers by the insulating layer leading to the formation of parallel capacitors.

Since the silicon dioxide is the insulator knowing its thickness we can calculate the capacitance.

C=Ɛ

Ɛo= permittivity of free space-8.854x1014f/cm


ins= relative permittivity of sio2=4.0

D= thickness of the dioxide in cm

A = area of the plate in cm2

Standard unit of Capacitance Cg

It is convenient to employ a standard unit of capacitance that can be given a value

appropriate to the technology but can also be used in calculations without associating it with an

absolute value. the unit is denoted Cg and is defined the gate-to-channel capacitance of a MOS

transistor having W=L=feature size, that is ,a ‘standard or ‘feature size’ of square.

Since the standard gate capacitance has been defined, the other capacitances like

polysilicon, metal, diffusion can be expressed in terms of the same standard units so that the total

capacitance can be obtained by simply adding all the values. In order to express in standard

values the following steps must be followed,

1. Calculate the areas of area under consideration relative to that of standard gate i.e.4. (Standard

gate varies according to the technology)

2. Multiply the obtained area by relative capacitance values tabulated.

3. This gives the value of the capacitance in the standard unit of capacitance Cg

4. Ratio= Relative area=

5. Capacitance = Relative area of Selected layer X Relative Capacitance of Selected layer

Problems

I. A particular layer of MOS circuit has a resistivity of 1 ohm -cm. The section is 55um long, 5um wide and

1 um thick. Calculate the resistance and also find Rs Solution:

R= RsxL/W,

Rs= /t

Rs=1x10-2/1x106=104ohm R= 104x55x10-6/5x106=110k


II. For a 5u technology the area of the minimum sized transistor is 5uX5u=25um2 i.e. λ=2.5u,

hence, area of minimum sized transistor in lambda is 2λX2λ= 4λ2. Therefore for 2u or 1.2u

or any other technology the area of a minimum sized transistor in lambda is 4λ2

Solution:

The figure above shows the dimensions and the interaction of different layers, for evaluating the total capacitance resulting so.

Three capacitance to be evaluated

Metal Cm, polysilicon Cp and gate capacitance Cg

Metal

Area of metal = 100λx3λ=300λ 2


Area of minimum sized transistor in lambda is 2λX2λ= 4λ2.

Ratio= Relative area= 퐌퐞퐭퐚퐥 퐀퐫퐞퐚 (퐒퐞퐥퐞퐜퐭퐞퐝 퐋퐚퐲퐞퐫)퐒퐭퐚퐧퐝퐚퐫퐝 퐆퐚퐭퐞 퐀퐫퐞퐚

Relative area =300λ 2 /4λ2=75

Metal Capacitance = Relative area of Selected layer (i.e. Meta) X Relative Capacitance of metal Relative Capacitance of metal from table=0.075 Cm= 75 x0.075=5.625 Polysilicon

Area of Polysilicon= (4λx4λ+1λx2λ+2λX2λ)(excluding Gate region) =22λ2

Relative area =22λ 2 /4λ2=5.5

Cp=5.5x0.1=0.55

Gate Area of Gate=2λX2λ= 4λ2 Relative area =4λ2 /4λ2=1(because it is a standard min size gate) Cg=1x1=1 Total capacitance Ct=Cm+Cp+Cg=5.625+0.55+1=7.2

Switching Characteristics

Charging and Discharging The delay of the CMOS inverter is a performance metric for how fast the circuit is. This

delay is dependent upon the RC charging or discharging of the load capacitor by the pMOS or nMOS devices respectively and provides a quantitative feel for the time that is taken by the output of the inverter to completely respond to a change at its input.

Rise time estimation: In this analysis we assume that the p-device stays in saturation for entire charging period of load capacitor CL. The circuit may then be modeled as shown in below figure,


The saturation current for P-transistor is given by

Idsp= 훃퐩(퐯퐠퐬 |퐯퐭퐩|)ퟐ

ퟐ

This current charges CL and since its magnitude is approximately constant we have

Vout=푰풅풔풑∗풕푪푳

Substituting for Idsp and rearranging we have

t= ퟐ푪푳푽풐풖풕휷풑(푽품풔 푽풕풑 )ퟐ

We now assume that t=tr when vout=+VDD and |Vtp|=20%VDD=0.2VDD

After simplifying we get

tr=ퟑ푪푳

휷풑푽푫푫

This results compares reasonably well with a more detailed analysis in which the charging of

CL is divided, more correctly, into two parts(1) saturation and (2) Resistive region of transistor.


Fall time

Similar reasoning can be applied to the discharge of CL through n-transistor.the circuit model in

this case is given as shown in below figure

Making similar assumption we may write for fall time:

tf=ퟑ푪푳

휷풑푽푫푫

Delay Time:

In MOS circuits, the delay of a single Gate is dominated by the output rise and fall time, the delay is approximately given by tdr= tr/2

tdf= tf/2

The average gate delay for rising edge and falling transitions is given by tav=(tdr+tdf)/2 (tr+tf)/4


Gate Transistor Sizing Size the following logic with respect to INVERTER Gate Size

1.


2. 3.


4. Size the transistor for the function out=AB+(C+D)E with reference to inverter i.e., Wp= Wn

5. Repeat the above function for Wp=3* Wn


Pair delay of cascaded Inverter

Case a :Symmetrical inverter design

– P mobility = ½ x N mobility – Wp = 2 x Wn – Input gate capacitance = 3 x Ceq, where Ceq is the pull-down device gate capac.

Pair delay = tfall + trise = R*3Ceq + 2(R/2)*3Ceq

= 6RCeq

Case b: Non-symmetrical inverter design

• Wp = Wn • Input gate capacitance = 2 x Ceq

Pair delay = tfall + trise = R*2Ceq + 2R*2Ceq = 6RCeq

• In the simple case where the load is comprised mainly of input gate capacitance no impact to the total delay of the pair of inverters was observed by using non-symmetrical Wn=Wp


Power Consumption:

There are 2 components which that establish the amount of power dissipated in the CMOS

circuit. These are

i. Static Power Dissipation – due to leakage current

ii. Dynamic Power Dissipation—

a) Switching transient Current

b) Charging and Discharging of Capacitor.

i. Static Power Dissipation

Consider CMOS gate as shown in figure,

when vin=0, n-MOS is OFF, and p-MOS is ON and vout=1

when vin=1, n-MOS is ON, and p-MOS is OFF and vout=0

Here any one of the transistor will be OFF always, since no current flows into gate terminal

and hence no DC current path between VDD and VSS , so Static Power (Ps) is zero.


However, there is some small static dissipation due to reverse bias leakage between

diffusion regions and the substrate. We need to look at a simple model that describes the

parasitic diodes for a CMOS inverter in order to have an understanding of the leakage involved

in the device. The source-drain diffusion and the p-well diffusion form parasitic diode. This can

be represented in the profile of an inverter shown in fig. In the model, diode D1 is a parasitic

diode between p-well to substrate. Since parasitic diodes are reversed biased, only their leakage

current contributes to static power dissipation. The leakage current is described by the diode

equation

IO=IS(푒 )

Where IO reverse saturation current

Q electronic charge

V diode voltage

K Boltzmann constant

T temperature

The static power dissipation is the product of the device leakage current and the supply voltage.

Total static power dissipation p is obtained from

Ps= ∑ (퐥퐞퐚퐤퐚퐠퐞 퐜퐮퐫퐫퐞퐧퐭 ∗ 퐒퐮퐩퐩퐥퐲 퐯퐨퐥퐭퐚퐠퐞)퐍ퟏ

Where N is number of devices


Dynamic dissipation

During transition from either ‘0’ to ‘1’ or alternatively from ‘1’ to ‘0’, both n- and p-transistors are on for a short period of time .This results in a short current pulse from VDD to VSS current is also required to charge and discharge the output capacitive load. This latter term is generally the dominant term. The current pulse from VDD to VSS results in a “short-circuit” dissipation which is dependent on the load capacitance and gate design. This is of relevance to I/O buffer design.

The dynamic dissipation can be modeled by assuming the rise and fall time of the step input is much less than the repetition period. The average dynamic power, PD, dissipated during switching for a square-wave input vin, having a repetition frequency of fp=1/tp as shown by fig

Thus for a repetitive step input the average power that is dissipated is proportional to the energy required to change and discharge the circuit capacitance .the important factor to be noted here is that shows power to be proportional to switching frequency but independent of the device parameters.


For a step input and with in(t)=CL dVo/dt

Total power dissipation can be obtained from the sum of the two dissipation components, so

Ptotal=Ps+Pd

When calculating the power dissipation a rule of thumb is to add all capacitance operating at

particular frequency and calculate the power. Then the power from other groups operating at

different frequencies may be summed, the dynamic power dissipation may be used to estimate

total power consumption of a circuit and also the size of VDD and VSS conductors to minimize

transient induced voltage drops.

Charge sharing:

In many structures a bus can be modeled as a capacitors Cb as shown in fig. Sometimes the

voltage on this bus is sampled to determine the state of a given signal frequency, this sampling

can be modeled by the two capacitors Cs and Cb and a switch. In general Cs is in some way

related to the switching element. The charge associated with each of the capacitance prior to

closing the switch can be described by

• At time t=0-, switch is open and each capacitor contains some initial charge

• At time t=0+, the switch is closed and the charge redistributes across both capacitors

• Conserve the total charge:

– Sum up initial charge Qt = Qb + Qs = CbVb + CsVs


– Total capacitance Ct= Cb + Cs

– When switch is closed the resultant voltage VR=Qt/Ct

– Therefore, VR = (CbVb + CsVs)/(Cb + Cs)

• If Vb = VDD and Vs = 0, then

VR= VDD Cb/(Cb + Cs) (which is similar to the equation for a resistor divider)

Design Margin:

As semiconductor technology scales to the nanometer regime, the variation of process

parameters is a critical problem in VLSI design. Thus the need for variation-aware timing

analysis for the performance yield is increasing. However, the traditional worst-case corner-

based approach gives pessimistic results, and makes meeting given designs specifications

difficult. As an alternative to this approach, statistical analysis is proposed as a new and

promising variation-aware analysis technique. However, statistical design flow cannot be applied

easily to existing design flow, and not enough tools for statistical design exist. To overcome

these problems, new design methodology based on traditional static timing analysis (STA) using

a relaxed corner proposed

Yield

An important issue in the manufacture of VLSI structure is yield, although yield is not a

performance parameter, it is influenced by such factors are

Technology

Chip area


Layout

Yield is defined as a ratio of

Y=

x 100%

And may be described as a function of chip area and defect density.

Two common equations used are,

1) Seed’s Model which is given by

Y=푒 √ Where A is chip area

D is defect density

This model is used for large chips and for yields less than 30%

2) Murphy’s Model, which is described by

Y= ( )

Where A is chip area

D is defect density

This model is used for small chips and for yields greater than 30% from these relations it

is obvious that yield decreases dramatically as the area of the chip increases.


Unit -3

Scaling of MOS Circuits

What is scaling?

Proportional adjustment of the dimensions of an electronic device while maintaining the

electrical properties of the device, results in a device either larger or smaller than the un-scaled

device.

.

Technology Scaling

Goals of scaling the dimensions by 30%:

Reduce gate delay by 30% (increase operating frequency by 43%)

Double transistor density

Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)

Die size used to increase by 14% per generation

Technology generation spans 2-3 years

International Technology Roadmap for Semiconductors (ITRS)


Scaling Models

1. Full Scaling (Constant Electrical Field)

Ideal model – dimensions and voltage scale together by the same scale factor

2. Fixed Voltage Scaling

Most common model until recently – only the dimensions scale, voltages remain

constant

3. General Scaling

Most realistic for today’s situation – voltages and dimensions scale with different

factors

Scaling Factors for Device Parameters

Device scaling modeled in terms of generic scaling factors:

1/α and 1/β

• 1/β: scaling factor for supply voltage VDD and gate oxide thickness D

• 1/α: linear dimensions both horizontal and vertical dimensions

Why is the scaling factor for gate oxide thickness different from other linear horizontal and

vertical dimensions? Consider the cross section of the device as in Figure, various parameters

derived are as follows.

Gate -Poly


1 Gate Length L L/α

2 Gate Channel Width W W/α

3 Gate Thickness t t/α

4 Gate Oxide Thickness D D/β

5. Supply Voltage VDD VDD/β

1. Gate area Ag

Ag= L* W

Where L: Channel length scaled by 1/α and W: Channel width and both are scaled by 1/α Thus Ag is scaled up by 1/α2

2. Gate capacitance per unit area Co or Cox

Cox = 표푥

Where

εox is permittivity of gate oxide (thin-ox)= εins* εo constant and

D is the gate oxide thickness scaled by 1/β

Thus Cox is scaled up by

Co =Cox = ퟏ(ퟏ휷)

=β

3. Gate capacitance Cg= oxide capacitance * Gate Area

Cg= Co* Ag= Co *(LW)

Thus Cg is scaled up by β* 1/ α2 =β/ α2


4. Parasitic capacitance Cx Cx is proportional to Ax/d

Where d is the depletion width around source or drain and scaled by 1/ α

Ax is the area of the depletion region around source or drain, scaled by (1/ α2). Thus Cx is scaled up by {1/(1/α)}* (1/ α2 ) =1/ α

5. Carrier density in channel Qon

Qon = Co * Vgs Where Qon is the average charge per unit area in the ‘on’ state.

Co is scaled by β and

Vgs is scaled by 1/ β.

Thus Qon is scaled by 1

6. Channel Resistance Ron

Ron = 푳푾

*ퟏ∗

Where μ= channel carrier mobility and assumed constant

Thus Ron is scaled by 1.

7. Gate delay Td Td is proportional to Ron*Cg

Td is scaled by 1* β/ α2 = β/ α2

8. Maximum operating frequency fo

fo= ∗

fo is inversely proportional to delay Td and is scaled by=ퟏ/훂ퟏ/훂

*((ퟏ∗훃∗ퟏ휷)

훃/ 훂ퟐ) = 훂ퟐ/훃

9. Saturation current IDSAT = 흁 푪풐풙 ∗ 푾

푳 *(푽품풔 − 푽풕풉)ퟐ

흁= channel carrier mobility and assumed constant

Cox is scaled by β


W and L are scaled by 1/α

Both Vgs and Vth are scaled by (1/ β)

Therefore, IDSAT is scaled by (β* ퟏ휷ퟐ

) =ퟏ휷

10. Current density J

Current density=푰푫푺풂풕푨

,

Where A is cross sectional area of the Channel=W* L= in the “on” state which is scaled by (1/α2).

Therefore, J is scaled by = (ퟏ훃)

( ퟏ훂ퟐ

) =휶ퟐ

휷

11. Switching energy per gate Eg

Eg= ퟏ

ퟐ VDD 2 Cg

VDD is scaled by ퟏ휷

Cg is scaled by β/ α2

Hence Eg is scaled by =ퟏ훃ퟐ∗ 훃훂ퟐ

= ퟏ훃훂ퟐ

12. Power dissipation per gate Pg Pg comprises of two components: static component Pgs and dynamic component Pgd:

Pg= Pgs+ Pgd

Where, the static power component is given by: Pgs=푽푫푫ퟐ

푹푶풏

Since VDD scales by (1/β) and Ron scales by 1, Pgs scales by (1/β2).

And the dynamic component by: Pgd= Eg * fo


Since Eg scales by ퟏ

훃훂ퟐ and

fo by 훂훃

Pgd also scales by ퟏ

훃훂ퟐ ∗.훂훃 =ퟏ훃ퟐ

Therefore, Pg scales byퟏ훃ퟐ

.

13. Power – speed product PT PT=Pg * Td

=ퟏ훃ퟐ

* 휷휶ퟐ

= ퟏ훃훂ퟐ

Device parameters for scaling models FULL SCALING for Constant E: β = α; CONSTANT VOLTAGE SCALINGfor Constant V: β =1


MERITS Implications of Scaling Improved Performance

Improved Cost

Interconnect Woes

Power Woes

Productivity Challenges

Physical Limits

Interconnect Woes Scaled transistors are steadily improving in delay, but scaled wires are holding

constant or getting worse. For short wires, such as those inside a logic gate, the wire RC delay is negligible. However, the long wires present a considerable challenge.


Productivity Challenges • Transistor count is increasing faster than designer productivity (gates / week) – Bigger design teams – More expensive design cost – Pressure to raise productivity • Rely on synthesis, IP blocks

– Need for good engineering managers

Physical Limits

• Will Moore’s Law run out of steam?

Yes, Can’t build transistors smaller than an atom…

Moore's Law Upheld

• Moore's law, first postulated by Intel co-founder Gordon Moore, says the number of transistors -- the main component of a microchip -- that can fit on a chip doubles about every 18-24 months.

• To keep pace with Moore's law, transistors would have to reach the atomic level by 2020. • The smallest transistor ever built has been created using a single phosphorous atom by an

international team of researchers at the University of New South Wales, Purdue

University and the University of Melbourne. "To me, this is the physical limit of Moore's

Law," Klimeck says. "We can't make it smaller than this (atom)."

Limitations of Scaling

Substrate doping

Depletion width

Limits of miniaturization

Limits of interconnect and contact resistance

Limits due to sub threshold currents

Limits on logic levels and supply voltage due to noise

Limits due to current density


Substrate doping

Built-in (junction) potential VB depends on substrate doping level – can be neglected as

long as VB is small compared to VDD.

As length of a MOS transistor is reduced, the depletion region width –scaled down to

prevent source and drain depletion region from meeting.

the depletion region width d for the junctions is

d= ퟐ퐪 ∗

훆퐬퐢퐍퐁

∗ 훆퐨 ∗ 퐕

εsi relative permittivity of silicon

ε0 permittivity of free space(8.85*10-14 F/cm)

V effective voltage across the junction Va + Vb

q Electron charge

NB doping level of substrate

Va maximum value Vdd-applied voltage

Vb built in potential and Vb =푲푻풒

ln푵푨푵푩풏풊ퟐ

For 5 μm Technology Vb=500mv while VDD=5v hence we must neglect Vb hence depletion

width

d= ퟐ퐪 ∗

훆퐬퐢퐍퐁

∗ 훆퐨 ∗ 퐕DD

For recent technologies NB is increased to reduce so that Vb is enlarged. At the same

time VDD is scaled down hence Vb is no longer smaller

Depletion width • NB is increased to reduce d, but this increases threshold voltage Vth –against trends for scaling

down.

• Maximum value of N B (1.3*1019 cm-3, at higher values, maximum electric field applied to gate

is insufficient and no channel is formed.


• N B maintained at satisfactory level in the channel region to reduce the above problem.

Limits of miniaturization • Minimum size of transistor; process tech and physics of the device

• Reduction of geometry; alignment accuracy and resolution

• Size of transistor measured in terms of channel length L

L=2d (to prevent push through)

• L determined by NB and VDD

• Minimum transit time for an electron to travel from source to drain is

Vdrift =μE

t= 푳퐕퐝퐫퐢퐟퐭

= ퟐ풅훍퐄

Limits of interconnect and contact resistance

• Short distance interconnect- conductor length is scaled by 1/α and resistance is increased by α

• For constant field scaling, I is scaled by 1/ α so that IR drop remains constant as a result of

scaling.-driving capability/noise margin.

The Propagation delay along single aluminum interconnect can be calculated as


TP= Rint* Cint+2.3(RON *Cint+RON*CL+ Rint* CL)

Limits due to subthreshold currents

• Major concern in scaling devices.

• I sub is directly proportional exp (Vgs – Vth) q/KT

• As voltages are scaled down, ratio of Vgs-Vth to KT will reduce-so that threshold current

increases.

• Therefore scaling Vgs and Vth together with Vdd.

• Maximum electric field across a depletion region is

Emax=2∗ (푽풂 푽풃풅

)

Limits on supply voltage due to noise

Decreased inter-feature spacing and greater switching speed –result in noise problems.

Observations – Device scaling

Gate capacitance per micron is nearly independent of process

But ON resistance * micron improves with process

Gates get faster with scaling (good)

Dynamic power goes down with scaling (good)

Current density goes up with scaling (bad)

Velocity saturation makes lateral scaling unsustainable

Observations – Interconnect scaling

Capacitance per micron is remaining constant

About 0.2 fF/mm

Roughly 1/10 of gate capacitance

Local wires are getting faster

Not quite tracking transistor improvement

But not a major problem

Global wires are getting slower

No longer possible to cross chip in one cycle


CMOS Circuit and Logic Design


CMOS COMPLEMENTARY LOGIC

CMOS structures require a nblock and a pblock for completion of the logic. That is for a n input logic 2n gates are required. Each logic function is duplicated for both pull-down and pull-up logic tree

– pull-down tree gives the zero entries of the truth table, i.e. implements the negative of the given function

– pull-up tree is the dual of the pull-down tree, i.e. implements the true logic with each input negative-going

Advantages: low power, high noise margins, design ease, functionality

Disadvantage:

high input capacitance reduces the ultimate performance For an N input logic 2N gates are required.


Implement following function using CMOS LOGIC

Number of transistor required= 2N, Here N=5, TOTAL=10 Transistor required to implement the function using Complementary CMOS logic


CMOS INVERTER CIRCUIT AND LAYOUT


CMOS 2-Input NAND with Layout


CMOS 2-Input NOR with Layout


PSEUDO – nMOS LOGIC

• This logic structure consists of the pull up circuit being replaced by a single pull up

PMOS whose gate is permanently grounded.

• This actually means that PMOS is all the time on and that now for a n input logic we

have only n+1 gates.

• This technology is equivalent to the depletion mode type and preceded the CMOS

technology and hence the name pseudo.

PSEUDO – nMOS LOGIC NAND GATE

• The two sections of the device are now called as load and driver.

• The ßn/ßp (ßdriver/ßload) has to be selected such that sufficient gain is achieved to get

consistent pull up and pull down levels.

• This involves having ratioed transistor sizes so that correct operation is obtained.

However if minimum size drivers are being used then the gain of the load has to be

reduced to get adequate noise margin.

(DRIVER)


OTHER VARIATIONS OF PSEUDO NMOS 1. Multi drain logic One way of implementing Pseudo NMOS is to use multidrain logic. It represents a

merged transistor kind of implementation. The gates are combined in an open drain

manner, which is useful in some automated circuits.

2. GANGED LOGIC The inputs are separately connected but the output is connected to a common terminal.

The logic depends on the pull up and pull down ratio. If PMOS is able to overcome

NMOS it behaves as NAND else NOR.

Example: NOR gate; Z = A+B+CCan be operated as NAND gate by suitably ratioing

PMOS over NMOS.


Implement following function using PSEUDO – nMOS LOGIC

Number of transistor required to implement PSEUDO – nMOS LOGIC = N+1

Here N=5

TOTAL=6 Transistor


ADVANTAGES

1. The gate capacitance of CMOS logic is two unit gate but for Psuedo logic it is only one gate unit.

2. Since number of transistors per input is reduced area is reduced drastically.

Drawbacks of the design

Since the PMOS is always on, static power dissipation occurs, whenever the NMOS is on. Hence the conclusion is that in order to use Psuedo logic a tradeoff between size & load or power dissipation has to be made.

DYNAMIC CMOS LOGIC

• This logic looks into enhancing the speed of the pull up device by Precharging the

output node to VDD.

• Hence we need to split the working of the device into

Precharge stage and

Evaluate stage for which we need a clock. Hence it is called as dynamic

logic


The output node is precharged to VDD by the PMOS and is discharged conditionally

through the NMOS. Alternatively you can also have a p block and precharge the n

transistor to VSS.

When the clock is low the precharge phase occurs

The pull up time is improved because of the active PMOS which is already

precharged.

The path to VSS is closed by the NMOS i.e., the ground switch and hence the pull

down time increases.

Two-Phase Operation

Phase CLK Inputs Output

Precharge low don’t care high

Evaluation high Valid inputs Valid outputs

Example


Two phase operation

Precharge (CLK = 0) Evaluate (CLK = 1)

Conditions on Output

• Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

• Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is

stored on CL

Implement following function using DYNAMIC CMOS LOGIC


Number of transistor required= N+2 =5+2

TOTAL=7 Transistor

Example :4-Input NAND Dynamic CMOS Gate

Properties of Dynamic Gates

• Logic function is implemented by the PDN only

– number of transistors is N + 2(CLOCK)(versus 2N for static complementary

CMOS)

– should be smaller in area than static complementary CMOS

• Full swing outputs (VOL = GND and VOH = VDD)

• Nonratioed - sizing of the devices is not important for proper functioning (only for

performance)


• Faster switching speeds

– reduced load capacitance due to lower number of transistors per gate.

• Power dissipation should be better

– consumes only dynamic power – no short circuit power consumption since the

pull-up path is not on when evaluating

• But power dissipation can be significantly higher due to

– higher transition probabilities

– extra load on CLK

• PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all

equal to VTn

– low noise margin (NML)

• Needs a precharge clock

DRAWBACK

• Inputs have to change during the precharge stage and must be stable during the evaluate.

If this condition cannot occur then charge redistribution corrupts the output node.

• A simple single dynamic logic cannot be cascaded. During the evaluate phase the first

gate will conditionally discharge but by the time the second gate evaluates, there is going

to be a finite delay. By then the first gate may precharge.

Cascading Problem in Dynamic CMOS Logic

• If several stages of the previous CMOS dynamic logic circuit are cascaded together using

the same clock CLK, a problem in evaluation involving a built-in “race condition” will

exist


• Consider the two stage dynamic logic circuit in the above diagram :

– During pre-charge, both output1 and output2 are pre-charged to VDD

– When CLK goes high to begin evaluate, all inputs at stage 1 require some finite time to resolve, but during this time charge may erroneously be discharged from output2

Now assume that eventually the 1st stage NMOS logic tree conducts and fully discharges output1, but since all the inputs to the N-tree all not immediately resolved, it takes some time for the N-tree to finally discharge output1 to GND.

If, during this time delay, the 2nd stage has the input condition shown with bottom NMOS transistor gate at a logic 1, then output2 will start to fall and discharge its load capacitance until output1 finally evaluates and turns off the top series NMOS transistor in stage 2

The result is an error in the output of the 2nd stage output2


CMOS Domino Logic

• A modification of clocked CMOS logic allows a single clock to precharge and evaluate a cascaded set of dynamic logic blocks. This involves incorporating a static CMOS inverter into each logic gate as shown in below figure.

• The problem with faulty discharge of precharged nodes in CMOS dynamic logic circuits can be solved by placing an inverter in series with the output of each gate

– All inputs to N logic blocks (which are derived from inverted outputs of previous stages) therefore will be at zero volts during precharge and will remain at zero until the evaluation stage has logic inputs to discharge the precharged node.

All circuits only provide non-inverted outputs

When CLK is low, dynamic node is precharged high and buffer inverter output is low. NFETs in

the next logic block will be off. When CLK goes high, dynamic node is conditionally discharged

and the buffer output will conditionally go high. Since discharge can only happen once, buffer

output can only make one low-to-high transition.

When domino gates are cascaded, as each gate “evaluates”, if its output rises, it will

trigger the evaluation of the next stage, and so on… like a line of dominos falling. Like dominos,

once the internal node in a gate “falls”, it stays “fallen” until it is “picked up” by the precharge

phase of the next cycle.

Thus many gates may evaluate in one eval cycle.


CMOS Domino Logic Design Hazards

• In (a) the N evaluate transistor is placed nearest to the output C1 node (poor design)

– During precharge C1 is charged high to VDD, but C2-C7 do not get charged and may be sitting at ground potential.

– When the clock goes high for the evaluate phase, some or all of capacitors C2-C7

will bleed charge from the larger node capacitor C1, thus reducing the voltage on C1.

• Voltage across C1 i.e. V(C1) may reduce to VDD(C1/(C1 + C2 + C3 + C4 + C5 + C6 + C7)) in the worst case

Vn1=∑

푉


V (C1) =푽푫푫푪ퟏ

푪ퟐ 푪ퟑ 푪ퟒ 푪ퟓ 푪ퟔ 푪ퟕ 푪ퟏ

If 푪ퟏ = ퟑ푪ퟐ and 푪ퟐ = 푪ퟑ = 푪ퟒ = 푪ퟓ = 푪ퟔ = 푪ퟕ and VDD=5v

then V (C1) =ퟑ푪ퟐ푽푫푫ퟔ푪ퟐ ퟑ푪ퟐ

==ퟑ푪ퟐ푽푫푫ퟗ푪ퟐ

=ퟑ푽푫푫ퟗ

=푽푫푫ퟑ

=1.5v

this is below the threshold voltage of buffering inverter

– The solution is to put the discharge transistor N1 at the bottom of the logic tree thus allowing the possibility of getting C2-C7 charged during the precharge phase

• Using additional precharge P transistors (as in b) to charge intermediate nodes in a complex logic tree will help with the charge sharing problem.

NP Domino Logic (NORA Logic)

• An elegant solution to the dynamic CMOS logic “erroneous evaluation” problem is to use NP Domino Logic (also called NORA logic) as shown below.

• Alternate stages of N logic with stages of P logic


• N logic stages use true clock, normal precharge and evaluation phases, with N logic tree in the pull down leg. P logic stages use a complement clock, with P logic stage tied above the output node.

• During precharge clk is low (-clk is high) and the P-logic output precharges to ground while N-logic outputs precharge to Vdd.

• During evaluate clk is high (-clk is low) and both type stages go through evaluation; N-logic tree logically evaluates to ground while P-logic tree logically evaluates to Vdd.

If we turn a dynamic gate “upside down” and use PFETs to build the logic block, we get a logic gate that “precharges” low and “discharges” high. By using these gates in an alternating sequence with regular NFET dynamic gates we can eliminate the race problem we had with NFET-only dynamic gate sequences and hence we don’t need the buffer inverter present in domino gates.

Removing the buffer is a mixed blessing since we may need it for drive reasons and to keep compatibility with other domino gates. It also makes NORA logic very susceptible to noise since during the evaluate phase all information is stored dynamically.

NORA CMOS Logic Circuit Example

• An example of NP or NORA (No Race) logic is shown below:

• During CLK low (CLK’ high), each stage pre-charges

– N logic stages pre-charge to VDD; P logic stages pre-charge to GND


• When CLK goes high (CLK’ low), each stage enters the evaluation phase

– N logic evaluates to GND; P logic stages evaluate to VDD

– All NMOS and PMOS stages evaluate one after another in succession, as in Domino logic

• Logic below:

– Stage 1 is X = (A · B)’

– Stage 2 is G = X’ + Y’

– Stage 3 is Z = (F · G + H)’


CLOCKED CMOS LOGIC

• Clocked CMOS logic has been used for very low power CMOS and/or for minimizing hot electron effect problems in N-FET devices

• Clocking transistors allow valid logic output only when CLK is high

• Clocking transistors may be at output end of logic trees (maximum performance) or at power supply end of logic trees (maximum protection from hot electrons)


Implement following function using CLOCKED CMOS LOGIC

a) NAND2 GATE b) NOR2 GATE


Differential Cascode Voltage Switch Logic

• It is possible to create a ratioed logic style that completely eliminates static currents and provides rail-to-rail swing. Such a gate combines two concepts: differential logic and positive feedback.

• A differential gate requires that each input is provided in complementary format, and produces complementary outputs in turn. The feedback mechanism ensures that the load device is turned off when no needed


CASE 1: Assume PDN1 OFF (0) this will make PDN2 ON (1) (Because PDN1 and PDN2 are mutually exclusive) So PDN2 ON (1) will make Out will discharge completely and it will become (Out=0) this will make M1 ON this will make Out to charge VDD (Out=1) because of PDN1 is OFF, Out stays at 1 this will turn off M2

CASE 2: Assume PDN1 ON (1) this will make PDN2 OFF (0) (Because PDN1 and PDN2 are mutually exclusive) So PDN1 ON (1) will make Out will discharge completely and it will become (Out=0) this will make M2 ON this will make Out to charge VDD (Out=1) because of PDN2 is OFF Out stays at 1 only, this will turn off M1

1. NAND and AND


2.XNOR and XOR

2. XNOR and XOR Verification

OR


3. Implement following function using DCVL LOGIC


ADVANTAGES

The DCVSL gate provides differential (or complementary) outputs. Both the output signal (Vout1) and its inverted value (Vout2) are simultaneously

available. This is a distinct advantage, as it eliminates the need for an extra inverter to produce the

complementary signal. It has been observed that a differential implementation of a complex function may reduce

the number of gates required by a factor of two

Pass-Transistor Logic

A popular and widely-used alternative to complementary CMOS is pass-transistor logic which attempts to reduce the number of transistors required to implement logic by

allowing the primary inputs to drive gate terminals as well as source/drain terminals


COMPLEMENTARY PASS TRANSISTOR LOGIC

1. AND/NAND

2. OR/NOR


3. XOR/XNOR

TRANSMISSION GATE – SYMBOL & LAYOUT


1. Implementation of Multiplexor(2:1) using TG


2. Implementation of XOR using TG


3. Implementation of D Latch using TG


Problems 1. Design 4 to 1 multiplexor using transmission-gates. 2. Implement a full adder using transmission gates. 3. Implement AB+BC using Pass Transistor Logic Case Study and Seminar

Clocking Strategies I/O Structures Low power Design


UNIT-5 Datapath Subsystems

Chip functions generally can be divided into the following categories:

1. Data path operators

2. Memory elements

3. Control structures

4. Special-purpose cells

I/O

Power distribution

Clock generation and distribution

Analog and RF

Data path operations-Addition/Subtraction

Addition forms the basis for many processing operations, from ALUs to address generation to

multiplication to filtering. As a result, adder circuits that add two binary numbers are of great

interest to digital system designers. An extensive, almost endless, assortment of adder

architectures serves different speed/power/area requirements. This section begins with half

adders and full adders for single-bit addition

ADDER

HALF ADDER

The half adder adds two single-bit inputs, A and B, The result of two bits are required to

represent the value; they are called the sum S and carry-out Cout. The carry-out is equivalent to a

carry-in to the next more significant column of a multibit adder,


1. FULL ADDER

For a full adder, it is sometimes useful to define Generate (G), Propagate (P), and Kill (K)

signals.

The adder generates a carry when Cout is true independent of Cin, so GenerateG =

A · B.

The adder kills a carry when Cout is false independent of Cin, so K = A · B = A + B

The adder propagates a carry; i.e., it produces a carry-out if and only if it receives a

carry-in, when exactly one input is true:

the full adder logic is


Write K map , simplify and get the equation for S and Cout


2. SIMPLIFIED FULL ADDER in single design


SUBTRACTOR

An N-bit subtractor uses the two’s complement relationship

This involves inverting one operand to an N-bit carry-propagate adder and adding 1 via the carry input, as shown in Figure

ADDER/SUBTRACTOR

An adder/subtractor uses XOR gates to conditionally invert B, as shown in below Figure.

In prefix adders, the XOR gates on the B inputs are sometimes merged into the bitwise PG

circuitry.

Example: Design of 4 bit Binary Adder/Subtractor

While it is perfectly possible to design a custom circuit for the subtraction operation, it is much more common to re-use an existing adder and to replace a subtraction by a two-complement's addition.

The figure shows how this is done

When the SUB/ADD input is low (0), the XOR-gates act as non-inverting buffers and the carry-input to the adder is 0. Therefore, the adder calculates a four-bit sum plus carry-out:

(Cout, S3, S2, S1, S0) = (A3, A2, A1, A0) + (B3, B2, B1, B0)


If the SUB/ADD input is high (1), the XOR-gates act as inverting buffers, and the carry-input to the adder is 1.

(Cout, S3, S2, S1, S0) = (A3, A2, A1, A0) - (B3, B2, B1, B0) 2. ADD A+B A 1110 B 1111 SUM= 1101 CAR=1

2. SUBTRACT A-B

A 1110 B 1111 1‘s Compliment of B 0000 2’s Compliment of B=1‘s Compliment of B+1= 0000+1= 0001 S=A-B=A+B+1=A+2’s Compliment of B


S=1110+0001 S=1111 BOR=1

MULTIPLICATION Multiplication can be considered as a series of repeated additions. The number to be added is

the multiplicand, the number of times that it is added is the multiplier, and the result is the

product. Each step of the addition generates a partial product. In most computers, the operands

usually contain the same number of bits. When the operands are interpreted as integers, the

product is generally twice the length of the operands in order to preserve the information content.

This repeated addition method that is suggested by the arithmetic definition is slow that it is

almost always replaced by an algorithm that makes use of positional number representation. It is

possible to decompose multipliers in two parts. The first part is dedicated to the generation of partial

products, and the second one collects and adds them.

1. Parallel Multiplier


2. Serial Multiplier 3. Serial Parallel Multiplier 4. Booth Multiplier

1. Parallel Multiplier

M × N-bit multiplication P = Y × X can be viewed as forming N partial products of M bits each,

and then summing the appropriately shifted partial products to produce an M+ N-bit result P.

Binary multiplication is equivalent to a logical AND operation. Therefore, generating partial

products consists of the logical ANDing of the appropriate bits of the multiplier and

multiplicand. Each column of partial products must then be added and, if necessary, any carry

values passed to the next column. We denote the multiplicand as

We denote the multiplicand as Y {yM–1, yM–2, …, y1, y0} and the multiplier as X {xN–1, xN–2, …, x1, x0}. For unsigned multiplication, the product is given in Equation

For example, the multiplication of two positive 6-bit binary integers, 2510 and 3910, proceeds as shown in Figure


4 Bit array Multiplication


COMPARATOR

Digital or Binary Comparators are made up from standard AND, NOR and NOT gates

that compare the digital signals present at their input terminals and produce an output depending

upon the condition of those inputs. For example, along with being able to add and subtract binary

numbers we need to be able to compare them and determine whether the value of input A is

greater than, smaller than or equal to the value at input B etc. The digital comparator

accomplishes this using several logic gates that operate on the principles of Boolean algebra.

There are two main types of digital comparator available and these are.

1. Identity Comparator - an Identity Comparator is a digital comparator that has only one

output terminal for when A = B either "HIGH" A = B = 1 or "LOW" A = B = 0

2. Magnitude Comparator - a Magnitude Comparator is a type of digital comparator that

has three output terminals, one each for equality, A = B greater than, A > B and less

than A < B

The purpose of a Digital Comparator is to compare a set of variables or unknown

numbers, for example A (A1, A2, A3, .... An, etc) against that of a constant or unknown value

such as B (B1, B2, B3, .... Bn, etc) and produce an output condition or flag depending upon the

result of the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs

would produce the following three output conditions when compared to each other.

Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when any of the above three conditions are achieved. For example, produce an output from a counter when a certain count number is reached. You may notice two distinct features about the comparator from the above truth table. Firstly, the circuit does not distinguish between either two "0" or two "1"'s as an output A = B is produced when they are both equal, either A = B = "0" or A = B = "1". Secondly, the output condition for A = B resembles that of a commonly available logic gate, the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-bits giving: Q = A ⊕ B

Digital comparators actually use Exclusive-NOR gates within their design for comparing their respective pairs of bits. When we are comparing two binary or BCD values or variables against


each other, we are comparing the "magnitude" of these values, a logic "0" against a logic "1" which is where the term Magnitude Comparator comes from.

1-bit Comparator

Then the operation of a 1-bit digital comparator is given in the following Truth Table.

Truth Table

CMOS LOGIC STRUCTURE OF 1-BIT COMPARATOR

XNOR


PARITY GENERATORS

A parity bit can be added to an N-bit word to indicate whether the number of 1s in the word is

even or odd. In even parity, the extra bit is the XOR of the other N bits, which ensures the (N +

1)-bit coded word has an even number of 1s:

Parity generator helps in indicating the parity of a binary number or a word. Let us consider

One/Zero Detectors Detecting all ones or zeros on wide N-bit words requires large fan-in AND or NOR gates. Recall

that by DeMorgan’s law, AND, OR, NAND, and NOR are fundamentally the same operation

except for possible inversions of the inputs and/or outputs. You can build a tree of AND gates, as

shown in Figure. Here, alternate NAND and NOR gates have been used.


Don’t go in detail of Counters and Shifters( not required)

Counters

Two commonly used types of counters are binary counters and linear-feedback shift

registers. An N-bit binary counter sequences through 2N outputs in binary order. Simple designs

have a minimum cycle time that increases with N, but faster designs operate in constant time. An

N-bit linear-feedback shift registers sequences through up to 2N – 1 outputs in pseudo-random

order. It has a short minimum cycle time independent of N, so it is useful for extremely fast

counters as well as pseudo-random number generation.

Some of the common features of counters include the following:

Resettable: counter value is reset to 0 when RESET is asserted (essential for testing)

Loadable: counter value is loaded with N-bit value when LOAD is asserted

Enabled: counter counts only on clock cycles when EN is asserted

Reversible: counter increments or decrements based on UP/DOWN input

Terminal Count: TC output asserted when counter overflows (when counting up)

or underflows (when counting down)

1. Binary Counters

The simplest binary counter is the asynchronous ripple-carry counter, as shown in Figure

It is composed of N registers connected in toggle configuration, where the falling transition of

each register clocks the subsequent register. Therefore, the delay can be quite long. It has no

reset signal, making it difficult to test. In general, asynchronous circuits introduce a whole


assortment of problems, so the ripple-carry counter is shown mainly for historical interest and is

not recommended for commercial designs.

2. Ring Counters

A ring counter consists of an M-bit shift register with the output fed back to the input, as

shown in Figure. On reset, the first bit is initialized to 1 and the others are initialized to 0. TC

toggles once every M cycles. Ring counters are a convenient way to build extremely fast

prescalars because there is no logic between flip-flops, but they become costly for larger M.

3. Johnson Counters

Johnson or Mobius counter is similar to a ring counter, but inverts the output before it is fed

back to the input, as shown in Figure. The flip-flops are reset to all zeros and count through 2M

states before repeating. Table shows the sequence for a 3-bit Johnson counter.


4. Linear-Feedback Shift Registers

A linear-feedback shift register (LFSR) consists of N registers configured as a shift register. The

input to the shift register comes from the XOR of particular bits of the register, as shown in

Figure for a 3-bit LFSR. On reset, the registers must be initialized to a nonzero value (e.g., all

1s). The pattern of outputs for the LFSR is shown in Table.


Shifters Shifts can either be performed by a constant or variable amount. Constant shifts are trivial in

hardware, requiring only wires. They are also an efficient way to perform multiplication or

division by powers of two. A variable shifter takes an N-bit input, A, a shift amount, k, and

control signals indicating the shift type and direction. It produces an N-bit output, Y. There are

three common types of variable shifts, each of which can be to the left or right:

Rotate: Rotate numbers in a circle such that empty spots are filled with bits shifted off the

other end

Example: 1011 ROR 1 = 1101; 1011 ROL 1 = 0111

Logical shift: Shift the number to the left or right and fills empty spots with zeros.

Example: 1011 LSR 1 = 0101; 1011 LSL 1 = 0110

Arithmetic shift: Same as logical shifter, but on right shifts fills the most significant bits

with copies of the sign bit (to properly sign, extend two’s complement numbers when

using right shift by k for division by 2k).

Example: 1011 ASR 1 = 1101; 1011 ASL 1 = 0110

A. Funnel Shifter B. Barrel Shifter

Funnel Shifter Perform 6 different operations Logic Shift Right Logic Shift Left Arithmetic Shift Right Arithmetic Shift Left Barrel Shift Right Barrel Shift Left

Logic Shifter – After shift fills vacated positions with 0’s. ex. Logic Shift Right 2 110110 → _ _1101 → 001101 ex. Logic Shift Left 2

110110 →

0110_ _ →

011000


Arithmic shifter-For Right shift fills vacated positions with a value of Most Significant Bit ex. Arithmic Shift Right 2 110110 → 110110 → _ _1101 → 111101 For Left shift, same as Logic Shifter

Barrel shifter - Pushed out bits fill vacated bit positions. ex. Barrel Shift Right 2 110110 → _ _1101 → 101101 ex. Barrel Shift Left 2 110110 → 0110_ _ →011011

Relations between the Functions Logic Shift Left = Arithmic Shift Left

Barrel Shift Right = Nt – Barrel Shift left;

where Nt = Total number of Bits

Ex. For a 4 Bit shifter

4 - Barrel Shift Left 1 = Barrel Shift Right 3

Logic Shift Right = Nt – Logic Shift left;

where Nt = Total number of Bits

Shift and rotate examples for A = a7a6a5a4a3a2a1a0 and B = 3.


UNIT-6

Datapath Control So far we have talked about what goes into the datapath. These function units / latches /

muxes manipulate the data itself. But this logic is only part of the whole chip. Something needs to tell the datapath elements what to do. And this is the function of the control.

Control

It is usually an FSM since some operations that the chip performs take multiple clock cycles, and

the controller must know where it is in the instruction. In pipelined microprocessors, each

instruction may take n cycles to complete, but the next instructions are started before previous

ones have finished. The controller must track which instruction is at each function in each cycle.

FSM

Finite State Machines (as a sequential network) hold the present state in memory and compute

the next state and output using combinational logic. The input to the next state computation is the

present state and any inputs. A modulus counter represents the simplest FSM since it has no


inputs, the next state depends completely on the present state. For example, a Mod-5 counter

FSM counts 0, 1, 2, 3, 4, 0, 1, ... The general architecture of an FSM is the following: the

architecture consists of Compute Next State that uses the Present State to determine which will

be the next state to enter. The Clock input serves to synchronize the FSM operation into discrete

points of state change.

It is important to understand the role of the clock in coordinating the operation of the FSM. As

the following diagram illustrates, the Next State computation is (must be) completed when the

clock pulse occurs. The clock is active on the rising edge in this example meaning that all

changes to the memory occur on the rising clock edge. The Next State becomes the Present State

on the active clock edge, meaning the count changes.

FSM Design

• This presentation deals with front to end design of finite state machines, both Mealy and

Moore types.

FSM Implementation

• Converting a problem to equivalent state table and state diagram is just the first step in the design process

• The next step is to design the system hardware that implements the state machine.

• This section deals with the process involved to design the digital logic to implement a finite state machine.

• First step is to assign a uniquely binary value to each of the state that the machine can be in. The state must be encoded in binary.

• Next we design the hardware to go from the current state to the correct next state. This logic converts the current state and the current input values to the next state values and stores that value.

• The final stage would be to generate the outputs of the state machine. This is done using combinatorial logic.

Assigning State Values


• Each state must be assigned to a unique binary value; for a machine with n states we have [log2n] bits;

• Any values can be assigned to the states, some values can be better than others (in terms of minimizing the logic to create the output and the next state values)

• This is actually an iterative process: first the designer creates a preliminary design to generate the outputs and the next states, then modifies the state values and repeats the process. There is a rule of thumb, that simplifies the process: whenever possible, the state should be assigned the same with the output values associated with that state. In this case, same logic can be used to generate the next state and the output

Mealy and Moore Machine Implementations

• The current state value is stored into the register

• The state value together with the machine inputs, are input to a logic block (CLC) that generates the next state value and machine outputs

• The next state is loaded into the register on the rising edge of the clock signal


EXAMPLE: Modulo 6 Counter

Specification:

• A module 6 counter is a 3-bit counter that counts through the following sequence:

– 000->001->010->011->100->101->000->…

– 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0 …

• It doesn’t use value 6 (110) nor 7 (111)

• It has an input I that controls the counter:

– When I=1 the counter increments its value on the rising edge of the clock

– When I=0 the counter retains its value on the rising edge of the clock

• The value of the count is represented as three bit value (C2C1C0)

• There is an additional output O (Carry) that is 1 when going from 5 to 0 and 0 otherwise (the O output remains 1 until the counter goes from 0 to 1)

Modulo 6 Counter – State table

Present State

I Next State

0 C2C1C0

S0 0 S0 1 000

S0 1 S1 0 001

S1 0 S1 0 001

S1 1 S2 0 010

S2 0 S2 0 010

S2 1 S3 0 011

S3 0 S3 0 011

S3 1 S4 0 100

S4 0 S4 0 100


S4 1 S5 0 101

S5 0 S5 0 101

S5 1 S0 1 000

• For each state examine what happens for all possible values of the inputs

– In state S0 input ‘I’ can be either 0 or 1

– If I=0 the state machine remains in state S0 and outputs ‘O’=1 and C2C1C0=000

– If I=1 the state machine goes in state S1, outputs O=0 and C2C1C0=001

• In the same manner, each state goes to the next state if I=1 and remains in the same state if I=0

Generating the Next State

• Since the Mealy and Moore machines must traverse the same states under the same conditions, their next state logic is identical

• We will present three methods to generate the next state logic:

– (i) Combinatorial logic gates

– (ii) Using multiplexers

– (iii) Using lookup ROM

• To begin with, we need to setup the truth table for the next state logic

Modulo 6 Counter - Next State Logic (i)

Present State

P2P1P0

I Next State

N2N1N0

000 0 000

000 1 001


001 0 001

001 1 010

010 0 010

010 1 011

011 0 011

011 1 100

100 0 100

100 1 101

101 0 101

101 1 000

• The system inputs and the present states are the inputs of the truth table

• Next state bits are the outputs

• We have to construct a Karnaugh map for each output bit and obtain its equation

• After that we design the logic to match the equations

• N2 = P2P0 + P2I +P1P0I

• N1 = P1P0 + P1I + P2P1P0I

• N0 = P0I + P0I


• Modulo 6 Counter – Next State implementation using logic gates (i)

Generating System Outputs

• Both for Mealy and Moore machines we follow the same design procedure to develop their output logic

• There are two approaches to generate the output (similar to generate the next state logic):

– Using combinatorial logic gates

– Using lookup ROM

• We are beginning by creating the truth table:

– For Mealy machine, the truth table inputs will be the present state and the system inputs, and the table outputs are the system outputs

– For Moore machine, only the state bits are inputs of the truth table, since only these bits are used to generate the system outputs; the table outputs are the system outputs


Moore Modulo 6 Counter – Moore state diagram

• The outputs are represented adjacent to the state

• The inputs are represented on the arcs

P2P1P0 O C2C1C0

000 1 000

001 0 001

010 0 010

011 0 011

100 0 100

101 0 101


Mod 6 Counter – Moore Implementation

• The outputs depend only on the present state and not on its inputs

• Its configuration is different than the Mealy machine

– The system output depends only on the present state, so the implementation of the output logic is done separately

– The next state is obtained from the input and the present state (same as for the Mealy machine)

• Outputs - Moore machine:

– C2 = P2

– C1 = P1

– C0 = P0

– O = P2’P1’P0’ = (P2+P1+P0)’


• Modulo 6 Counter – Moore Implementation

Mealy

Modulo 6 Counter - Mealy state diagram

• The outputs are represented on the arcs as I/OC2C1C0


P2P1P0 I O C2C1C0

000 0 1 000

000 1 0 001

001 0 0 001

001 1 0 010

010 0 0 010

010 1 0 011

011 0 0 011

011 1 0 100

100 0 0 100

100 1 0 101

101 0 0 101

101 1 1 000


Mod 6 Counter – Mealy Implementation

• The logic block (CLC) is specific to every system and may consist of combinatorial logic gates, multiplexers, lookup ROMs and other logic components

• The logic block can’t include any sequential components, since it must generate its value in one clock cycle

• The logic block contains two parts:

– One that generates the outputs (f function, CLC1)

– One that generates the next state (g function, CLC2)


Outputs - Mealy (i)

• Mealy machine (note that the equations for C2, C1, C0 are exactly the same as for the N2, N1, N0. This is the result of optimally assignation of the state values. Same combinatorial logic can be use to obtain the outputs):

– C2 = P2P0’+P2I’+P1P0I

– C1 = P1P0’+P1I’+P2P1’P0I

– C0 = P0’I+P0I’

– O = P2’P1’P0’I’+P2P0I


Modulo 6 Counter – Mealy Implementation

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