Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comVLSI PHYSICAL DESIGNINTRODUCTION:The transformation of a circuit description into a geometric description,is known as a layout. Alayout consists of a set of planar geometric shapes in several layers.The process of converting the specifications of an electrical circuit into a layout is called the Physical design.Due to the large number of components and the fine details required by the fabrication process,the physical design is not practically possiblewithout the help of computers. As a result, almostall phasesofphysical designextensivelyusecomputeraideddesign!"AD#toolsandmanyphases are either partially or fully automated. This automation of the physical design processhas increased the level of integration, reduced the turnaround time, and enhanced chipperformance.There are various"AD toolsavailablein marketand each of them havetheir own strengthsand weaknesses. The $lectronic Design Automation !$DA# companies like "adence,%ynopsys, &agma, and &entor 'raphics provide these "AD tools.()%*physical designautomationismainlydealswiththestudyofalgorithmsrelatedtothephysical design process. The ob+ective is to study optimal arrangements of devices on a plane !orinathreedimensional space#andvariousinterconnectionschemesbetweenthesedevicestoobtain the desired functionality. ,ecause space on a wafer is very expensive, algorithms mustusethespaceveryefficientlytodecreasethecostsandimprovetheyield. *naddition, thearrangement of devices !placement# plays a key role in determining the performance of a chip.Algorithms for physical design must also ensure that all the rules required by the fabrication arefollowedand that thelayoutiswithin thetolerance limitsofthe fabrication process.-inally,algorithms must be efficient and should be able to handle very large designs. $fficient algorithmsnot only lead to fast turnaround time, but also permit designers to iteratively improve the layouts.VLSI DESIGN CYCLE: The design process ofproducing a packaged()%* chip physicallyfollows various steps whichis popularly known as ()%* design cycle.This design cycle is normally represented by a flowchart shown below. The various steps involved in the design cycle are elaborated below.1 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.com(i). System speciic!ti"#. The specifications of the system to be designed are exactly specified inthis step. *t considersperformance, functionality, and the physical dimensions of the design. Thechoice offabrication technology and design techniques are also considered. The end results arespecifications for the si/e, speed, power, and functionality of the ()%* system to be designed.(ii) $%#cti"#!& 'esi(#:*nthis step, behavioral aspects of thesystemareconsidered. Theoutcomeis usually a timing diagram or other relationships between subunits. This informationis used to improve the overall design process and to reduce the complexity of the subsequentphases.(iii). L"(ic 'esi(#. *nthis step, the functionaldesign is convertedinto a logical design,using the ,ooleanexpressions. Theseexpressions areminimi/ed to achievethe smallest logicdesign whichconforms to thefunctional design.This logic design ofthe system is simulatedand tested to verify itscorrectness.(i)).Ci*c%it 'esi(#:This step involvesconversion of,oolean expressions into a circuit representation by taking into consideration thespeedandpowerrequirementsoftheoriginal design. Theelectrical behaviorofthevarious2 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comcomponents arealsoconsideredinthis phase. Thecircuit designis usuallyexpressedinadetailed circuit diagram.()).P+ysic!& 'esi(#.*n this step, the circuit representation of each component is converted intoa geometric representation. This representation is a set of geometric patterns which perform theintended logic function of the corresponding component. "onnections between differentcomponents are also expressed as geometric patterns. !This geometric representation of a circuitis calledalayout#. Theexact details of thelayout alsodependondesignrules, whichareguidelines based on the limitations of the fabrication process and the electrical properties of thefabrication materials. Physical design is a very complex process, therefore, it is usually brokendown into various substeps in order to handle the complexity of the problem. ()i). Desi(# )e*iic!ti"#:*n this step, the layout is verified to ensure that the layout meets thesystemspecificationsandthefabricationrequirements. Designverificationconsistsofdesignrule checking !D0"# and circuit extraction. D0" is a process which verifies that all geometricpatterns meet the design rules imposed by the fabrication process. After checking the layout fordesign rule violations and removing them, the functionality of the layout is verified by circuitextraction. This is a reverse engineering process and generates the circuit representation from thelayout. Thisreverseengineeredcircuit representationcanthenbecomparedtotheoriginalcircuit representation to verify the correctness of the layout.()ii). $!,*ic!ti"#:This step is followed after the design verification. The fabrication processconsists of several steps like, preparationof wafer, deposition, anddiffusionof variousmaterials on the wafer according to the layout description. A typical wafer is 12 cm in diameterandcanbeusedtoproducebetween13and42chips. ,eforethechipismassproduced, aprototype is made and tested.()iii). P!c-!(i#(. testi#(. !#' 'e,%((i#( . *n this step, the chip is fabricated and diced in afabrication facility. $ach chip is then packaged and tested to ensure that it meets all the designspecifications and that it functions properly. "hips used in printed circuit boards !P",s# arepackaged in a dual inline package !D*P# or pin grid array !P'A#. "hips which are to be used ina multichip module!&" are not packaged because &"&s use bare or naked chips.PHYSICAL DESIGN CYCLE :3 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comThe Physical designcycle converts acircuit diagramintoa layout. This complextaskiscompleted in several steps ,like s partitioning, floorplanning, placement, routing, and layoutcompaction etc. The details of these steps are given below.(!).P!*titi"#i#( . The chip layout is always a complex task and hence it is divided intoseveral smaller tasks. A chip may contain several million transistors. )ayout of the entire circuitcannot be handled due to the limitation of memory space as well as computation power available.Therefore, it is normallypartitionedbygroupingthecomponents intoblocks. Theactualpartitioning process considers many factors such as si/e of the blocks, number of blocks, andnumberofinterconnectionsbetweentheblocks.Theoutputofpartitioningisasetofblocksalong with the interconnections required between blocks. The set of interconnections required isreferredtoasanet list. *nlargecircuitsthepartitioningprocessishierarchical andat thetopmost level achipmayhavebetween5and35blocks. $achmoduleisthenpartitionedrecursively into smaller blocks.A disadvantage of the partitioning process is that it may degrade the performance of the finaldesign. During partitioning, critical components should be assigned to the same partition. *f suchan assignment is not possible, then appropriate timing constraints must be generated to keep thetwocritical componentsclosetogether.6sually,several components, formingacritical path,determinethechipperformance. *f eachcomponent is assignedtoadifferent partition, thecritical path may be too long. &inimi/ing the length of critical paths improves systemperformanceAfter a chip has been partitioned, each of the subcircuits must be placed on a fixed plane and thenets between all the partitions must be interconnected. The placement of the subcircuits is doneby the placement algorithms and the nets are routed by using routing algorithms.(,)P&!ceme#t:*t istheprocessofarrangingaset ofmodulesonthelayout surface.$achmodule has fixed shape and fixed terminal locations. A poor placement uses larger area andhenceresults in performance degradation.The placement process determines the exact positions of the blocks on the chip, so as to find aminimum area arrangement for the blocks that allows completion of interconnections betweenthe blocks. Placement is typically done in two phases. *n the first phase an initial placement is4 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comcreated. *n the second phase the initial placement is evaluated and iterative improvements aremade until the layout has minimum area and conforms to design specifications.*t is important to note that some space between the blocks is intentionally left empty to allowinterconnections between blocks. Placement may lead to unroutable design, i.e., routing may notbe possible in the space provided. Thus, another iteration of placement is necessary. To limit thenumber of iterations of the placement algorithm, an estimate of the required routing space is usedduring the placement phase. A good routing and circuit performance heavily depend on a goodplacement algorithm.This is due to the fact that once the position of each block is fixed, verylittle can be done to improve the routing and the overall circuit performance.There are various types of placements.System/&e)e& p&!ceme#t :Place all the P",s together such that Area occupied is minimumand 7eat dissipation is within limits.0"!*'/&e)e& p&!ceme#t :All the chips have to be placed on a P",. Area is fixed All modulesof rectangular shape.The ob+ective is to ,&inimi/e the number of routing layers and &eet system performancerequirements.C+ip/&e)e& p&!ceme#t :8ormally, floor planning9 placement carriedout alongwithpinassignment. *t has limited number of routing layers !3 to :#. ,ad placements may be unroutable."an be detected only later!during routing#. "ostly delays in design cycle.&inimi/ationofarea.$&""*p&!##i#(:-loorplan design is an important step in physical design of ()%* circuits to plan the positions ofa set of circuit modules on a chip in order to optimi/e the circuit performance. *n floorplanning,the information of a set of modules, including their areas and interconnectionis considered andthegoal is to plan their positions on a chip to minimi/e the total chip area andinterconnect cost. *n the floor planning phase, the macro cellsare positioned on the layout surface in such a waythat no blocks overlap and that there is enough space left to complete the interconnections. Theinput for the floor planning is a set of modules, a list of terminals !pins for interconnections# foreach module and a net list, which describes the terminals which have to be connected.5 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comDifferent approaches are followed to the floor planning problem. ;imeret al.describe a branchand bound approach for the floor plan si/ing problem, i.e. finding an optimal combination of allpossible layoutalternatives for all modules after placement. ;hile their algorithm is able to findthe best solutionfor this problem, it is verytime consuming, especiallyfor real probleminstances."ohoonet al. implemented a genetic algorithm for the whole floor planning problem.Their algorithm makes use of estimates for the required routing space to ensure completion of6 Dr.Y.NARASIMHA MURTHY Ph.D yayavaram@yahoo.comthe interconnections. Another more often used heuristic solution method for placement is%imulated Annealing (c) R"%ti#(:The main ob+ective in this step isto complete the interconnections between blocksaccording to the specified netlist. -irst, the space not occupied by the blocks !called the routingspace#ispartitionedintorectangularregionscalledchannelsandswitchboxes.Thegoalofarouter is to complete all circuit connections using the shortest possible wire length and usingonly the channels and switchboxes. This is usually done in two phases, referred to as the globalrouting and detailedrouting phases. *n global routing, connections are completed between the proper blocks of the circuitdisregarding the exact geometric details of each wire and pin. -or each wire, the global routerfinds a list of channels which are to be used as a passage way for that wire. *n other words,global routingspecifiesthe