VLSI Design

A Course on

Design of Digital VLSI Systems & Circuits

ByPragnan Chakravorty

Associate Professor & H O D (E&TC) CIET RaipurAssociate Professor & H.O.D (E&TC),CIET, RaipurM.Tech (IIT Kharagpur), MIEEE

Member IEEE(USA) :‐Communication. Soc, 

Microwave Theory and Techniques Soc,Antenna & Wave Propagation. SocAntenna & Wave Propagation. Soc

IEEE Standards Soc.

INTRODUCTION TO INTEGRATED CIRCUITS

How is a VLSI Circuit Different?Unlike conventional electronic circuits, Transistors in a VLSI/ Integrated Circuits arecarved / sculpted over a single‐wafer (Monolith) of semiconductor almostcarved / sculpted, over a single‐wafer (Monolith) of semiconductor, almostconcatenated so as to reduce the lengths of interconnects. The interconnects aremade as the final layer of fabrication known as metallization layer. Metallizations arenow done using polysilicon. The ability to manipulate the area/volume occupied bynow done using polysilicon. The ability to manipulate the area/volume occupied bythe carved transistors and the interconnects between them renders a tremendousscope of device miniaturization /scaling and a very large scale integration over asmall space.

SSI, MSI, LSI,VLSI,ULSI:There has been a tremendous rise in the number of devices integrated into a single chip(conventionally 10mm x 10mm area chip) in the past few decades as a result the scale ofdevice integration has been categorized as follows:

Device Integration Table:

S.No Category Year Number of  D iDevices

1 Small Scale Integration (SSI) 1964 05 ‐to‐ 20

2 Medium Scale Integration (MSI) 1967 20 ‐to‐ 200

3 Large Scale Integration (LSI) 1972 200 ‐to‐ 2000

4 Very Large Scale Integration (VLSI) 1978 2000 ‐to‐ 20000

5 Ultra Large Scale Integration (ULSI) 1989 20000 ‐to‐ ?

Moor’s Law:In 1965, a Caltech Professor, Gordon Moore observed that plotting the number of transistorsthat can be most economically manufactured on a chip gives a straight line on a semithat can be most economically manufactured on a chip gives a straight line on a semilogarithmic scale. At the time, he found transistor count doubling every 18 months. Thisobservation has been called Moore’s Law and has become a self‐fulfilling prophecy

Moor’s graph compared with actuality

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Date of Introduction

Advantages of High Scale Integration/Device Miniaturization:The most important message here is that the logic complexity per chip has beenp g g p y p p(and still is) increasing exponentially. The monolithic integration of a large numberof functions on a single chip usually provides:

Less area/volume and therefore, compactness

Less power consumption

Less testing requirements at system level

Higher reliability mainly due to improved on chip interconnectsHigher reliability, mainly due to improved on‐chip interconnects

Higher speed, due to significantly reduced interconnection length

Significant cost savings due to batch processing

Lesser fabrication error /Higher yield due to batch processing/ g y p g

VLSI Design FlowA VLSI system is a multi domain system where designs need to be carried out fromb h i l l l t h i l l t l l With i h d i th d i bbehavioral levels to physical layout levels. With in each domain the design can becategorized into certain levels of abstraction and then the designs need to followcertain hierarchically categorized steps.

Domains of Design: Domains are different distinct categories over which any engineering system spans. There can be three such major domains stated below:

Behavioral domain:  Which describes  the behavior of the system for example the transmitting behavior of a transmitter system.

Structural domain:  Which describes the structure of the system for example where and how are the various amplifiers ,oscillators, filters etc are structured in the  transmitter system.

Geometrical layout domain.  Describe the  physical layout or placement of  different components or devices in a system for example the placement  and connections b t i t i t RLC i lifi ill t filt tbetween various transistors , RLCs, in amplifiers oscillators filters etc.

Generalized Design Flow

The Y ChartThe Y‐chart (first introduced by D. Gajski) shown in Fig. illustrates a design flow for

t l i hi i d i ti iti th diff t (d i ) hi hmost logic chips, using design activities on three different axes (domains) whichresemble the letter Y.

Levels of AbstractionDomains can further be hierarchically divided into different levels of design b t ti Cl i ll th h i l d d th f ll iabstraction. Classically, these have included the following

for digital chips:Architectural or functional levelLogic or Register Transfer Level (RTL)Logic or Register Transfer Level (RTL)Circuit level

The relationship betweenThe relationship betweendescription domains and levels ofabstraction is elegantly shown bythe Gajski‐Kuhn Y chart in Figure.the Gajski Kuhn Y chart in Figure.In this diagram, the three radiallines represent the behavioral,structural, and physical domains.p yThe annular regions betweenconcentric circles show differentlevels of abstraction.

Design HierarchyThe levels of abstraction are generic divisions which can map designs of one domaini t th D i ifi di i i f th l l f b t ti ll dinto another. Domain specific divisions of the levels of abstractions are calledhierarchical divisions. The hierarchical design approach reduces the designcomplexity by dividing the large system into several sub‐modules

Hierarchical divisions in structural domain of a 4‐bit adder

Concepts of Regularity, Modularity and LocalityThough the design complexity reduces down with hierarchical sub‐modules, suchb d l th l t h d i t it ith h thsub module themselves must have some consonance and integrity with each other

so as to further simplify the design process and make them effective. Suchconsonance between the sub‐modules are brought in by the following concepts:

Regularity: Regularity is the division of the hierarchy into a set of similar buildingblocks (modules/sub‐modules). Regularity can exist at all levels of the designhierarchy. At the circuit level, uniformly sized transistors can be used, while at thehierarchy. At the circuit level, uniformly sized transistors can be used, while at thegate level, a finite library of fixed‐height, variable‐length logic gates can be used

Modularity: Modularity states that modules/sub‐modules have well‐definedfunctions and interfaces. If modules/sub‐modules are “well‐formed,” the interactionwith other modules/sub‐modules can be well characterized.

Locality: Locality is the localized composition of components with in a module/sub‐module so that they do not interact with other modules/sub‐modules. Thereforeinternals of a module/sub‐modules are unimportant to other modules/sub‐modules.S t l i t f d t ff t i t l i t f d iSo, external interfaces do not affect internal interfaces and visa‐versa.

VLSI Design Styles/MethodsThe VLSI design styles or methods depend upon the target IC platform or standard.Depending upon the IC standards the design style vary and have platform specificp g p g y y p plimitations and flexibility or advantages and disadvantages.

Overview VLSI Design Styles/ Standards/Platforms

Complex Programmable Logic Device(CPLD)

CPLD is a single device with multiple simple programmable logic devices(SPLDs) suchP bl A L i (PLA) G i A L i (GLA) PAL d GALas Programmable Array Logic (PLA) or Generic Array Logic (GLA). PALs and GALs are

based on sum of products (SOP) architecture with a programmable AND array and afixed OR array

CPLD Block DiagramPLA/GLA CKT View

PLA/GLA Block Diagram

Field Programmable Gate Array (FPGA) DesignA typical field programmable gate array (FPGA) chip consists of I/O buffers, an arrayof configurable logic blocks (CLBs) and programmable interconnect structures Theof configurable logic blocks (CLBs), and programmable interconnect structures. Theprogramming of the interconnects is implemented by programming of RAM cellswhose output terminals are connected to the gates of MOS pass transistors. Generaland detailed blocks of an FPGA are shown below.and detailed blocks of an FPGA are shown below.

The LUT is a di i ldigital memory that stores the truth table of the Boolean function. 

XILINX Model XC2000

Configurable Logic Block (CLB): A simple CLB (model XC2000 from XILINX) is shownabove where it consists of four signal input terminals (A, B, C, D), a clock signalterminal user‐programmable multiplexers an SR‐latch and a look‐up table (LUT)terminal, user‐programmable multiplexers, an SR‐latch, and a look‐up table (LUT).The LUT is a digital memory that stores the truth table of the Boolean function. It cangenerate any function of up to four variables or any two functions of three variables

While the design implementation of the FPGA chip is done with user programming,that of the gate array is done with metal mask design and processing. Gate array

Gate Array/ Sea of Gates  Design

implementation requires a two‐step manufacturing process: The first phase, which isbased on generic (standard) masks, results in an array of uncommitted transistors oneach GA chip. These uncommitted chips can be stored for later customization, whichis completed by defining the metal interconnects between the transistors of thearray

Standard Cell Based DesignIn this design style, all of the commonly used logic cells are developed, characterized,and stored in a standard cell library. A typical library may contain a few hundred cellsy yp y yincluding inverters, NAND gates, NOR gates, complex AOI, OAI gates, D‐latches, andflip‐flops. It is almost a full custom design but for the predesigned cells which can’tbe customized.

Full Custom DesignIn full custom design the customization starts at transistor level itself. Thereforedifferent cells can be customized and optimized according to the various designdifferent cells can be customized and optimized according to the various designspecifications and constraints. Full custom designs are usually prevalent with analogdesigns and not digital.

General Purpose IC  & ASSP System DesignSystem level digital designs are often practically done by programming generaly g g p y y p g g gpurpose ICs. These general purpose ICs are programmed using high level languagesand are different from the ASICs described so far. These ICs include variousmicroprocessors microcontrollers, MIPS , RISC and SISC processors. ApplicationSpecific System Processors(ASSPs) are also a kind of dedicated general purposeprocessors such as DSP processors which are programmed using high levellanguages.

DESIGN & FABRICATION ASPECTS

ofStandard Cell Based Design Style

Basic Steps of Fabrication ProcessEach processing step requires that certain areas aredefined on chip by appropriate masks.defined on chip by appropriate masks.Consequently, the integrated circuit may be viewedas a set of patterned layers of doped silicon,polysilicon, metal and insulating silicon dioxide. In

l l t b tt d b f th tgeneral, a layer must be patterned before the nextlayer of material is applied on chip. The processused to transfer a pattern to a layer on the chip iscalled lithography/Photolithography. Since eachg p y/ g p ylayer has its own distinct patterning requirements,the lithographic sequence must be repeated forevery layer, using a different mask

Figure at the right shows simplified processsequence for fabrication of the n‐well CMOSintegrated circuit with a single polysilicon layer,showing only major fabrication steps.

Lithographic Steps of Patterning

Set of Masks for Patterning

The cross‐section view is of aninverter

In a CMOS circuit fabrication, theh h l f khypothetical set of six masks: n‐well, polysilicon, n+ diffusion, p+diffusion, contacts, and metal.Masks specify where thep ycomponents will be manufacturedon the chip. Figure shows a topview of the six masks.

Different Development  Stages in CMOS Fabrication

Fabrication of NMOSFET & PMOSFET

Fabrication of N Well

Laying out interconnects and thick insulating oxides

2D & 3D Representations ofNMOS & PMOS in CMOS Process

Layout Design RulesThe physical mask layout of any circuit to be manufactured using a particular processmust conform to a set of geometric constraints or rules, which are generally calledg , g ylayout design rules. These rules usually specify the minimum allowable line widthsfor physical objects on‐chip such as metal and polysilicon interconnects or diffusionareas, minimum feature dimensions, and minimum allowable separations betweentwo such features. The main objective of design rules is to achieve a high overallyield and reliability while using the smallest possible silicon area, for any circuit to bemanufactured with a particular process.

The design rules are usually described in two ways :

•Micron rules: in which the layout constraints such as minimum feature sizes and•Micron rules: in which the layout constraints such as minimum feature sizes andminimum allowable feature separations, are stated in terms of absolute dimensionsin micrometers, or,

•Lambda rules: These rules specify the layout constraints in terms of a singleparameter λ (which is generally half the channel length and equal to the thickness ofpolysilicon layer) and, thus, allow linear, proportional scaling of all geometricalp y y ) , , , p p g gconstraints. The design rules are usually given by Metal Oxide SiliconImplementation Service (MOSIS‐ established in 1981).

Basic Lambda Design Rules

Sti k DiStick DiagramAs layout is time‐consuming, designers need fast ways to plan cells and estimatearea before committing to a full layout. Stick diagrams are easy to draw because theydo not need to be drawn to scale It is easy to estimate the area of a layout from thedo not need to be drawn to scale. It is easy to estimate the area of a layout from thecorresponding stick diagram even though the diagram is not to scale. As an examplestick diagrams of an inverter and 3 I/P NAND gate are shown below

MOSIS Design Rule (Sample Set)Rule number Description L‐Rule

R1 Minimum active area width 3 LR2 Mi i ti i 3 LR2 Minimum active area spacing 3 LR3 Minimum poly width 2 LR4 Minimum poly spacing 2 LR5 Minimum gate extension of poly over active  2 LR6 Mi i l ti d i 1 LR6 Minimum poly‐active edge spacing  1 L

(poly outside active area)R7 Minimum poly‐active edge spacing  3 L

(poly inside active area)R8 Mi i t l idth 3 LR8 Minimum metal width 3 LR9 Minimum metal spacing 3 LR10 Poly contact size 2 LR11 Minimum poly contact spacing 2 LR12 Minim m pol contact to pol ed e spacin 1 LR12 Minimum poly contact to poly edge spacing 1 LR13 Minimum poly contact to metal edge spacing 1 LR14 Minimum poly contact to active edge spacing 3 LR15 Active contact size 2 LR16 Minimum active contact spacing 2 LR16 Minimum active contact spacing 2 L

(on the same active region)R17 Minimum active contact to active edge spacing 1 LR18 Minimum active contact to metal edge spacing 1 LR19 Minimum active contact to poly edge spacing 3 LR19 Minimum active contact to poly edge spacing 3 LR20 Minimum active contact spacing 6 L

(on different active regions)

Illustration of some ofthe typical MOSIS layoutdesign rules listed above

NMOS & PMOS Transistors  as Switches( Binary Logic Generators)

NMOS Transistor PMOS Transistor

An NMOS transistor is built with a p‐type body and has regions of n‐typeAn NMOS transistor is built with a p type body and has regions of n typesemiconductor adjacent to the gate called the source and drain. They are physicallyequivalent and for now we will regard them as interchangeable. The body is typicallygrounded. A PMOS transistor is just the opposite, consisting of p‐type source andg j pp g p ypdrain regions with an n‐type body. In a CMOS technology with both flavors oftransistors, the substrate is either n‐type or p‐type. The other flavor of transistormust be built in a special well in which dopant atoms have been added to form thebody of the opposite type.

Transistor in OFF stateConsidering NMOS transistor, the body is generally grounded so the p–n junctions ofthe source and drain to body are reverse‐biased. If the gate is also grounded, no

Transistor in ON state

current flows through the reverse‐biased junctions. Hence, we say the transistor isOFF. Just the opposite happens with PMOS transistors.

When the gate voltage is raised, it creates an electric field that starts to attract freeelectrons to the underside of the Si–SiO2 interface. If the voltage is raised enough,the electrons outnumber the holes and a thin region under the gate called theh l i i d i d d i h fchannel is inverted to act as an n‐type semiconductor. Hence, a conducting path ofelectron carriers is formed from source to drain and current can flow. We say thetransistor is ON. Similarly in case of PMOS the conditions are reversed

MOS Transistors as Switches

Layout Examples:CMOS Inverter

NOR2 GATE

NAND2 GATE

Circuit Diagram                                                                  Layout Diagram

Circuit Diagram                                                                          Layout Diagram

Full Adder

Circuit Diagram Layout Diagram

Calculation of Capacitances & Resistances Capacitances and resistances are the most vital factors governing the performanceof a digital VLSI circuit Perhaps the most significant aspect of a digital circuit is itsof a digital VLSI circuit. Perhaps the most significant aspect of a digital circuit is itsspeed of operation which can be determined through delay calculations. Resistancesand capacitances in an IC form ‘RC’ pairs and cause various delays in the signal flow.Resistances and capacitances in ICs can be categorized into two:Resistances and capacitances in ICs can be categorized into two:Intrinsic RCs: Those resistances and capacitances which occur inside the transistorsExtrinsic RCs: The resistances and capacitances which occur outside the transistors.i.e. those which are contributed from the interconnects.

Resistance & Capacitance Calculation through RC Delay Model

Effective resistance in transistors:A unit NMOS transistor is defined to have effective resistance R. The size of the unittransistor is arbitrary but conventionally refers to a transistor with minimum lengthand minimum contacted diffusion width (i e 4/2λ) Alternatively it may refer to theand minimum contacted diffusion width (i.e., 4/2λ). Alternatively, it may refer to thewidth of the NMOS transistor in a minimum‐sized inverter in a standard cell library.An NMOS transistor of k times unit width has resistance R/k because it delivers ktimes as much current A unit PMOS transistor has greater resistance generally intimes as much current. A unit PMOS transistor has greater resistance, generally inthe range of 2R because of its lower mobility. R is typically on the order of 10 kΩ fora unit transistor.

Effective capacitance in transistors:Each transistor also has gate and diffusion capacitance. We define C to be the gatecapacitance of a unit transistor of either flavor. A transistor of k times unit width hascapacitance kC Diffusion capacitance depends on the size of the source/drain region Usingcapacitance kC. Diffusion capacitance depends on the size of the source/drain region. Usingthe approximations we assume the contacted source or drain of a unit transistor to alsohave capacitance of about C. Wider transistors have proportionally greater diffusioncapacitance. Increasing channel length increases gate capacitance proportionally but doesnot affect diffusion capacitance. Although capacitances have a nonlinear voltagedependence, we use a single average value. We roughly estimate C for a minimum lengthtransistor to be 1 fF/micron of width. In a 65 nm process with a unit transistor being 0.1micron wide C is thus about 0 1 fFmicron wide, C is thus about 0.1 fF.

Equivalent RC Circuit Representations Equivalent Circuit for an Inverter

Generalized model for MOSFET capacitances:The capacitances associated with a MOSFET are shown in Fig as lumped elements betweenthe device terminals. Based on their physical origins, the device capacitances can beclassified into two major groups: (1) oxide related capacitances and (2) junctionclassified into two major groups: (1) oxide‐related capacitances and (2) junctioncapacitances. The gate‐oxide‐related capacitances are Cgd (gate‐to‐drain capacitance), Cgs(gate‐to‐source capacitance), and Cgb (gate‐to‐substrate capacitance). Notice that in reality,the gate‐to‐channel capacitance is distributed and voltage dependent. Consequently, all ofthe oxide‐related capacitances described here change with the bias conditions of thetransistor.

Effective resistance in interconnects:The resistance of a metal or polysilicon line also have a profound influence on the signalpropagation delay over that line. The resistance of a line depends on the type of material used(polysilicon aluminum gold ) the dimensions of the line and finally the number and(polysilicon, aluminum, gold, ...), the dimensions of the line and finally, the number andlocations of the contacts on that line. Consider the interconnection line shown in Fig. The totalresistance in the indicated current direction can be found as

Where ρ represents the characteristic resistivity of the interconnect material, and Rsheetrepresents the sheet resistivity of the line, in (ohm/square). For a typical polysilicon layer, thesheet resistivity is between 20‐40 ohm/square, whereas the sheet resistivity of silicide is about2 4 ohm/square Using the formula given above we can estimate the total parasitic resistance2‐ 4 ohm/square. Using the formula given above, we can estimate the total parasitic resistanceof a wire segment based on its geometry. Typical metal‐poly and metal‐diffusion contactresistance values are between 20‐30 ohms, while typical via resistance is about 0.3 ohms.

Effective capacitance in interconnects:A set of simple formulas developed by Yuan and Trick in the early 1980’s can be used toestimate the capacitance of the interconnect structures in which fringing fields complicate theeffective capacitance calculation The following two cases are considered for two differenteffective capacitance calculation. The following two cases are considered for two differentranges of line width (w).

These formulas permit the accurate approximation of the parasitic capacitance values toThese formulas permit the accurate approximation of the parasitic capacitance values towithin 10% error, even for very small values of (t/h).

Power Dissipation

Static CMOS gates are very power‐efficient because they dissipate nearly zero power while idle.For much of the history of CMOS design, power was a secondary consideration behind speedand area for many chips. As transistor counts and clock frequencies have increased, powerconsumption has skyrocketed and now is a primary design constraint We begin by reviewingconsumption has skyrocketed and now is a primary design constraint. We begin by reviewingsome definitions. The instantaneous power P(t) drawn from the power supply is proportional tothe supply current iDD(t) and the supply voltage VDD

The energy consumed over some time interval T is the integral of the instantaneous power 

Static Power Dissipation

Considering the static CMOS inverter shown in Figure 4 26 if the input = '0 ' the associatedConsidering the static CMOS inverter shown in Figure 4.26, if the input = 0, the associatednMOS transistor is OFF and the pMOS transistor is ON. The output voltage is VDD or logic'1.'When the input = '1,' the associated nMOS transistor is ON and the pMOS transistor is OFF.The output voltage is 0 volts (GND). Note that one of the transistors is always OFF when the gateis in either of these logic states. Ideally, no current flows through the OFF transistor so thepower dissipation is zero when the circuit is quiescent, i.e., when no transistors are switching.Zero quiescent power dissipation is a principle advantage of CMOS over competing transistortechnologies. However, secondary effects including sub threshold conduction, tunneling, andtechnologies. However, secondary effects including sub threshold conduction, tunneling, andleakage lead to small amounts of static current flowing through the OFF transistor. Assuming theleakage current is constant so instantaneous and average power are the same, the static powerdissipation is the evaluation product of total leakage current and the supply voltage.

Dynamic Power Dissipation

Combinational & Sequential Logic DesignWith VHDLWith VHDL

What is VHDL?VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym forVery High Speed Integrated Circuits) It is a hardware description language that can beVery High Speed Integrated Circuits). It is a hardware description language that can beused to model a digital system at many levels of abstraction ranging from the algorithmiclevel to the gate level. The complexity of the digital system being modeled could vary fromthat of a simple gate to a complete digital electronic system, or anything in between. Thedigital system can also be described hierarchically. Timing can also be explicitly modeled inthe same description.The VHDL language can be regarded as an integrated amalgamation of the followinglanguages:languages:

sequential language +concurrent language +net‐list language +timing specifications +waveform generation language => VHDL

Therefore, the language has constructs that enable you to express the concurrent orsequential behavior of a digital system with or without timing. It also allows you to modelthe system as an interconnection of components. Test waveforms can also be generatedi th t t All th b t t b bi d t idusing the same constructs. All the above constructs may be combined to provide a

comprehensive description of the system in a single model

Use of VHDL in digital logic designVHDL is used to describe a model for a digital hardware device. This model specifies theexternal view of the device and one or more internal views. The internal view of the devicespecifies the functionality or structure while the external view specifies the interface of thespecifies the functionality or structure, while the external view specifies the interface of thedevice through which it communicates with the other models in its environment. The Figuredrawn below shows the hardware device and the corresponding software model.

What is an entity?What is an entity?Entity is an abstraction level of the hardware device in cosideration. The device to devicemodel mapping is strictly a one to many. That is, a hardware device may have many devicemodels. For example, a device modeled at a higher level of abstraction may not have a clock asone of its inputs, since the clock may not have been used in the description. Also the datatransfer at the interface may be treated in terms of say, integer values, instead of logicalvalues. In VHDL, each device model is treated as a distinct representation of a unique device,called an entity .called an entity .

Basic TerminologiesThe digital system can be as simple as a logic gate or as complex as a complete electronicsystem. A hardware abstraction of this digital system is called an entity. An entity X, when usedsystem. A hardware abstraction of this digital system is called an entity. An entity X, when usedin another entity Y, becomes a component for the entity Y. Therefore, a component is also anentity, depending on the level at which you are trying to model.To describe an entity, VHDL provides five different types of primary constructs, called design

i Thunits. They are

1. Entity declaration2. Architecture bodyy3. Configuration declaration4. Package declaration5. Package body

An entity is modeled using an entity declaration and at least one architecture body. The entitydeclaration describes the external view of the entity, for example, the input and output signalnames. The architecture body contains the internal description of the entity, for example, as aset of interconnected components that represents the structure of the entity, or as a set ofconcurrent or sequential statements that represents the behavior of the entity. Each style ofrepresentation can be specified in a different architecture body or mixed within a singlearchitecture body Figure given below shows an entity and its modelarchitecture body .Figure given below shows an entity and its model.

A configuration declaration is used to create a configuration for an entity It specifies theA configuration declaration is used to create a configuration for an entity. It specifies thebinding of one architecture body from the many architecture bodies that may be associatedwith the entity. It may also specify the bindings of components used in the selectedarchitecture body to other entities. An entity may have any number of differentconfigurations.A package declaration encapsulates a set of related declarations such as type declarations,subtype declarations, and subprogram declarations that can be shared across two or moredesign units. A package body contains the definitions of subprograms declared in a packagedesign units. A package body contains the definitions of subprograms declared in a packagedeclaration.

Once an entity has been modeled, it needs to be validated by a VHDL system. A typical VHDLsystem consists of an analyzer and a simulator. The analyzer reads in one or more design unitscontained in a single file and compiles them into a design library after validating the syntaxand performing some static semantic checks The design library is a place in the hostand performing some static semantic checks. The design library is a place in the hostenvironment (that is, the environment that supports the VHDL system) where compiled designunits are stored.The simulator simulates an entity, represented by an entity‐architecture pair or by aconfiguration, by reading in its compiled description from the design library and thenperforming the following steps:1. Elaboration2 Initialization2. Initialization3. Simulation

EXAMPLES

Entity Declaration: The entity declaration specifies the name of the entity being modeled andlists the set of interface ports. Ports are signals through which the entity communicates withthe other models in its external environment.

Here is an example of an entity declaration for the half‐adder circuit shown in Fig above

entity HALF ADDER is y _port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER; ‐‐ This is a comment line. 

The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies inputport), and two output ports, SUM and CARRY (the mode out specifies output port). BIT is apredefined type of the language; it is an enumeration type containing the character literals '0'and '1'. The port types for this entity have been specified to be of type BIT, which means thatthe ports can take the values, '0' or '1'.

Architecture Body: The entity declaration specifies the name of the entity being modeled andlists the set of interface ports. Ports are signals through which the entity communicates withthe other models in its external environment.

architecture HA_Archbody of HALF_ADDER is begin 

SUM <= A xor B after 8 ns; CARRY <= A and B after 4 ns; 

end HA_Archbody; 

Here a dataflow model is used where the HALF_ADDER is described using two concurrentsignal assignment. In a signal assignment statement, the symbol <= implies an assignment of avalue to a signal. The value of the expression on the right‐hand‐side of the statement iscomputed and is assigned to the signal on the left hand side called the target signal Acomputed and is assigned to the signal on the left‐hand‐side, called the target signal. Aconcurrent signal assignment statement is executed only when any signal used in theexpression on the right‐hand‐side has an event on it, that is, the value for the signal changes.

Configuration Declaration is used to select one of the possibly many architecture bodies thatan entity may have, and to bind components, used to represent structure in that architecturebody, to entities represented by an entity‐architecture pair or by a configuration, that reside ina design library Consider the following configuration declaration for the HALF ADDER entitya design library. Consider the following configuration declaration for the HALF_ADDER entity.

The first statement is a library context clause that makes the library names CMOS_LIB andMY_LIB visible within the configuration declaration. The name of the configuration isHA BINDING and it specifies a configuration for the HALF ADDER entity The next statementHA_BINDING, and it specifies a configuration for the HALF_ADDER entity. The next statementspecifies that the architecture body HA_STRUCTURE is selected for this configuration. Sincethis architecture body contains two component instantiations, two component bindings arerequired.

The first statement (for X1: . . . end for) binds the component instantiation, with label X1, to anentity represented by the entity‐architecture pair, XOR_GATE entity declaration and theDATAFLOW architecture body, that resides in the CMOS_LIB design library. Similarly,component instantiation A1 is bound to a configuration of an entity defined by theconfiguration declaration, with name AND_CONFIG, residing in the MY_LIB design library.

Package Declaration: A package declaration is used to store a set of common declarations likePackage Declaration: A package declaration is used to store a set of common declarations likecomponents, types, procedures, and functions. These declarations can then be imported intoother design units using a context clause. Here is an example of a package declaration.

The name of the package declared is EXAMPLE_PACK. It contains type, component, constant,and function declarations. Notice that the behavior of the function INT2BIT_VEC does notappear in the package declaration; only the function interface appears The definition or bodyappear in the package declaration; only the function interface appears. The definition or bodyof the function appears in a package body

Package Body: A package body is primarily used to store the definitions of functions andprocedures that were declared in the corresponding package declaration, and also thecomplete constant declarations for any deferred constants that appear in the packagep y pp p gdeclaration. Therefore, a package body is always associated with a package declaration;furthermore, a package declaration can have at most one package body associated with it

MODELING STYLESThe architectural body which determines the internal characteristics of an entity can bemodeled using different modeling styles as described below

1. As a set of interconnected components (to represent structural style), 2. As a set of concurrent assignment statements (to represent dataflow style), 3. As a set of sequential assignment statements (to represent behavioral style), f q g ( p y ),4. Any combination of the above three. 

Structural Style of Modeling In the structural style of modeling, an entity is described as a set of interconnectedcomponents. Such a model for the HALF ADDER as discussed before, is described in anp _ ,architecture body as shown below.

The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ADDER(presented in the previous section) specifies the interface ports for this architecture body. Thearchitecture body is composed of two parts: the declarative part (before the keyword begin)and the statement part (after the keyword begin). Two component declarations are present inand the statement part (after the keyword begin). Two component declarations are present inthe declarative part of the architecture body. These declarations specify the interface ofcomponents that are used in the architecture body. The components XOR2 and AND2 mayeither be predefined components in a library, or if they do not exist, they may later be bound

h i lib h d l d i i d i hto other components in a library. The declared components are instantiated in the statementpart of the architecture body using component instantiation statements. X1 and A1 are thecomponent labels for these component instantiations.

The first component instantiation statement, labeled XI, shows that signals A and B (the inputports of the HALF_ADDER), are connected to the X and Y input ports of a XOR2 component,while output port Z of this component is connected to output port SUM of the HALF_ADDERentity Similarly in the second component instantiation statement signals A and B areentity. Similarly, in the second component instantiation statement, signals A and B areconnected to ports L and M of the AND2 component, while port N is connected to the CARRYport of the HALF_ADDER.

Dataflow Style of Modeling In this modeling style, the flow of data through the entity is expressed primarily usingconcurrent signal assignment statements. The structure of the entity is not explicitly specifiedin this modeling style but it can be implicitly deduced Consider the following alternatein this modeling style, but it can be implicitly deduced. Consider the following alternatearchitecture body for the HALF..ADDER entity that uses this style.

The dataflow model for the HALF_ADDER is described using two concurrent signal assignmentt t t ( ti l i l i t t t t d ib d i th t ti ) Istatements (sequential signal assignment statements are described in the next section). In asignal assignment statement, the symbol <= implies an assignment of a value to a signal. Thevalue of the expression on the right‐hand‐side of the statement is computed and is assigned tothe signal on the left‐hand‐side, called the target signal. A concurrent signal assignmentstatement is executed only when any signal used in the expression on the right‐hand‐side hasan event on it, that is, the value for the signal changes. Delay information is included in thesignal assignment statements using after clauses.

Behavioral Style of Modeling In contrast to the styles of modeling described earlier, the behavioral style of modelingy g , y gspecifies the behavior of an entity as a set of statements that are executed sequentially in thespecified order. This set of sequential statements, that are specified inside a processstatement, do not explicitly specify the structure of the entity but merely specifies itsf nctionalit A process statement is a conc rrent statement that can appear ithin anfunctionality. A process statement is a concurrent statement that can appear within anarchitecture body. For example, consider the following behavioral model for the DECODER2x4entity.

Basic language ElementsThese include data objects that store values of a given type, literals that represent constantvalues and operators that operate on data objects Every data object belongs to a specificvalues, and operators that operate on data objects. Every data object belongs to a specifictype.

Data Objects

Data TypesData types categorically divides different forms of data to be associated with data objects.Subtypes are data types with constraints These constraints may specify a range of valuesSubtypes are data types with constraints. These constraints may specify a range of values.

Scalar Types

Composite Types

OperatorsOperators are mathematical or logical functions which give action to data objects or relate twoor more data objectsor more data objects

Logical Operators

Relational Operators

Adding Operators

Multiplying Operators

Miscellaneous Operators