How to Test Complex VLSI/SoC

2010

Sungho Kang

2

OutlineWhat is Testing? Faults, ATPG & Fault SimulationAd-HocScanLogic BIST & Memory BISTP1149.1 & P1500Conclusion

3

Determine requirements

Write specifications

Design synthesis and Verification

Fabrication

Manufacturing test

Chips to customer

Customer’s need

Test development

VLSI Implementation

4

Design Constraints

Area

Speed

Power

Testability

5

Testing Defect

Physical deviation from some specified properties

Test An experiment whose purpose is to detect the presence of detectsand to diagnose the source of defects

Byproduct of testing Reliability measurement of the product and processQuality assuranceAssistance to verification and validation

6

Testing ProcessRule of thumb: spend 5-10% die area on DFT (10% of die is state and scan is 50% overhead per state!)

7

Verification vs TestingVerification

Correctness of designSimulation, Emulation and Formal verificationPerformed once before manufacturingResponsible for quality of design

TestingCorrectness of manufactured hardwareTest generation and test applicationPerformed every manufactured devicesResponsible for quality of devices

8

Testing Costs To detect problems early (Rule of Ten)

Test Failure CostChip Test Component Failure $0.3Board Test Board Failure $3System Test System Failure $30Field Test Field Failure $300

9

Test Cost vs Manufacturing Cost

10

VLSI Chip Yield

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication processA chip with no manufacturing defect is called a good chipFraction (or percentage) of good chips produced in a manufacturing process is called the yield

WaferDefects

Faulty chips

Good chips

Unclustered defectsWafer yield = 12/22 = 0.55

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77

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Bathtub Curve

Failure Rate

Time

EarlyFailures

WearoutFailures

Infant Mortality

Working Life

Wearout

Random failure

12

Test Process

TestProcess

Parts forManufacturing Line

Bad partswhich fail Test

(BF)

Good partswhich pass Test

(GP)

Bad partswhich pass Test

(BP)

Defect Level =BP

GP + BP

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Quality of TestQuality of Test

Y : YieldDL: Defect Leveld : defect coverageDL = 1 - Y 1-d

Consider a 0.5 yield processTo achieve 0.01 defect level, 99% coverage is requiredTo achieve 80% coverage, 0.2 defect level

1.0

0.8

0.6

0.4

0.2

0.00 20 40 60 80 100

defect level (%)

fault coverage (%)

Y = 0.01

Y = 0.1Y = 0.25

Y = 0.5

Y = 0.75

Y = 0.9

Y = 0.99

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Design for TestabilityRefers to those design techniques that make test generation and test application cost-effective

Why need?Difficulty in preparing test patterns

AdvantagesTest generation is easyHigh quality testing

DisadvantagesArea overheadTiming overhead

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How Much Testing Is Enough?

40

30

20

10

0

0 20 40 60 80 100Testability of a Circuit (%)

Test Development Time as a Percentage of Total

Design Time

16

Test Costs vs Manufacturing Costs

Additional silicon areaOverhead for test purposes

costs

No specialtest provision

Total costs

Processing costs

Packaging costs

Testing costs

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Current Situation Increase of complexity

Moore’s LawNo. of transistors doubles every 18 months

Increase of speed30% increase per year

Timing and signal integrity Increase of test cost

30-40% of overall costIncrease of ATE performance

12% increase per yearTime to Market

Exhaustive testing is no good8080 takes 1020 years at one million tests per second

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Test Cost Factors

Low costexternal ATE

RF/AnalogCore

User Defined

Core

User DefinedCore

DRAM

IP

ROM

IP

IP

UDL

BIST Mem BISTTest AccessSoC Test Controller

IO Pad

IO Pad

Design for Testability

Test Equipment

TestEngineering

Test CAD Tools

TestMethodology

Spec.Design MethodologyLow Cost Test

Equipment

Efficient TestEngineering

Sound TestMethodology

AppropriateDFT

Powerful TestCAD Tools

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Manufacturing Defects

In fabrication, defects get introduced from many sources:ContaminationMetalization DefectImplant DefectWafer DefectOxide DefectInterconnect Defect

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Logical Fault ModelsGate Level Faults

Stuck-atShort between signal and ground or power

Bridging Short between two signals

Transistor Level FaultsShort

Connecting points not intended to be connectedOpen(break)

Breaking a connectionStuck-on (stuck-short)Stuck-open (stuck-off)

Delay FaultsTemporary Faults

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Single Stuck-at Fault (SSF)Only one line in the circuit is faulty at a timeThe fault is permanent (as opposed to transient)The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0)The function of the gates in the circuit is unaffected by the fault

A B C

0 0 00 1 01 0 01 1 1

Fault-Free Gate

Vcc

A

BC

Fault: A s-a-1

A B C

0 0 00 1 11 0 01 1 1

Faulty Gate

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Relative Performance of Fault Models

at-speedfunctional

slow functional

stuck-at scan

at-speedscan

0 80

0

0 5

190 22

02

4 6

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HP(1996) : 25K std. cell design, 0.8micronFull scan : 1497FFs, 33MHzFunctional pattern : 83.7% fault coverageStuck-at fault coverage : 99% with 284 patternsTransition fault coverage : 99.4% with 554 patterns

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Fault Coverage and Efficiency

Fault coverage =

Fault efficiency

# of detected faultsTotal # faults

# of detected faultsTotal # faults -- # undetectable faults=

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Fault Simulation

FaultSimulator

Circuit

FaultCoverage

FaultList

TestPatterns

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ATPG

FaultList

ATPGCircuit Tests

FaultModel

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ATPG ExampleG output s-a-1 A

BCD

E

F

G

H

J

IK

0/1

A

111

E

F

G

H

J

IK

0/1

0

0

0

Fault Excitation

X

111

F

G

H

J

IK

0/1

0

0

0

0/1

10

Fault Propagation

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Sequential ATPG

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DFT Rule Checking

Scan Design, Boundary Scan DesignMemory BIST Design, Logic BIST Design

DFT Rule CheckingStatic Timing Analysis

Test Pattern Generation

Logic SimulationTest Vector Translation

DFT Rule Checking

Full Timing Simulation

DFT Rule Checking

Test Synthesis

Verilog/VHDL Netlist

ATPG

DFT Flow

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Classification of DFTAd-Hoc Design

InitializationAdding extra test pointsCircuit partitioning

Structured DesignScan designBoundary ScanBuilt-in Self Test

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PartitioningPhysically divide the system into multiple chips or boardsOn board-level systems, use jumper wires to divide subunitsCan have performance penalties

Module 2

Module 3

Module 1System

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Test Point InsertionEmploy test points to enhance controllability and observabilityLarge demand on extra I/O pins Example

32

Sequential Circuit

FF

FF

FF

Combinational

logic

PI PO

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Adding Scan Structure

FF

FF

FF

Combinational

logic

PI PO

SCANOUT

SCANIN

Test/Normal

A MUX is added

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Automated Scan Design

Chip layout: Scan-chain optimization,timing verification

Behavior, RTL, and logicDesign and verification

Gate-levelnetlist

Scan design

rule audits

CombinationalATPG

Scan hardwareinsertion

Scan sequenceand test program

generation

Design and testdata for

manufacturing

Rule violations

Scannetlist

Combinationalvectors

Scan chain order

Mask dataTest program

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Sources of DFT Rule ViolationReset/preset violations

Controllability through PIs or disabled during testClock rule violations

Controllability/gatingTristate bus violations

Ensures there is no contentionBidirectional I/O violations

Controls direction to avoid contentionsLatch violations

Ensures transparency during test modeShift constraint violations

Ensures proper shifting of data through the scan chain

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Scan Chain ReorderingTo reduce the routing congestionsTo reduce the hold-buffer insertion during placement

May need skew-based optimization

Before After

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Built In Self Test Capability of a product to carry out an explicit test of itself

Test patterns are generated on-chipResponses to the test patterns are also evaluated on chipExternal operations are required only to initialized the built-in tests and to check the test results (go/no-go)

Pattern Generator

Logic BISTController

Response Analyzer

CUT

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Linear Feedback Shift RegisterThe state of shift register depends only on the prior state

= 1

D Q D QD QD Q

c2c1c1 cn

cn-1

Q1 Q2 Q3 Qn

a-1 a-2 a-n+1 a-n

am am-1 am-2 am-n+1 am-n

Next State

Current State

= 1

D Q D QD QD Q

c2c1c1cn

cn-1

Q1 Q2 Q3 Qn

am-1 am-2 am-nCurrent State

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LFSR ExampleCharacteristic Polynomial : 1+x2+x3

Initial condition (1,0,0) : xQ1 : x / (1+x2+x3)Q2 : x2 / (1+x2+x3)Q3 : x3 / (1+x2+x3)

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LFSR ExampleWhen initial state is 100

Q1 Q2 Q31 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 00 1 01 0 1

When initial state is 000Q1 Q2 Q30 0 00 0 0

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MISRMultiple input signature analysis

...

D Q D Q D Q D Q+ + +...Q1 Q2 Q3 Qn

Cn-2 C1Cn-1Cn

+

D1 D2 D3 Dn

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Test patterns are applied to CUT every clock cycleAdditional logic and delay are required between the input FF and CUTBILBO like type: Cannot perform compression and pattern generation concurrentlyEntire test is scheduled and divided into sessionsComplex test control unit is required

Test-per-Clock

PRPG

MISR

CUT

43

STUMPS

PRPG

Logic BISTcontroller

MISR

Scan chain

Scan chain

Scan chain

Scan chain

Self Testing Using MISR and Parallel SRSGCentralized and separate BISTMultiple scan paths

Reduction in test timeLower overhead than BILBO but takes longer to apply

44

Complete Fault CoverageHybrid test pattern generation

Combination of pseudo-random test and deterministic testDeterministic test pattern generation

Store-and-generate schemeTest set embedding scheme

Bit-flipping or Bit-fixingLFSR reseeding or multiple-polynomial reseeding

Hybrid BIST trade-off ( random deterministic)

TimeTime

Short test timeShort test timeHeavy H/W overheadHeavy H/W overhead

TimeTime TimeTime

Long test timeLong test timeLight H/W overheadLight H/W overhead

Optimal test timeOptimal test timeOptimal H/W overheadOptimal H/W overhead

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Multiple Seed / Reseeding

LFSR

CUT

MISR

Seed0Seed1Seed2

BISTController

SeedROM

Testclock

vvv

v

46

SequentialCUT

t0 t1 … ... tL-1 s0 s1 … ... sn-1

Scan chain

Bit FlippingCircuit

… ...

SignatureAnalyzer

Bit Fixing/Bit Flipping Method

Today’s SoC environments Large and complex VLSI circuitsNeed an enormous amount of test data

Limitations of ATE based test methodsChannel width and memory sizeModified or more expensive ATE must be required

Reducing test data by eliminating useful test patternsCan be reduced for the size of the ATE memory Deceases the accuracy of testing

Why Need Test Compression ?

Compress the test input sequencesNeed a decompression units to make original test sequencesCan be reduced for both limitations of ATE

The size of ATE memoryThe width of ATE channel

Can be reduced test application time

Test Compression

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Embedded Memory Testing

Source: ITRS 2001 – Percentage of Logic Forecast in SoC Design

9442352014

9098702008

7113161002005

5216321302002

2016641801999

% Area Memory

% Area Reused Logic

% Area New Logic

Node(nm)

Year

50

Memory Functional Model

51

MBIST Basic ArchitectureFault Model

Stuck-at FaultAddress Decoding FaultCoupling FaultPattern-Sensitive Fault

Memory Test AlgorithmsMarch TestCheckerboardZero-One

Embedded RAM

ModuleMUX

Normal Inputs

BIST Pattern Generation &

Response Comparison

TestOutputs

TestInputs

BISTMODE

NormalOutputs

52

Concept of Boundary ScanImprove testability by reducing the requirements placed on the physical test equipmentAlso called

• JTAG (Joint Test Action Group) Boundary Scan Standards• IEEE P1149.1

Why use it?• Testing interconnections among chips• Testing each chip• Snapshot observation of normal system data

Why testing boards?• To test board is easier than to test systems

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53

IEEE 1149.1 Device Architecture

IDCODE Register

Instruction register

Bypassregister

TAP

MUX

BS Test bus circuitry

TDO

TCK

TDI

TMS

I/O Pad Boundary-scan cell

Boundary-scan path

GlueLogic

S out

TRST

54

The Principle of BS Architecture

55

SOC Design EvolutionEmergence of very large transistor counts on a single chipMixed technologies on the same chipCreation of Intellectual Property (IP)Reusable IP-based design

Data Path

CPUCore

DSP Core

DRAM

IP Core

ROM

IP Core

IP Core

UDL

Logic BIST Memory BISTT̀est AccessBoundary Scan TAP Controller

IO Pad

IO Pad

56

IEEE P1500

57

ChipOutputs

User Defined Test Access Mechanism

Core 1

Standard P1500

Core Test Wrapper

Core N

Standard P1500

Core Test Wrapper

P1500 WIP

Wrapper control

WSO1 WSIN

WSI1 WSON

TAM-In TAM-InTAM-Out TAM-Out

TAM-Source TAM-Sink

ChipInputs

System ChipTAM Source/SinkFrom chip I/O, test bus/rail/port, BIST, etc..

TAM In/Out0 to n lines for parallel and/or serial test data, or test control

P1500 Wrapper Interface Port(WIP)From chip-level TAP controller, chip I/0, …

System Chip with P1500 Wrapped Cores

58

Test Access

No Direct Physical Access MethodTest access mechanism is required

Today’s chip is tomorrow’s core

Test Control Interface

Test Control I/F

Test Control I/F

3rd Generation Core

2nd Generation Core

1st GenerationCore

Test Access

59

Core Level Testing Summary

RF/AnalogCore

User Defined

Core

User DefinedCore

DRAM

IP

ROM

IP

IP

UDL

BIST Mem BISTTest AccessSoC Test Controller

IO P

ad

IO P

ad

Low costexternal ATE

• Memory test algorithm• Memory BIST, BISR

• Testable design

• Analog Fault modeling• Mixed signal Built-In Self Test

• Built-In Self Calibration

• Testable core design• Logic BIST• Test reuse• Hierarchical testing

• Core access architecture• Parallel access & bypass• Core isolation

• IP-system test interface

• Test spec.• Test hardware

control• Test

scheduling

• Automatic test pattern • Fault simulation• Testability measure• Scan insertion & synthesis

• BIST circuit synthesis• Boundary scan insertion & synthesis

Test Automation

60

Test ChallengesTest quality

Test cost reduction

At-speed test

Reduction of design efforts

Test design reuse