VLSI Systems Design -...

MicroLab, VLSI-31 (1/61)

JMM v1.0

VLSI Systems Design

Connection and Communication Models

Goal: You can make the link between the low level connection architectures and the higher level communication models and master their implementation. You are familiar with the most common buses and networks.


JMM v1.0

Interprocess Communication

multitasking systems need mechanisms for communication between tasksreal-time operating systems (RTOS) provide interprocess communication mechanisms in embedded systemsdefinition of „process element“ (PE):

a piece of software running on an embedded processora hardware unit executing an algorithm implemented for example as a FSM-D architecture model

interprocess communication is information exchange between „processing elements“


JMM v1.0

Blocking/Non-Blocking Communication

We distinguish between blocking and non-blocking communication:blocking communication: the process element initiating the communication goes in a waiting state until communication end.non-blocking communication: the process element initiating the communication can execute other useful tasks during an ongoing communication.both types of communication are useful.


JMM v1.0

Shared Memory Communication:test-and-set operation

two major (logically equivalent) communication styles exist:

shared memorymessage passing

shared memory communication between processing elements using bus a structuremessage is stored in communication link

need of atomic „test-and-set“ operations, else:PE 1 reads flag location and sees „not busy“PE2 reads flag location and sees „no busy“PE1 sets flag location to „busy writing“ and writes data to the shared locationPE2 erroneously sets flag „busy writing“ and overwrites the data left by PE1

PE1 PE2sharedlocation

Memory

write read


JMM v1.0

Shared Memory Communication:Semaphores

a semaphore is a language level synchronization elementwith semaphores guarded access to shared memory can be realized:

wait for semaphore: P();P() uses a test-and-set operation to repeatedly test a location that holds a memory lockrelease semaphore: V();V() resets the memory lock

...

/* non-protected memory access is here */P(); /* wait for semaphore */… /* do protected memory access here */V(); /* release semaphore */

/* non-protected memory access is here */

...


JMM v1.0

Message Passing Communication

each communication entity has its own send/receive unitmessage is stored on endpoints of send/receive unit and not in communication link as at shared memory communicationmessage passing is used at applications where units operate relatively autonomous: ex. car control system

PE1 PE2

send/receive send/receivemessage


JMM v1.0

Signals

major interprocess communication mechanisms:shared memorymessage passing

simple interprocess communication mechanism:signal

a signal does not pass data beyond its existencea signal is analogous to hardware interrupt, but can entirely be implemented in softwarea signal is generated by a process and transmitted to another process by the operating systemsignal have fairly limited functionality:

CPU exceptions to operating systemoperating system servicestermination of a process

PE1 OS/PE2

send receivesignal


JMM v1.0

Data Dependencies

communication processes that execute data exchange at identical rates:

relationship shown using data dependenciesdata dependencies define a partial ordering of process executiondirected acyclic graph (DAG): task graph

communication processes that execute data exchange at different rates:

no one-to-one relation between source and destination of data

P1

P2

P3 P4

system

video

audio


JMM v1.0

Deadlocks

US Kansas legislature law early last century:„When two trains approach each other at a crossing, both shall come to a full stop and neither shall start up again until the other has gone.“

Dealing with deadlock problem:ignoring (very popular)detection and recovering (quite popular)preventingavoiding (not applicable)

P1 P2

R1 R3

R2

P3


JMM v1.0

The Four-Cycle-Handshake

the four-cycle-handshake ensures a correct communication between two devicespredefined master/slave devices

device 1 is master and initiates communicationdevice 2 is slavesend or receive is possibledata bus is bidirectional

device 1(master)

device 2(slave)

req

ack

data

rw


JMM v1.0

The Four-Cycle-Handshake:predefined master/slave

four-cycle-handshake for data sending:

four-cycle-handshake for data receiving:

rw

req

data

ack

data data stored

data valid

requ

est

phas

e

stor

eph

ase

ackn

owle

dge

phas

e

end

phas

e

device 1

device 2

rw

req

data

ack

data

data stored

data valid

requ

est

phas

e

achn

owle

dge

phas

e

stor

eph

ase

end

phas

e

device 1

device 2


JMM v1.0

Bus Allocation

complex SoC may have sharable resources:memoriesprocessing elementsI/O devicesbuses

bus allocation principles:allocation on a fixed time schedulebus allocation on the basis of need

destructive bus allocation (Ethernet: Carrier Sense Multiple Access with Collision Detection CSMD/CD, ...)non-destructive bus allocation (arbitration)


JMM v1.0

Bus Arbitration Algorithms

arbitration is the method to grant the bus to a requesting masterarbitration schemas:

fixed priority (or rate-monotonic) algorithmround robin algorithm

A B C D E F G H

priorities 8 7 6 5 4 3 2 1

top priority

A B C D E F G H

priorities 8 7 6 5 4 3 21


JMM v1.0

Typical Processor Bus

a bus is a collection of wires as well as a protocolmicroprocessor buses build on handshake protocolbasic bus operations are reading and writingsystem clock helps to increase data transfer speed

processingelement(CPU)

device 1

clockr/waddr enaddrdata rdydata

device 2

clock

r/w

addr en

addr

data rdy

data valid

addr valid addr valid

valid

waitstate

read write


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Bus With DMA Controller

direct memory access (DMA) controllers perform direct data transfers between devices without CPU involvementfour-cycle-handshake with processor to get bus master (interrupt processor when finished)used for high speed requirementsto prevent to block the processor too long, partial block transfer mode possible, 16, 32 or 256 words for example. bus DMA controller is a bus with 2 masters

processingelement(CPU)

DMAcontroller

clockr/waddr enaddrdata rdydata

device 1

busrequest

busgrant

device 2


JMM v1.0

System Bus

embedded systems-on-chip use bus hierarchies:Avalon from Altera Inc., used for Nios (simple)AMBATM bus from AMD Inc., used for ARMTM

CoreConnectTM from IBM Inc., used for PowerPCTM

features:high-speed buses provide wider data connectionshigh-speed buses require more expensive circuitry and connectors. The cost of low-speed devices can be held down by using lower-speed, lower-cost bus.The bridge may allow the buses to operate independently, thereby providing some parallelism in processing an I/O operations.

bus bridge: slave at fast bus, master at slow bus

CPU

memoryhigh-speedprocessing

element

brid

ge

low-speedI/O device

low-speedprocessing

element

high-speed bus low-speed bus


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The AMBA System Bus

advanced high-performance bus (AHB)high-performancepipelined operationmultiple bus masterburst transfersplit transactions

advanced high-performance system bus (ASB)dito, but no split transactions

advanced peripheral bus (APB)low-powerlatched address and controlsimple interfacesuitable for many peripherals

CPU

on-chip RAM(high-

bandwidth)

processingelement

(high-speed)

brid

ge

UART

AHB or ASB APB

DMA

Timer

PIO Keypadexternalmemoryinterface

(high-band-width)


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Advanced High-Performance Bus (AHB)

The AHB bus consists of the following elements:

AHB master: able to initiate read and write transfersonly one bus master is allowed to control the bus

AHB slave:responds to read and write operations in a given address spacesignals back to the master: success, failure or waiting of the data transfer

AHB arbiter:ensures that only one master at a time is allowed to control busany arbitration algorithm can be used, like highest priority, fair access, etc

AHB decoder:decodes address and generates device select signalssingle centralized decoder is required


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Basic AHB Interconnection Schemaarbiter determines bus mastercentral multiplexor schemacentral decoder for read dataadditional characteristics:

single cycle bus master handoversingle clock edge operationnon-tristate implementationwider data bus configuration (64/128 bits)

master# 1

HADDR

HWDATA

HRDATA

master# 2

HADDR

HWDATA

HRDATA

master# 3

HADDR

HWDATA

HRDATA

slave# 1

HADDR

HWDATA

HRDATA

slave# 2

HADDR

HWDATA

HRDATA

slave# 3

HADDR

HWDATA

HRDATA

slave# 4

HADDR

HWDATA

HRDATA

arbiter

decoder


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Basic AHB TransferPhases:

address & control phaseone or more data phase

Slave can delay transfer with HREADYaddress source is master: HADDR[31:0]data source for write operations is master: HWDATA[31:0]data source for read operations is slave: HRDATA[31:0]

HCLK

HADDR[31:0]

control

HWDATA[31:0]

HREADY

HRDATA[31:0]

A B C D

ctrl A ctrl B ctrl C ctrl D

data A data B data C

A B C

addr phase (A)

data phase (A)


JMM v1.0

AHB Transfer ExampleMaster shows transfer type with HTRANS[1:0]

IDLE (“00“): no data transfer is requiredBUSY (“01“): master is delaying an ongoing transferNONSEQUENTIAL (“10“): first transfer of a burst or single transferSEQ (“11“): remaining transfers of a burst

Delaying transfermaster delays transfer with HTRANS[1:0]slave delays transfer with HREADY

incremental burst of unspecified length is shown

HCLK

HTRANS[1:0]

HADDR[31:0]

HBURST[2:0]

HWDATA[31:0]

HREADY

HRDATA[31:0]

C1

NONSEQ BUSY SEQ SEQ

C2 C3 C4 C5 C6

SEQ SEQ

C7 C8

0x20 0x24 0x24 0x28 0x2C 0x30

INCR

data0x20

data0x24

data0x28

data0x2C

data0x30

data0x20

data0x24

data0x28

data0x2C

data0x30


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AHB Transfer Example(4-beat wrapping burst)

Master defines bus operation with HBURST[2:0]SINGLE (“000“): single transferINCR (“001“): increment burst of unspecified lengthWRAP4 (“010“): 4-beat wrapping burstINCR4 (“011“): 4-beat incrementing burstWRAP8 (“100“): 8-beat wrapping burstINCR8 (“101“): 8-beat incrementing burstWRAP16 (“110“): 16-beat wrapping burstINCR16 (“111“): 16-beat incrementing burst

Burst must not cross 1kB address boundary

data0x38

data0x3C

data0x30

data0x34

data0x70

data0x72

HCLK

HTRANS[1:0]

HADDR[31:0]

HBURST[2:0]

HWRITEHSIZE[2:0]

HPROT[3:0]

HWDATA[31:0]

HREADY

HRDATA[31:0]

NONSEQ SEQ SEQ SEQ

0x38 0x3C 0x30 0x34

WRAP4

data0x38

data0x3C

data0x30

data0x34

control for burst, SIZE=word

NONSEQ SEQ

0x70 0x72

INCR

SIZE=halfword

data0x70

data0x72


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AHB Transfer Example with Responseslave can complete a transfer in a number of ways:

complete the transfer immediatelyinsert wait statessignal an error to indicate transfer has faileddelay the completion of the transfer, but allow master/slave to back off bus

slave shows status of transfer with HRESP[1:0] in combination with HREADY

OKAY: transfer is progressing normallyERROR: transfer has been unsuccessfulRETRY and SPLIT: both indicate that transfer cannot complete immediately

ERROR, RETRY and SPLIT are at least two-cycles

HCLK

HTRANS[1:0]

HADDR[31:0]

HWDATA[31:0]

HREADY

HRESP[1:0]

SEQ IDLE

C6 C7 C8

B+4 B

dataB

RETRY RETRY

C1

OKAY ERROR ERROR

NONSEQ SEQ IDLE

A

dataA

C2 C3 C4 C5

A+4

NONSEQ NONSEQ

OKAY

B


JMM v1.0

AHB Bus Arbitrationsignals for bus arbitration:

HBUSREQx: master sends bus request HGRANTx: arbiter issues bus grantHMASTER[3:0]: arbiter issues bus master numberHLOCKx: master may request bus lockHMASTLOCKx: arbiter issues bus lock grant signal

arbiter can terminate non size-limited bursts earlymaster can require locked accessif a master looses bus access in the middle of a burst it must re-assert HBUSREQx to regain access

HCLK

HBUSREQ_M1

HBUSREQ_M2

HGRANT_M1

HGRANT_M2

HMASTER[3:0]

HTRANS[1:0]

HADDR[31:0]

HWDATA[31:0]

HREADY

M2

C6 C7 C8

SEQ

C1

M1

C2 C3 C4 C5

NONSEQ SEQ SEQ NONSEQ

dataA

dataA+4

dataA+8

dataA+12

A A+4 A+8 A+12 B

IDLEIDLE

Mx


JMM v1.0

AHB Address Decoder Schematicslaves sample HSELx when HREADY is activeminimum address space allocated to a slave is 1kBif system does not contain complete memory map, default slave (decoder) should respond to wrong addressesaccess attempt to nonexistent location will be answered by default slave:

ERROR response to NONSEQUENTIAL or SEQUENTIALzero wait state OKAY response to IDLE or BUSY

Master determines transfer size with HSIZE[2:0]“000“: size is byte“001“: size is half-word“010“: size is word...“111“: size is 32 bytes

master# 1 HADDR_M1[31:0]

master# 2

slave# 1

HADDR

slave# 2

slave# 3decoder

HADDR_M2[31:0]

HSEL_S1

HSEL_S2

HSEL_S3


JMM v1.0

AHB Interface Diagrams

select HSELxHADDR[31:0]

HWRITEHTRANS[1:0]

HSIZE[2:0]HBURST[2:0]

HWDATA[31:0]HRESETn

HCLKHMASTER[3:0]

HMASTLOCK

addressandcontrol

dataresetclock

HREADYHRESP[1:0]

HRDATA[31:0]

HSPLIT[15:0]

AHBslave

split-capableslave

data

transferresponse

arbitergrant

HGRANTx

HREADYHRESP[1:0]

HRDATA[31:0]

HRESETnHCLK

transferresponse

data

resetclock

HBUSREQxHLOCKxHTRANS[1:0]HADDR[31:0]HWRITEHSIZE[2:0]HBURST[2:0]HPROT[3:0]HWDATA[31:0]

AHBmaster address

andcontrol

arbiter

transfertype

data

arbiterrequestsand locks

HBUSREQx1HLOCKx1

HBUSREQx2HLOCKx2

HADDR[31:0]HSPLITx[15:0]HTRANS[1:0]HBURST[2:0]

HRESP[1:0]HREADY

HRESTEnHCLK

addressandcontrol

resetclock

HGRANTx1HGRANTx2

HMASTER[3:0]HMASTLOCKAHB

arbiter

arbitergrants

HRDATA[31:0] HSELx1HSELx2

AHBdecoder selectaddress


JMM v1.0

AHB-Lite

AHB-Lite is a subset of full AHB specificationsonly one bus masterthus no request/grant protocol for arbiterthus no split or retry response from slaves

AHB-Lite enables faster design and verificationcompatibility:

full AHB master can be used in AHB-Lite systemAHB slaves can be used in AHB-Lite system, if they do not support split and retryAHB-Lite slaves can be used in full AHB system

master

slave #3

slave #2

slave #1


JMM v1.0

Advanced Peripheral Bus (APB)

the APB is a low-power extension to the AHB/ASBAPB appears as a local secondary bus encapsulated as a single AHB/ASB slave device

APB bridge acts as slave and handles necessary handshake control and bus retimingAPB bridge proves latching of all addresses, control and data

APB should be used to handle low-bandwidth devicesAPB slave devices have following characteristics:

address and control valid throughout the access (non-pipelined)zero-power interface during non-peripheral bus activitytiming can be provided by decode with strobe timing (un-clocked interface)write data valid for the whole access (allowing glitch-free transparent latch implementation)

CPU

high-bandwidth

on-chip RAM

high-speedprocessing

device

brid

ge

UART

AHB or ASB APB

DMA bus master

Timer

PIO Keypadhigh-band-width

externalmemoryinterface


JMM v1.0

APB Basic Transfers

write transfer

PCLK

PADDR[31:0]

PWRITE

PSEL

PENABLE

PWDATA[31:0]

C1

addr A

C2 C3 C4

data A

IDLE SETUP ENABLE IDLE

PCLK

PADDR[31:0]

PWRITE

PSEL

PENABLE

PRDATA[31:0]

C1

addr A

C2 C3 C4

data A

IDLE SETUP ENABLE IDLE

read transfer


JMM v1.0

APB Interface Diagrams

recommended to implement APB data bus asmultiplexed or OR-bus schema tri-state is possible but not recommended

PRDATA[31:0]

PRESETnPCLK

data

resetclock

PSEL1PSEL2

PENABLEPADDR[31:0]PWRITEPWDATA[31:0]

APBbridge

address &control

selects

strobe

write data

PSELxPENABLE

PADDR[31:0]PWRITE

PWDATA[31:0]

PRDATA[31:0]

PRESETnPCLK

data

resetclock

PRDATA[31:0]

APBslave

read data

selectstrobe

address& control


JMM v1.0

Read Transfer from AHB to APB

HCLK &PCLK

HADDR[31:0]

HWRITE

HRDATA[31:0]

HREADY

PADDR[31:0]

PWRITE

PSEL

PENABLE

PRDATA[31:0]

C1

addr A

C2 C3 C4

data(A)

addr A addr A+4 addr A+8 addr A+12

data(A)

data(A+4)

data(A+8)

addr A+4 addr A+8 addr A+12

addr A+12

C5 C6 C7 C8 C8

data(A+12)

data(A+4)

data(A+8)

data(A+12)

for a write transfer the data can be latched when:risinf edge of PCLK, when PSEL is highrising edge of PEANBLE, when PSEL is high


JMM v1.0

AMBA Test InterfaceAMBA test philosophy allows individual modules in the system to be tested in isolation

modules are designed to be tested by bus transfers onlytest harness provides access to inputs/outputs of modules not already connected to bus

dedicatedmodule

inputs

dedicatedmoduleoutputs

applicationmodule

bus interfaceteststimuli

testresults

AMBA bus

Test InterfaceController

(TIC)

ExternalBus

Interface(EIB)

TCLK

TRE

QA

TRE

QB

TAC

K

cont

rol

addr

ess

data

TBU

S[3

1:0]

AMBA bus


JMM v1.0

AMBA Test Interface Write Cycle

test control signals during normal operation

test control signals during test mode

TREQA TREQB TACK description0 0 0 normal operation1 0 0 enter test mode request- - 1 test mode entered

TREQA TREQB TACK description- - 0 current access incomplete1 1 1 address, control or turnaround vector1 0 1 write vector0 1 1 read vector0 0 1 exit test mode

HCLK

TREQA

TREQB

TACK

TBUS[31:0]

HTRANS[31:0]

HADDR[31:0]

control

HWDATE[31:0]

HREADY

C6 C7 C8C1 C2 C3 C4 C5

dataA

HBURST[2:0],HWRITE,HSIZE[2:0],HPROT[3:0]

addr write1 addrwrite2 write3

IDLE NONSEQ IDLESEQ SEQ

A A+4 A+8

dataA+4

dataA+8

C9


JMM v1.0

Introduction to Networks

motivation for distributed embedded systems:if processing tasks are physically distributed, processing power can be implemented there (eg. automotive)data reduction by signal pre-processing for data reduction (eg: finger print feature recognition)modularity by encapsulating processing operations and not using local system bus

interprocess communicationin SoC shared memory is often usedin distributed system networks shared memory is not available

sensor/actuatorPE #1

32-bitRISCPE #2

DSPPE #5

SoCPE #6

network

32-bitRISCPE #3

sensor/actuatorPE #4


JMM v1.0

Switching-Based Architecturescrossbar:

higher bandwidth compared to bus-based architecturesmajor drawback is its expense

PEout1

PEin1 PEin2 PEin3 PEin4

PEout2

PEout3

PEout4

crosspointswitch

omega:higher bandwidth compared to bus-based architectures, but lower than crossbarmore expense than bus, but less expensive than crossbar

PEout1 PEin1

PEin2

PEin3

PEin4

PEout2

PEout3

PEout4 2 x 2 switch


JMM v1.0

OSI Network Abstraction Model

open system interconnection reference model (OSI)OSI defines communication formats, contents and meanings:

connection-oriented protocol: first connection is established and possibly protocol negotiatedconnectionless protocol: no setup necessary, message directly transmitted

for modularization/encapsulation 7 layers are defined in OSI:

application

presentation

session

transport

network

data link

physical

end-user interface

data format

application dialog format

connections

end-to-end service

reliable data transport

mechanical, electrical

7

6

5

4

3

2

1

process A

application

presentation

session

transport

network

data link

physical

process Bmachine #1 machine #2


JMM v1.0

The OSI Layer Message

each layer has its own protocol that can be changed independently of the other ones

technology improvement

this independence makes layer protocols attractivethe collection of protocols in a particular system is called protocol stack

data link layer header data link layer trailernetwork layer header

transport layer headersession layer header

presentation layer headerapplication layer header

message

bits that actually appear on the network


JMM v1.0

The OSI Layers

The Physical Layer:basic property of interface, mechanical, electrical and bit exchange procedure

The Data Link Layer:primary purpose is error detection and correctiongroup bits into frames, appends checksum

The Network Layer:end-to-end data transmission by routing

The Transport Layer:defines connection-oriented servicesbreaks message into packets, and guarantees delivery of whole message

The Session Layer:enhanced version of transport layeradds checkpoints for crash handling

The Presentation Layer:defines data exchange formats

The Application Layer:collection of miscellaneous protocols like email, file transfer, etc


JMM v1.0

The Client-Server Model

protocol overhead in OSI might be to high for LAN: traversing half a dozen layers up and down (acceptable for WAN)client-server model structures the cooperating processes:

server: processes who offer services to usersclient: processes who consumes services

use of connectionless request/reply protocolprimary advantage:

simplicity: no connection has to be established, reply message serves as acknowledgeefficiency: protocol stack is shorter, only 3 OSI levels are necessary

client

µkernel

server

µkernel

request

reply

network

layer765 request/reply432 data link1 physical


JMM v1.0

Buffered vs. Un-Buffered Message Passing: Mailbox

un-buffered message passingreceive has to be issued before send primitive

buffered message passing: mailboxserving processes install mailbox before using it

client

µkernel

server

µkernel

network

addr

address refersto a mailbox

client

µkernel

server

µkernel

network

addr

address refersto a process


JMM v1.0

Reliable Message Passing

different approaches to reliable message passing:assume the message passing is unreliable (e.g. post office)reliable message passing using separate acknowledgement (compare four cycle handshake)

reliable message passing using acknowledgment principle

client

µkernel

server

µkernel

1st request2rd reply/ACK

network

3rd ACK

client

µkernel

server

µkernel

1st request3rd reply

network

4rd ACK2nd ACK

layer765 request/reply4 transport32 data link1 physical


JMM v1.0

The I2C Bus: Physical Layerpopular for initialization & command word exchange between uP and peripherals like MP3, AD, smart sensor, small EEPROM, etcserial bi-directional 2-wire busmulti-master/slave operationopen drain/open collector lines

structure of an I2C bus system

physical layer

master #1transmitter& receiver

master #2transmitter

slave #1transmitter& receiver

slave #2receiver

SCLSDA

SCL

assert clockclock input

SDA

assert datadata input

I2C driver


JMM v1.0

Level Shifter for I2C Bus (Physical Layer)

due to chip technology scaling single supply voltage is rarely seen todaynetworks connecting devices of different voltage sections thus need level shifters

3.3V I2Cdevice

3.3V I2Cdevice

5V I2Cdevice

5V I2Cdevice

SCL1

SDA1

VDD1=3.3V VDD2=5V

SCL2

SDA2

s dg

s dg

lower voltage section higher voltage section


JMM v1.0

Multiple Level Shifter for I2C Bus(Physical Layer)

multiple power suppliespower down of supply sections possiblemodular and extendable

3.3V I2Cdevice

3.3V I2Cdevice

SCL1

SDA1

VDD1=3.3V

s dg

s dg

lower voltage section

5V I2Cdevice

5V I2Cdevice

SCL2

SDA2

VDD2=5V

sdg

sdg

higher voltage section

VDD3 = max(VDDi)


JMM v1.0

I2C Bus: Data Link Layer

transmitting one byte(start) - byte - acknowledge – (stop)

who activates the bus lines

SCL

SDA MSB

startcondition

stopcondition

ack8-bit byte

SCLmaster

MSBSDAtransmitter

SDAreceiver

transmitter stays off the busduring acknowledgement

acknowledgementsignal from receiver

trasnsmittertakes bus(data or stop)


JMM v1.0

I2C Bus: Data Link LayerTransfer Formats

master write format (2 data bytes)

master read format (2 data bytes)

2 succeeding master write formats

7-bit slave address

Start addr Write Ack data Ack data Ack Stop

“0“can be repeated n times

7-bit slave address

Start addr Read Ack data Ack data NAck Stop

“1“can be repeated n times

can be repeated n times

Start addr Write Ack data Ack Start addr data Ack Stop

no proceeding Stop condition


JMM v1.0

The CAN Bus

Control Area Network (CAN): ISO 11898 standardhigh-integrity serial data communications bus for real-time applications operates at data rates of up to 1 Mbit/secexcellent error detection and confinement capabilities originally developed by Bosch for use in cars, now being used in many other industrial automation and control applicationsfeatures:

message prioritizationguarantee of latency timeerror detection and signaling, automatic retransmission of corrupted messagesmulti-master






JMM v1.0

The CAN BusOSI Layer Structure

physical layer not defined in CAN protocol but in ISO 11898

data link layerobject layertransfer layer

Application Layer

Data Link Layer

(Object Layer)-message filtering-message and status handling

(Transfer Layer)-fault confinement-error detection and signaling-message validation-acknowledgement-arbitration-message framing-transfer rates and timing

Physical Layer

-signal level and bit representation- transmission medium


JMM v1.0

CAN: Physical Layerapplication domain specific electrical characteristics

voltage levels for automotive applications up to 36V

wired-AND logic on CAN bus linesseparation between CAN controller an transceiver often seen

transceiver

C_H

C_L

CANcontrollernode #n

Vdiff

Vgnd_n

Vdd_n

transceiver

CANcontrollernode #m

Vgnd_m

Vdd_m

bustermination

CAN bus

buspull-upCAN bus

Vdd

CANcontrollernode #2

CANcontrollernode #1

2-wire differential lines (up to 1 Mbaud)

single wire line (only 33.3 kbaud)


JMM v1.0

CAN Network:Data Link Layer

principles of data exchangeno nodes are addressedcontent-oriented addressing schema:- identifier of message content (unique in network)- identifier defines priority

CAN node #1

(receiver)

select

receivemessage

accept

CAN node #2

(transceiver)

CAN node #3

(receiver)

select

receivemessage

accept

CAN node #4

(receiver)

select

receivemessage

CAN bus

sendmessage

prepare


JMM v1.0

CAN Network: Data Link LayerBus Arbitration

bus allocation:fast data transmission asks for fast bus allocationnon-destructive bitwise arbitrationidentifier defines arbitration prioritywired-AND priority: low value means high priorityCSMA/AMP: Carrier Sense Multiple Access with Arbitration on Message Passing

CAN bus

CANnode #1

CANnode #2

CANnode #3

CAN bus

node #1

node #2

node #3

node #1loses

node #3loses


JMM v1.0

CAN Network: Data Link LayerMessage Frame Formats

CAN supports two message frame formats:standard (CAN 2.0A): 11 bit identifierextended (CAN 2.0B): 29 bit identifier (11 + 18 bit)

RTR: remote transmission requestr0: reserved

inter-framespace

star

t arbitrationfield

controlfield

datafield

CRCfield ack

field

1 12 6 0 to 64 16 2 7

iden

tifie

r

RTR

bit

data

leng

thco

deiden

tifie

rex

tens

ion

r0 AC

K s

lot

AC

K

delim

iter

Standard Data Frame

end offrame

interframespace

11 1 1 1 4 1 1

CR

C fi

eld

CR

C

delim

iter

15 1


JMM v1.0

CAN Network: Data Link LayerError Handling

detecting and signaling errors:CRC: x15+ x14+ x10+ x8+ x7+ x4+ x3+1frame checkACK check

error detection at bit level:monitoring: each transmitter checks locally send signalsbit stuffing: after 5 identical consecutive bits the sender adds one complementary bit which will be removed by the receivers (used for bit synchronization)

error handling:if error is detected, the current transmission is aborted by sending an „error flag“sender automatically re-attempts transmission

CAN distinguishes between sporadic and permanent errors and thus localizing node failures (statistical assessment)

automatic switch off failure nodes is possible


JMM v1.0

The CAN Bus:Time Triggered CAN

event and time triggered protocoltime division multiplexed access (TDMA)reference message

send by time master control unit4 bytes for global time, 4 bytes for message

exclusive windowreserved for one particular CAN message only

arbitration windowone arbitrationarbitration losers: retransmitting is disabled

free windowreserved for future TTCAN expansion

referencemessage

exclusivewindow

arbitrationwindow

freewindow

exclusivewindow

Basic Cycle

referencemessage


JMM v1.0

Ethernet

widely used as local area network for general purpose computingCarrier Sense Multiple Access with Collision Detection (CSMA/CD)non synchronized busexponential backoff limits bus overload at high demand factorsmaximum length defined by nodes ability to detect collisions.

senderreceivernode # 1




0 1 2 3# of attempts

wait time

exp weightingfactor

randomditheredtimes

preamble startframe

destinationaddress

sourceaddress

length data padding CRC


JMM v1.0

InternetInternet Protocol (IP)

protocol on OSI network levelconnectionless, packet-based communicationreal-time performance is hard to predict, except within embedded systems by simulation

relationship between IP and network layersIP packet structure

service stack

appliation...transportnetworkdata linkphysical

appliation...transportnetworkdata linkphysical

networkdata linkphysical

IP

node A node Brouter

FTP HTTP SMTP Telnet SNMP

TCP UDP

IP

transmission control protocolfile transfer protocolhypertext transport protocolsimple mail transfer protocoluser datagram protocolsimple network management


JMM v1.0

Network-Based DesignCommunication Analysis

design tasksscheduling computations and assigning them to PEsscheduling and allocating communication

message delayno contention: tm = tx + tn + tr

tx transmission delay, tn network transmission time, trreceiver side overheadwith contention: ty = td + tm

td network availability delay

contention:fixed-priority: network may be blockedfair arbitration (round-robin): td = N(tx+tarb)


JMM v1.0

Network-Based Design 1Example

Example: adjusting messages to improve network delay

P1 is allocated to PE1, P2 to PE2, and P3 to PE3processes and transmission times are 4 time units

simple implementations:

implementation with rescheduling:

P1

P2

P3

d1

d2

PE1 PE2 PE3

P1

P2

d1 d2

P3

PE1

PE2

PE3

network time

0 5 10 15 20

d1d2d1d2d1d2d1d2

d3 d3 d3 d3

P1

P2

PE1

PE2

PE3

network time

0 5 10 15 20


JMM v1.0

System Performance Analysis

no interference

interference between tasksdata dependency from P1 to P2 translates uncertainty in execution time of P1 to start of P2co-allocation of P2 and P3 to PE2 means that variations of start of P2 affects completion time of P3data dependency from P3 to P4 translates variations of completion time of P3 to start time of P4

P1 P2ntx

tp1 tp2

tp1+ntx+tp2

PE1

P1

PE3

P4

PE2

P2P3


JMM v1.0

Hardware Platform Design,Allocation & Scheduling

use only as much hardware as is necessarychoices:

number and types of PEsnumber and types of networks

procedure to construct scheduling and allocation:for I/O intensive systems start with I/O devices

inventory required I/Oprocessing with I/Os with short deadlines may need local processing, other I/O can be attached with simple interfacesdetermine which devices can share PE or networkanalyze communication times to determine whether critical communication may interfere with each otherallocate minimum required PE to go with each I/Odesign the rest of the system shown as below

for computing-intensive systems start with processesstart with task with shortest deadlineanalyze communication times to determine whether critical communication may interfere with each otherallocate lower-priority tasks to shared PEs where possible


JMM v1.0

Exercises: VLSI-31

Ex vlsi31.1: (difficulty: easy, short time): Assume that our I2C bus runs at 200kbits/s and we need to send one 2 data bytes. Some of the instructions in the transmitter and receivers drivers – namely the loops that send/receive bytes will run concurrently with the message transmission. If we assume that 20 instructions outside the loops are executed by the transmitter and receiver, overheads on a 20 MHz microcontroller have to be taken into account. Calculate the total message delay.

Result: start bit + address byte + ack + data byte + ack + data byte + ack + stop bit; tm=147µs

VLSI Systems Design -...

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