Jaeyong Chung

System-on-Chips (SoC) Laboratory

Incheon National University

VLSI-I

Lecture 5

IDEC MPW 실습 (FrontEnd)

http://esc.inu.ac.kr/~portal/pdk_docs/MPW%EC%84

%A4%EA%B3%84%EA%B5%90%EC%9C%A1_201

7_%EC%8B%A4%EC%8A%B5.pdf

Use saturn server

Set ENV variables properly export PACKAGES=/usr/local/packages/synopsys

export

PATH=$PATH::$PACKAGES/icc/bin:$PACKAGES/primetime/bin:$PACKAGES/hspice/

hspice/bin:$PACKAGES/vcs/bin:$PACKAGES/design_compiler/bin

export LM_LICENSE_FILE=27020@saturn

export VCS_HOME=/usr/local/packages/synopsys/vcs

Prepare your local directory for this lab cp –r /soc/vlsi/PDK/IDEC_MPW_EDU_2017/2017_MPW_Edu_web_release/

your_local_directory

Chung VLSI 2

Design

Chung VLSI 3

Library Setup

Chung VLSI 4

Will use Magnachip/SK Hynix 180nm

Start Design Compiler

Chung VLSI 5

TCL Script for DC

Chung VLSI 6

Linking Error

Chung VLSI 7

To compile library, use the following new DC:

/usr/local/packages/synopsys/dc_2017/syn/N-2017.09-

SP3/bin/dc_shell-xg-t

To use this library, we should use the new DC from

now on

Timing Constraints

create_clock -period 12 -name MAIN_CLOCK -

waveform {6 12} [get_ports CLK]

Chung VLSI 8

Compile

Chung VLSI 9

<Units> (defined in the library)WNS: nsTNS: nsAREA: um^2LEAKAGE Power: nW

Static Timing Analysis

Chung VLSI 10

CLOCK

D Q D Q

Launch Path

Capture Path

LD

CD

Setup Check

cL ckc loTD D

Timing Report by Design Time

Chung VLSI 11

dc_shell> report_timing

I/O Timing Requirements

Chung VLSI 12

Power Reports in DC

Chung VLSI 13

dc_shell> report_power

Area Reports in DC

Chung VLSI 14

3800um x 3800um = 14,400,000 um^2

Gate count

Mapped Netlist

Chung VLSI 15

http://esc.inu.ac.kr/~portal/pdk_docs/m18gm180s_typ_081128.pdf