Gallium Nitride Based Power Electronic Devices and Converters · 2016-01-07 · Gallium Nitride...

Gallium Nitride Based Power Electronic

Devices and ConvertersNPEC 2015, Session 17, Tutorial 3,

DC-DC Converters Based on Silicon and GaN Devices

Dr. G NarayananEE Dept., IISc

Bangalore

DC-DC Converters Based on Silicon and GaN Devices

DC – DC Buck Converter

A buck converter comprises of:

• A switching network that produces a pulsed voltage waveform

• Passive elements (L and C) for filtering purpose

Ideally, no energy loss in switches, L and C

Power switching converters are quite efficient

GaN devices expected to improve the efficiency furtherGaN devices expected to improve the efficiency further

Pulsed Voltage Applied Without Filtering

For a resistive load, current waveform has the same shape as the

voltage waveform

Current waveform is not smooth and has a high ripple content

Filtering is required

Inductive Filter

• With an inductive filter, the current waveform is smoother and has less

ripple content.

• Average voltage across L is zero. The entire average voltage gets

applied across the load.

• Considerable portion of the ripple voltage in the applied waveform is

dropped across the inductor.

LC Filter

Capacitor C across the load provides a path for the ripple current

through L

Mainly DC current flows through the load; the ripple current through L

is triangular

For an acceptable ripple, L and C reduce with increase in switching

frequency

Single-Pole Double-Throw Switch for Buck

Conversion

The load (with filter) should be connected directly across the dc

source during one interval.

The load should be shorted in the other interval.

A single-pole double-throw (SPDT) switch is required.

DC-DC Buck Converter with a Generic Single-

Pole Double-Throw switch

Transistor is switched on and off with certain duty ratio D at a frequency f

Diode comes into conduction (freewheels) when the transistor is turned off

Conduction and switching losses in transistor and diode; total device loss

determines heat sink size

If switching energy loss is lower, switching frequency could be higher.

Higher the switching frequency, lower the filter size

Synchronous Buck Converter

Two transistors are switched in a complementary fashion

Forward conduction loss in the first switch, reverse conduction loss in the second

switch, switching losses in both; device loss decides heat sink size

If switching energy loss is lower, switching frequency could be higher.

Higher the switching frequency, lower the filter size

Voltage Buck Converter is a Current Boost

Converter

VIN IIN = VOUT IOUT OR VOUT / VIN = IIN / IOUT

A Current Buck Converter

Voltage Boost Converter

++

iIIN P T2L

VOUT

-

VIN

-

C

T1

Electronic Realization of the SPDT Switch in

Boost Converter

An Ideal Switch

• No voltage drop during conduction (forward drop)

• No leakage current in blocking state

• Instantaneous transition between on and off statesstates

• No energy loss since either voltage or current is always zero

• True for on-state, off-state and also switching transitions

Wish List for Any New Device

• Reduced forward conduction drop

• Leakage current and blocking state loss should continue to be negligible

• Faster device turn-on and turn-off under inductive switching condition

• Reduced switching energy loss for every transition• Reduced switching energy loss for every transition

• Reduced total power loss in the active device

• Compatible diode with low forward drop and reverse recovery loss

• OR, low reverse conduction drop of the device

List of GaN High Electron Mobility Transistors (HEMT)

and their Si Counterparts

A. Pal, “Study on GaN based power semiconductor devices…”, ME Project

Report, IISc, June 2015.

Comparison of commercial Si and GaN (normally off)

devices

Source: A. Pal and G. Narayanan, “A survey on commercially available GaN based

power electronic switches and GaN-based high-performance dc-dc converters,”

Technical Report, URL: www.nampet.in

Comparison of commercial Si and GaN (normally off)

devices – contd.

Source: Same as before

Device capacitances and charges are greatly reduced with GaN; hence lower switching

transitions times and higher switching frequency (500 kHz – 2 MHz)

Loss in transistor and diode in dc-dc buck

converter

2

, ( )

(1 )

T o DS on on off sw in DSS

D o D rr sw

P DI R E E f V I

P D I V E f

= + + +

= − +

GaN device has marginally lower Rds, very low Eon and GaN device has marginally lower Rds, very low Eon and

Eoff, significant leakage current Idss, and high reverse

conduction drop

Advantages: Very low Eon and Eoff; very fast switching

transitions; higher switching frequency; smaller filter

components

Typical switching transitions

t

v

i

Instantaneous power

loss is v*i

Peak instantaneous

power = V*I

Energy loss is area

under product curve

v

i

t

Energy loss depends on

V, I and transition times

Low transition times for

GaN

Gate-charge characteristic

Turn-on transition – device voltage and

gate voltage

Anirban Pal, “Study on GaN based power semiconductor devices …”, ME

Project Report, IISc, June 2015.

Turn-off transition – device voltage and gate

voltage

Size and packaging of GaN

• Dimensions are in mm as opposed to cm

• Impressive size reduction

• Land grid array (LGA) package

• Fingers to be connected at • Fingers to be connected at board level

• Package is more complicated to handle at board level

• PCB and related technologies required are more challenging

From device datasheet

Heat flow paths and thermal equivalent circuit

for GaN device

• Some heat flows out through the Si substrate

• Rest (most) of the heat flows down through solder bars

• Heat gets spread over the drain and source pads in the PCB.

(PCB is the heat sink!)

• Heat spreads to other PCB layers through epoxy and/or vias

• Heat finally gets convected into atmosphere

Thank you!

Questions?Questions?

Gallium Nitride Based Power Electronic

Devices and ConvertersNPEC 2015, Session 17, Tutorial 3,

Practical GaN based DC-DC Converter

V ChandrasekarPower Electronics Group

CDAC-Thiruvananthapuram

[email protected]

Practical GaN based DC-DC Converter

Outline of Presentation

• Introduction to DC-DC Converter system

�Requirement of SMPC

�Challenges in GaN Based SMPC

�Selection of components�Selection of components

• Recommended Layout practices

• Specification and schematics

• Performance Evaluation

• Demonstration of a DC-DC converter system

Requirement of SMPC

Recent Trends in SMPC are

�High Power density

�Performance Enhancement with Device materials

�Packaging of Converters

Operate stably at Higher Voltage,at Higher temperature &at High frequency

No harm to Human body( no hazardous materials )

SMPC

Packaging of Converters

Yole & NIT Japan

Silicon Carbide & Gallium Nitride

Two very important wide band gap materials showing great promise for

the future for both switching and RF power applications are Gallium

Nitride (GaN) and Silicon Carbide (SiC)

GaN SMPC

Impact of GaN properties and its performance convergence

EPC

INP

UT

(1

2V

)

POWER CIRCUIT

OU

TP

UT

(3

.3V

)

Block Diagram of the SMPS

GATE DRIVE INTERFACE

CIRCUIT

PWM CONTROLLER

INP

UT

(1

2V

)

OU

TP

UT

(3

.3V

)

Specification of DC-DC converter

Description of

Parameter

Value of

Parameter

Input

Voltage Min 11.4 VDC

Voltage Max 12.6 VDC

Current Max * 530mA

Output

Voltage 3.3VDC

Maximum Current 1.8 A

Description of

Parameter

Value of Parameter

Losses, Max* 480mW

Cooling Natural Cooled

Power Density ~10 W/inch3

EMC CISPR 11

Safety CE

Environmental IEC60571

Control Type Analog ControlMaximum Current 1.8 A

Voltage tolerance 4%

Ripple 5.0 %

Load Regulation 1.0 %

Maximum Power 6W

Over Voltage

Protection

3.465 VDC

Efficiency Better than 92%

Control Type Analog Control

Application Target Power Supply for

Digital Controller

Frequency of

Operation

>500kHz < 1MHz

Operational

Temperature

-10 to +70 degC

Relative humidity 95% max

Enclosure Encapsulated Enclosure

Challenges in DC-DC Converter

• Design of high immune controller and gate driver for GaN

devices

• PCB Design of High frequency power and control circuits

• Design of passive and reactive components for high

frequency environment

• Thermal design and encapsulation of the Converter

Switching Device comparison

Parameters IRF7470

(Silicon MOSFET)

EPC2014C

(eGaN HEMT)

Drain to source voltage, Vds 40V 40V

Continuous drain current, Id 10A 10A

Maximum Gate Source Voltage ± 12V -4V/6V

On state Resistance 30 mOhm 16mOhm

Reverse body diode voltage 0.65-0.80V 1.8V

Gate threshold 0.8-2V 0.8-2.5V Si-MoSFETGate threshold 0.8-2V 0.8-2.5V

Gate-to-Source Charge 7.9-12nC 0.7nC

Internal gate resistance - 0.4Ω

Gate to source leakage 200nA 2mA

Body diode reverse recovery

charge

150-230nC None

Avalanche capable Yes Not rated

Package SO-8

( 4.8mmx5.8mm)

LGA

(1.087mmx1.702mm)

1.7

02

mm

1.087mm

eGaN HEMT

Si-MoSFET

Selection of componentsComponents Salient Features Package

eGaN FET

EPC2014C

Enhancement

mode Power

Transistor

VDS = 40V,

RDS(on) = 16mOhm,

ID = 10A

Ultra Low Qg

LGA ( Land Grid Array)

LTC 3833

Step down

DC/DC

Vin Range = 4.5 V to 38V

High output accuracy

Differential output sensing

20-pin QFN

( 3mmx4mm)

DC/DC

ControllerDifferential output sensing

Frequency Prog. 200kHz – 2MHz

Fast Load Transient Response

LM5113

Half Bridge Gate

Driver

5A, 100V

Independent Hi & Lo side inputs

1.2/5A peak source / sink current

Internal bootstrap voltage clamp

Fast Propagation times ( 28nsTyp)

VCC – UVLO optimized for eGaN (3.5V)

DSBGA ( 2mmx2mm)

Gate Drive Recommendations

• Gate voltage should not exceed 6V

• Separate pull up and pull down gate path

• Use single point to ground to avoid mixing high currents

with gate drive and control currents

• Provide low gate drive impedance to prevent undesired

turn on turn on

• Gate driver should have

• Low inductance SMD package

• Output impedance 0.5Ω or less

• Operate down to 4.5V supply voltage

• Peak output current >5A at 5V supply

• Better than 5nS rise and fall times with 1nF load

• Reduce gate loop inductance

• Place driver close to the

device(shorter than 0.5 inch)

• Place gate drive and return

Gate Drive Recommendations

• Place gate drive and return

paths on top of one another

• Keep the gate drive and return path lengths

minimum

• Small outline SMD package drivers with minimum

lead inductance

• Limiting zener diodes are not recommended

because of its capacitive effects

Suggested Layouts by the manufacturer

Suggested Layout No of Layers

Filled-via dual-sided termination 4 layers or more

Dual-sided termination 4 layers or more

Single-sided termination 2 layers or more

Pe

rfo

rma

nce

Co

st

Single sided Dual sided

PCB Layout of EPC eGaN HEMT

EPC Recommended PCB Layout PCB Layout of CDAC fabricated DPT PCB

Filled-Via-Dual sided

eGaN SMPS- Layout details

Pad to pad spacing - 6mils

Via to via spacing - 6mils

Drill size - 6mils

Drill annular ring - 8mils

4 layer PCB with solder mask and legend on 1.6mm glass epoxy ENIG finish with PTH and

SMD components, 70microns copper thickness, BBT testing required. Impedance matching

not required. Track to track, track to via, track to pad, via to via, via to pad,

pad to pad clearance: 6mils, All vias should be non conductively filled, Via size: drill-6mils,

annular ring 8-mils.

Recommended Layout Practices

• GaN FETs placed close to the PWM driver

• Minimizing the loop length and area of bootstrap capacitor

circuit

• Optional gate resistor is provided for damping the oscillations

• Drain and source connections are routed in alternate planes to

minimize the inductance

• Double sided terminations to enhance current carrying capacity• Double sided terminations to enhance current carrying capacity

• Gate-source circuit and drain-source circuits are placed

orthogonal to reduce coupling between the circuits

• Routing is replaced with copper pour

• 2oz copper is used in all layers to ensure the lowest possible

connection resistance

• In controller circuit, differential pairs of signals are routed as

close to identical to eliminate the effect of noise injection

Parallel plate overlap Coplanar plate overlap

Recommended Layout Practices

The inductance per unit length for the coplanar arrangement is

approximately 5.7 times higher than the parallel plate configuration

PCB Layers of GaN SMPS

Top

Inner2

Bottom

Inner1

PCB Layout Guidelines

• The via set located in between the two eGaN FETs provides a

reduced length high frequency loop inductance path leading

to lower parasitic inductance.

• The via set located beneath the SR eGaN FET provides

reduced resistance during the SR eGaN FET freewheeling reduced resistance during the SR eGaN FET freewheeling

period, reducing conduction losses.

• The interleaving of the via sets with current flowing in

opposing direction allows for reduced eddy and proximity

effects, reducing AC conduction losses.

Thermal Management

The backside of the device is

isolated. So heat sink can be

mounted directly on the die

RθJC 3.6 ˚C/W

RθJB 9.3 ˚C/W

RθJA 80 ˚C/W

Dual die under one heat sink and thermal pad

RθJA 80 ˚C/W

DPT test

The Parasitics Considered are:

• Source inductance Ls• Gate inductance Lg• Drain inductance Ld

DPT is used for obtaining the switching characteristics of the Device under Test (DUT)

at the desired voltage and current without thermal limitation.

DPT is also used in the study to verify the impact of parasitic capacitances and inductances on

the switching characteristics of the device.

• Parasitics may lead to– Excessive voltage overshoots across the gate-source

– Damping of the gate to source voltage

– Ringing in Vgs, Vds & Id

• The optimized values of the parasitics are• Ls = 50 pH • Lg = 0.5 nH• Ld = 50 pH

• Rg = 1Ω

• Drain inductance Ld• Gate Resistance Rg

Power Circuit- GaN SMPS

Control Circuit – GaN SMPS

Performance Evaluations

Oscilloscope details

HDO6104 (Teledyne Lecroy make), 1 GHz, 2.5

GS/s, 4 Channels, 12-bit HD Digital Oscilloscope

Probe details

ZD1000 (Teledyne Lecroy make), 1000 MHz

Differential Probe

PP018 (Teledyne Lecroy make), 500 MHz Passive

ProbeProbe

ADP 305 (Teledyne Lecroy make), 1kV, 100 MHz

High-Voltage Differential Probe

CP031 (Teledyne Lecroy make), 30A, 100 MHz

Current Probe

Regulated DC Power Supply

LQ6324T (Aplab make)

TEST SETUP

Performance Evaluations – 250kHz

Time Scale : 200ns/div

ChC1: VGS of Top Switch (2V/div)

ChC2: VGS of Bottom Switch

Time Scale : 200ns/div

ChC1: VDS of Bottom Switch (8V/div)

ChC2: VGS of Bottom Switch (5V/div)


Time Scale : 1 μs/div

ChC1: Output Voltage Vo (2.0 V/div)

ChC2: VDS of Bottom Switch (10.0 V/div)

ChC3: Inductor Current (500 mA/div)

Inductor Current Ripple : 339 mA




ChC4: VDS of Top Switch (10.0 V/div)






ChC3: Output Current (500 mA/div)

Average Output Current : 1.576A










ChC4: VDS of Top Switch (10.0 V/div)


Quantitative performance

Sl # Input Output Efficiency

%Voltage

V

Current

A

Power

W

Voltage

V

Current

A

Power

W

1 12 0.03 0.360 3.305 0.0971 0.321 89.17

2 12 0.06 0.72 3.334 0.1956 0.652 90.552 12 0.06 0.72 3.334 0.1956 0.652 90.55

3 12 0.09 1.08 3.304 0.2945 0.979 90.56

4 12 0.29 3.48 3.32 0.9988 3.316 95.28

5 12 0.46 5.52 3.32 1.5770 5.236 94.85

Initial level testing @500kHz





ChC3: Output Current (500 mA/div)

Average Output Current : 1.566A

Photographs

Design1

TOP SIDE BOTTOM SIDE

Design2

Details of Demonstration

Components of SMPC

Double pulse Test Board

Synchronous Buck DC-DC Converter board

Acknowledgements

NaMPET-II an initiative of DeitY

Project title

Investigations on Gallium Nitride (GaN) devices for Power

Electronic switching applications and Design and Development of

a high frequency GaN convertera high frequency GaN converter

Joint development by

CDAC Trivandrum & IISc ( Dept of EE, CeNSE, DESE) Bangalore

http://www.nampet.in/wide-band-gap-devices

Thank You

Demonstration of DC-DC Converter

Thank You

Thank You

[email protected]

www.cdac.in www.nampet.in

http://www.nampet.in/wide-band-gap-devices

Introduction to GaN Devices

Comparison of Semiconductor Material Characteristics

Operates stably at Higher Voltage

Operates stably at Higher temperature of 500deg C

Operates stably at High frequency of 100GHz

No harm to Human body( no hazardous materials ) NIT-Japan

PCB Fabrication agencies

• ACME CIRCUITS

• HIQ

• PRECISION

• MICROPAK

• PC PROCESS

• SHOGINI

• SUNNY CIRCUITS TECHNOLOGY

• PCBPOWERPCBPOWER

• FINE LINE CIRCUITS LTD

• GENUS ELECTROTECH LTD

• ASCENMT CIRCUITS PVT LTD

• EPITOME COMPONENTS

• SULAKSHANA CIRCUITS LTD

• AT&S

• PRISM CIRCUITRONICS

Purchase Requisition date : 01-07-2015

Purchae Order date : 12/08/2015

Gate pull down resistance and impedance

Condition to avoid Miller turn on

.

Time constant of the circuit is,

Should be limited

Where, Zpull-down includes

Gate resistance, Rg

Pull down resistance, Rsink

Loop Inductance

Gate pull up resistance

• QGD is much lower compared to Si MOSFETs

eg: 40V 10A, Si MOSFET(IRF7470TRPBF), QGD = 44nC,

GaN HEMT(EPC2014C), QGD = 2.5nC)

• Fast turn on compared to Si MOSFETs

• High dv/dt can create shoot-through during the ‘hard’ switching transitionswitching transition

• Gate drive pull up resistor– minimize transition time

– Adjust the switch node voltage overshoot and ringing

– Better EMI

– Should not induce unwanted losses

– Anti parallel diode is not used because of low threshold voltage

Gate drive dead time

• No reverse recovery losses

• Higher body diode forward voltage drop

• Diode conduction losses are significant at low

voltage and high frequencyvoltage and high frequency

• Dead band control reduce diode conduction

interval

Gate Drive Supply Regulation

Discrete eGaN FET gate-driver solution

with high-side and low-side supply

voltage matching

LM5113: Half-Bridge Gate Driver Optimized

for eGaN FETs

Effect of Common source inductance

Equivalent partial power circuit showing the

di/dt effect of ‘hard’ turn-on

• Opposes gate drive voltage during di/dt

• Increase turn on and turn off times

• Reduces efficiency

• CSI, CGS, Rsink forms an LCR resonant tank

• Ringing in the gate voltage

‘hard’ turn-on of complementary device

showing effect of CSI ringing.

• Electroless Nickel Immersion Gold

Advantages:

• Flat Surface

• No Pb

• Good for PTH (Plated Through Holes)

• Long Shelf Life• Long Shelf Life

Disadvantages:

• Expensive

• Not Re-workable

• Black Pad / Black Nickel

• Damage from ET

• Signal Loss (RF)

• Complicated Process

Gallium Nitride Based Power Electronic Devices and Converters · 2016-01-07 · Gallium Nitride...

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Transcript of Gallium Nitride Based Power Electronic Devices and Converters · 2016-01-07 · Gallium Nitride...