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Design Project Report

ECE 511

Analog Integrated Circuits

Design of a CMOS fully-differential operational

transconductance amplifier

Joel Prabhakar Periathambi

Ajit Narwal

North Carolina State University

5th December, 2011

Honor Pledge

“We, Ajit Narwal and Joel Prabhakar Periathambi, have neither given nor received any unauthorized aid

on this project”

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Executive summary

Design for the fully-differential operational transconductance amplifier (OTA) was implemented using a

folded cascode operational amplifier with PMOS-differential pair input and the required gain was

achieved by employing gain-boosting operational amplifiers. The common-mode feedback (CMFB)

circuit is that of a series-shunt feedback type (topology 41). All the design specifications were

comprehensively met; however, the operational amplifier gain suffers from cross-over frequency

distortion (further elucidated in section 2.4).

1.1) Design results

Compliance table for the fully-differential operational transconductance amplifier-

Parameter Specifications Achieved values Low Frequency Gain 92 dB 104.9dB Unity gain frequency >200MHz 553.8MHz Phase margin >70 deg, for unity gain feedback,

no external load 71.3 deg

Settling time (1% of final value)

<90 nsec with 4pF cap load 87nsec with 4pf cap load

Output Swing .8 V pk-pk single-ended 1.6 V pk-pk differential

0.849V pk-pk single ended 1.624 V pk-pk differential

Input common-mode range Overlap with output range >0.5-V 0.1 to 1.05 with an overlap of 0.669 V

CMRR >60dB 135.3dB

PSRR >60dB 245.1dB

Supply Voltage 1.8V 1.8V

Power dissipation <10mW 6.695mW

Slew rate >30 V/usec 33.08 V/usec

Input-referred noise voltage <10 nV/√Hz 9.96 nV/√Hz

Table 1

1.2) Design Methodology

At the onset attempts were made to establish the circuit using a folded amplifier with gain boosting

provided by a common-source second stage; rigorous calculations were followed by circuit simulations,

however the circuit displayed severe limitations when it came to the overlap of the common-mode

input voltage range and single-ended output (to the tune of 30mV),which rendered the circuit hard to

implement for unity gain feedback even though substantial gain could be achieved through the second-

stage. The second and the final circuit that was attempted was a folded cascode design. The proposed

circuit used PMOSes for input for they provided a higher slew rate in comparison to NMOSes for the

same current. Design on paper was based on the gain-bandwidth product (GBWP). Employing the

gpdk180 design kit the nominal size of the input PMOSes was randomly decided upon to provide enough

transconductance for a given current to achieve the basic specification of GBWP. One thing to be kept in

1Dr. B Floyd, Analog Integrated Circuits Lecture Notes-21, pg. 17-18

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mind while designing folded cascades is that the current through NM5 (and NM1) shall be larger than

the tail current through PM8. This prepared the arrangement for the worst case of differential wherein

all the current is drawn to one leg of the input PMOSes which can occur when if inputs rail to one side.

To make sure that the circuit endured the situation and the CMOSes were being driven in saturation (i.e.

the circuit gain is maintained) INM5 (and INM1)>IPM8. The bottom current sources thus were designed

accordingly and a rough idea of designing the other CMOSes in the circuit was gained. Fig.a) depicts the

circuit in discussion. The design criteria also lend a valuable range of VDsats for CMOSes in the circuit.

Since output swing, single ended, was 0.8 V the overdrive ІVDsatsI could be designed ≤ 0.25V, preferably

on the lower side to ensure a safety margin.

Fig.a OTA design circuit

Simulations were run for single ended circuit lending a gain of 57dB.

1.3) Gain-boosting amplifiers

The Δ(required gain) =92-57dB was the basis for the design of the gain-boosting amplifiers. The design

parameters for NMOS operational amplifier is as under. It was made sure that the differential amplifier

inputs were

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Fig.b Gain-boosting amplifier design

NMOSes if providing negative feedback to a PMOS. These operational amplifiers drive the gate of the

CMOS to ensure that there is the source of PM4 is set to a set voltage, and which if set properly can

allow only a Vdsat drop across PM6 and NM1 lending an output of the circuit a swing of 2×Vdsat within

each rail. Also voltage drop across PM6 becomes less dependent on Vout.

Fig b) is an NMOS gain-booster. Another PMOS booster was designed as well. A circuit of this type

comes with a few caveats. Firstly make sure that the feedback of the circuit is indeed negative or else

positive feedback shall lead to oscillations. Secondly the input common mode range for booster

amplifiers shall be within the range of the parent operational amplifier.

This circuit lends the capacitor between gate and source of PM4 Miller effect and Cgs becomes

effectively Cgs (1+A), ‘A’ being the gain of the internal operational amplifier. This leads to reduction in

frequency of the secondary pole which deteriorates the phase margin of the circuit2. This needs to be

countered and hence these boosters need compensation. This shall be discussed under the section-

Compensation, section 1.4.

2Jiang, Xin, Sanghyun Seo, and Yumin Lu. “CMOS Single Stage Fully Differential Operational amplifier

with 120 dB DC Gain” (2003): 1-2. Print.

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Fig.c Operating points for the main circuit, with the gain-boosting operational amplifiers inserted

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Fig.d Operating points for NMOS booster amplifier circuit

1.4) Common-mode feedback (CMFB) circuit

Common mode feedback is required in all fully-differential amplifiers having active loads. Here a

topology was used which senses the output voltages in terms of current flowing through PM0. This can

be classified as a sensor for the output voltage.

Fig.e Common mode feedback circuit

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Gate of PM0 drives the gates of PM5 and PM6 until the common-mode output voltage is set to the

desired point. The feedback is negative and the phase margin of the loop thus obtained has to be taken

care of to ensure stability of the circuit.

Fig.f Common-mode feedback operating point

1.5) Compensation

Every circuit which includes feedback needs to be checked for stability and hence compensated for

adequate phase-margin for operation over variations of process, voltage and temperature. As discussed

in 1.4 the gain-boosting amplifiers induced a Miller effect on Cgs of PM4 and reduced the secondary pole

frequency wp2 which deteriorated the phase margin of the loop, hence a capacitor was connected at the

high impedance node (gain-boosting operational amplifier output) to ensure that the loop gain dropped

to a low value at wp2. The unity-gain frequency of the gain-boosting operational amplifiers must lie

between the 3-dB bandwidth of the original circuit and its unity-gain frequency ensuring a high gain

during the bandwidth of the original circuit and such that at higher frequency the pole of the gain-

boosters doesn’t affect the stability of the system.

Likewise the CMFB circuit also needed compensation which was provided by the compensation

capacitor of the main operational amplifier.

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1.6) Supply independent biasing

While the initial stages of circuit design involved extensive use of ideal energy sources, these were

finally replaced with circuits which require a trigger circuit and the regular Vdd supply=1.8V.

These circuits were replaced by a current reference (Vgs based) biasing circuit. Here the produced

current is independent of Vdd. One can notice two feedback loops in the biasing circuit, one positive

and the other negative, here the negative feedback dominates the circuit and ensures circuit

stability. The necessary bias voltages were obtained by the usage of a MOS transistor and its

complementary in diode connection.

Fig.g Supply-independent biasing circuit design

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Fig.h Biasing circuit operating-points

Circuit simulation results

Fig.i Frequency response of OTA

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As seen from the response above the low frequency gain obtained was about 105dB with a healthy

phase margin of 71o. The gain-bandwidth product was 554 MHz and the 3dB bandwidth of the circuit

was 4KHz. These values not only meet but exceed the required specifications by a healthy margin.

Fig.j Frequency response of Common-mode feedback circuit

Low frequency gain=96.7dB, phase margin=70o

2.2) Step response and settling time

Settling time for this circuit is the time required for the output to settle within a band of 1% of the final

value after being subjected to a step input with a load of 4pF capacitor. PMOS inputs for the OTA

ensured a high slew rate and hence a low settling time. As can be seen from Fig.k) the settling time

achieved with this design was around 87.5 ns and the slew rate was around 33 V/µs.

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Fig.k Slew rate and settling time

2.3) Input common-mode range

The common-mode input range was measured by sweeping the common mode voltage and plotting the

frequency response of the design. The range of voltages for which the gain of the amplifier lies within +-

6dB of the peak gain was found to be from 0 V to 1.05 V.

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Fig.l Input common mode range

2.4) Output Swing

The differential output swing is the output that can be obtained from the OTA whilst a healthy gain is

maintained. The range achieved with this design was from -797.6 mV to 826.794 mV (Fig. m) amounting

to a peak-to-peak differential voltage of 1.624 V. The single ended output swing had a peak-to-peak

differential swing greater than 0.8 V (Fig. n) for both the positive and negative outputs. The circuit,

however, suffered from cross-over frequency distortion wherein NM0 (and NM1) (refer fig. e)) were

pushed out of saturation when the single ended output of the circuit was low. The gain henceforth was

truncated and a dip is observed at point M (refer fig. m)). This is evidently a limitation of the employed

CMFB topology; however, the problem could be worked out by appropriately sizing the CMOS sizes in

the CMFB circuit to ensure a Vout+ and Vout- were maintained at halfway through the input rails. The

output swing was limited to values around 1.3 V when attempts were made to do away with the

distortion.

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Fig.m Differential Output Swing

Fig.n Single Ended Output Swings

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2.5) CMRR & PSRR

The CMRR or the common-mode rejection ratio is an estimation of sensitivity of the circuit. The common-mode

gain was determined by providing a 1 V alternating supply to the common mode input and plotting the

response of the common mode output. Ideally operational amplifiers must have a very low common mode gain

so that the differential gain is unaffected by changes in the common-mode input. The common mode rejection

ratio was obtained by plotting the response of the common mode gain and the differential mode gain and then

subtracting the latter from the former over a wide frequency range. One thing that was kept in mind while

performing the above test was that gains for both differential and common-mode were obtained using two

samples of the same OTA to avoid signal mixing and crossing-over.

Fig.o) Common-mode Rejection Ratio

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The power supply rejection ratio or PSRR is a measure of circuit robustness against supply variations, both in

Vdd and ground. The PSRR was calculated by plotting the differential gain while applying only a common mode

input to the differential pairs of the OTA and adding a 1V AC to the power supply, versus the differential mode

gain.

Fig.p) Power Supply Rejection Ratio

In both the scenarios it can be observed that the transconductance amplifier exhibits a high common mode

rejection ratio and power supply rejection ratio.

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2.6) Noise

The design exhibited a noise, referred to the input, less than 10 nV/√Hz. The main culprit devices were the

current sourcing NMOS transistors in the cascade circuit (namely NM5 and NM1, refer fig. a)) followed by the

input differential pairs.

Fig.q Equivalent input-referred noise response

Project learnings

The endeavor leading to the project provided invaluable insight to the circuit operation from a design

perspective. Among many a thing the behavior of CMOS devices under different operating conditions was

noticed and various trade-offs were dealt-with through various iterations that went into the design. In the

nascent stages of circuit simulations it was realized the CMOSes required to be sized and biased appropriately

to obtain an evenly distributed Vds among circuit elements. This lesson could save substantial time in the analog

circuit design. The voltages for common-mode to be set by the feedback loop provide important information

about the voltages to be selected for biasing. Also valuable confidence was gained in understanding and

working on the tool CADENCE. The design can be further improved by using further sizing the CMOS members

of the CMFB circuit to ensure a healthy gain throughout the input range. A rail-to-rail input operational

amplifier could be used to achieve input common-mode range between any values between the input rails.