CMOS Analog Circuitshome.iitk.ac.in/~baquer/L14_diff_amp_2.pdf · 2018. 7. 24. · CMOS Analog...

CMOS Analog Circuits

L14: Differential Amplifier-2(30.9.13)(30.9.13)

B Mazhari

G-NumberB. Mazhari, IITK42

B. MazhariDept. of EE, IIT Kanpur

Input Common Mode Range (ICMR)

Since differential pairs are often used as the input stage of multi-stageamplifiers, output voltage swing is not as important. What is instead veryimportant is the positive and negative input common mode range voltagep p g p g g(ICMR).

VDDVDD

M3 M4M3 M4

VO

Vi12.5V+vsig

5V

M2M1 Vi2Vi1

2.5V

VBias M5

ISS


VSS

3 3V

V

+3.3V3V

-3V

3V

VO

VS-3.3V3V

-3V

-3VLarge ICMR is required here

100k

+3.3V1k

VO

3V

-3VVS

~0


-3.3V

ICMR is not important here

V

ICMR+

VDD

10/110/1

VDD

M3 M4

VO2.21V2.21V

M3 M4

VO2.21V2.21V

M2M1

VO

Vic Vic0V 0V M2M1Vic Vic

1V 1V-0.54V

ISS

21

V

ic ic

10/110/1

20µA

-1.37V ISSM5VBias

VSS

M5VBias10/1

-2.41µ

VSS

A Vi i i d f h llSS As Vic is increased further, eventuallythe drain-source voltage of m1 and m2will fall below saturation voltage and


these transistors will enter linear modeof operation.

V

ICMR+

VDD

1 3D DD SGV V V

M3 M4

VO 1 1 1DS D SV V V

M2M1Vic Vic

1 1 1

3 1

DS D S

DD SG GS ICV V V V

ISSM5VBias

1 1DS SatV V

VSS1 1S GS icV V V

3 1 1ic DD SG GS satV V V V V

3 1 1DD SG GS satICMR V V V V

3

SSDD TN TP

IICMR V V V


3

ICMR+ close to VDD or even larger can be obtained

Summary

VDDVDD

VO(dc)VSG3

Vsat1M3 M4

ICMR+M2M1

VO

Vic Vic-VGS1

ISS

M2

M

M1

V

Vic Vic

VSS

M5VBias3 1 1DD SG sat GSICMR V V V V


Example VDD

10/1 10/1

M3 M4

VO

10/1

SSDD TN TP

IICMR V V V

M1Vic VicM210/110/1

3

3.3 1.89 0.86 0.23 4.1V

M5

10/1

10/1

-2.408V

20A10/1

VSS

10/1


Building Differential amplifiers with higher differential mode gain

3.3V

Vbias2

3.3V

(W/L)P

VDD= 3.3VRD M3

Vbi 2

Vbias3

vO

M2

(W/L)N-3.3V

VO

v

VBias1 vO

M2

Vbias2

VBias1

vS Vbias1

-3.3V

M13.3Vvin

-3.3V

M1vS

VDD VDD VDD

M3 M4M3 M4

VORD RD

VO1 VO2

3 4

M6 M7VO

ISS

M2

M5

M1

VBias

Vi1 Vi2M1

ISS

Vi1 M2

M3

Vi2

VBiasISS

M2

M5

M1

VBias

Vi1 Vi2


VSS

5

VSS

3

VSS

5

Differential Amplifier with Cascode Current mirror load

VDD

M MVDD

M3 M4

M6 M7

VSG3

VSG6

M2M1Vi1 Vi2

6 7VO VO(dc)Vsat1

VSG6

ISSM5VBias

ICMR+

-VVSS

-VGS1

1 2 7 7 4 1 2dm m o o m o m oA g r r g r g r

1 1g g

A higher differential mode gain isobtained at the expense of a reducedcommon mode range


3 6

1 5

1 11 2

m mcm

m o

g gAg r

common mode range

VDDVDD

M3 M4VDD

M7V

M6

VSG3

VSG6VO

MV VM

M8 M9VBias1 VBias1VO(dc)

SG6

Vsat1

Vsat8

ISS

M1Vi1 Vi2M2ICMR+

-VGS1M5

VSS

VBiasGS1

How do we use a cascode loadi h d i i dSS without reducing input common mode

range?


Folded Cascode ?

V

ICMR-

VDD

10/110/1

VDD=3.3V

M3 M4

VO2.21V2.21V

M3 M4

VO2.21V2.21V

M2M1

VO

Vic Vic0V 0V M2M1Vic Vic

-1V -1V-2.18V

ISS

21

V

ic ic

10/110/1

20µA

-1.37V ISSM5VBias

VSS

M5VBias10/1

-2.41µ

VSS=-3.3V

A V i d d f h llSS As Vic is decreased further, eventuallythe drain-source voltage of m5 will fallbelow saturation voltage and the


transistor will enter linear mode ofoperation.

ICMR-

VDD DD

M MM3 M4

VO 5 5 5DS D SV V VV V V

I

M2M1Vic Vic1GS IC SSV V V

ISSM5VBias 5 5DS Sat

V V

VSS

1 5 1S D GS icV V V V 1 5ic GS SS satV V V V

1 5SS GS satICMR V V V

1 5

2SS SSSS TN

I IICMR V V


1 5

ICMR- is poor in NMOS differential pair

VDD

Summary

-V

VDD

M M -VGSQ1

ICMR-M3 M4

VO

Vsat5

V

M2M1Vic Vic

VSSISSM5VBias

ICMR V V VVSS 5 1SS sat GS

ICMR V V V


Example VDD

10/1 10/1

M3 M4

VO

10/1

M1Vic VicM210/110/1

M5

10/1

10/1

-2.408V

20A10/1

1 5

2SS SSSS TN

I IICMR V V

VSS

10/13.3 0.74 0.145 0.205 2.21V


VDD

-VGSQ1

M3 M4

VO

ICMR-

M2M1

O

Vic VicVBias1-VGS5

Vsat5

Vsat6ISS

VBias1 M5

sat6

VSS

V ICMR V V V

VSS

VBias2 M61 5 1 5

1 5 1 5( )GS sat Bias GS

Bias GS GS sat

V ICMR V V V

ICMR V V V V

VSS

To maximize ICMR-, we should choose VBias1-VGS5 = VSS +Vsat6Bias1 GS5 SS sat6

6 5 1SS sat sat GSICMR V V V V


We thus see that a higher CMRR is obtained at the expense of reduced ICMR-

V

PMOS Differential Pair

VDD

M5VBiasI

1 5

2SS SSDD TP

I IICMR V V

M MV V

ISS 3.3 0.86 0.23 0.32 1.89V

SSIICMR V V VM1 M2Vi1 Vi2

VO2VO13

3.3 0.7 0.145 0.86 3.3

SSSS TN TP

IICMR V V V

V

M3 M4

VSS


VDD VDD

M5VBiasM3 M4

VO

5Bias

ISS

M2M1Vic VicM1 M2Vi1 Vi2

VO2VO1ISS

M5VBias M3 M4

VO2VO1

VSS

I

VSS

2I I

3

: GoodSSDD TN TPIICMR V V V

1 5

2 : PoorSS SSDD TPI IICMR V V

1 5

2 : PoorSS SSSS TNI IICMR V V

3

: GoodSSSS TN TPIICMR V V V


Can we combine both of them in some way to obtain a wide-swing differentialpair

Output Swing

VVDD

M MM3 M4

VOV(7)V(1)

ISS

M1 M2vid

SS

VSS

M5VBias

SS

1 2id GS GSv V V

As vid is increased, VGS1increases and VGS2 decreases

Good positive swing


1 2DS DSI I 3 4SD SDI I

Output Swing

VVDD

M MM3 M4

VOV(7)V(1)

ISS

M1 M2vid

SS

VSS

M5VBias

SS

1 2id GS GSv V V Poor negative swing

As vid is decreased, VGS1decreases and VGS2 increases

Poor negative swing


1 2 ?DS DSI I 3 4 ?SD SDI I2

2 2 2{( ) 0.5 )}DS GS T DS DSI V V V V

VDD

M3 M4

VO

I

M1 M2id

ISS

V

M5VBias

VSSVDD

RD RDVO2VO1

IDS1 IDS2

M2

ISS

M1

VIN

DS1 DS2


VSS= -3.3V

RSS

VDD Output Swing

M3 M4

VO

I

M1

VO

M2vid

ISS

VSS

M5VBias

VDD

M5VBiasISS

M1 M2Vi1 Vi2

VO2VO1


M3 M4

VSS

Frequency Response

4 4 2 2Total db gd db gdC C C C C VDD

M4M3Cdb4

C1f

VOC d2

Cgd4 34 4 2 22 ( )

dBO db gd db gd

fR C C C C

vi1M2M1

vi2Cdb2Cgd2

1 2 4dm m o oA g r r

13

mdm dB

gUGF A f VBiasISS

M 3 2dm dB totalf

CVSS

M5


Example

V

2 2.7gdC fF 2 5dbC fFVDD

M M10/1 10/1

4 2.4gdC fF 4 4.3dbC fFM3 M4

VO

4 4 2 2 14.4Total db gd db gdC C C C C fF M1 M2

10/110/1

Vi2Vi1

1.28OR M M5

10/1

-2.408V

20A

31 8.5

2 ( )dBf MHz

R C C C C

VSS

4 4 2 22 ( )O db gd db gdR C C C C

1g


1 1.52

m

total

gUGF GHzC

VDD

M4M3Cdb4

VO

VO

Cdb4

C 2

Cgd4 ROIN=gm1 vid CTotal

vi1M2M1

I

vi2Cdb2Cgd2

VBiasISS

M5VO

RO

VSS5

I f N ’ i l

CTotalAdmvid

In terms of Norton’s equivalent,the differential amplifier can beexpressed using an RC


equivalent circuit

VORO

VO

CTotalAdmviddm id

This equivalent circuit showsthat the transient response ispdetermined by time constantRoCTotal

If input voltage is largeIf input voltage is large,then output voltage varieslinearly rather than

ti ll


exponentially

VDD

10/1 10/1

M3 M4VO

CL=1pF

M1 M2

20A10/1 10/1

vid

VSS

M510/1

-2.408V


VDD

10/1 10/120µA

M3 M410/1 10/1

VOCL=1pF20µA 0µA

M1 M210/1 10/1

+200mV0µA

M510/1

20A

-2.408V

vid

VSS

O SS

L

dV Idt C

M3 M410/1 10/1

V

VDD 0µA

M M

VOCL=1pF

200 V0µA 20µA

M

M1 M2

20A10/1 10/1

vid

-200mV

O SSdV I

G-NumberB. Mazhari, IITK69VSS

M510/1

-2.408V O SS

L

dV Idt C

Noise

10 noise currents have to beM3 M4

VO

10 noise currents have to beconsidered, 2 from each transistor, onethermal and the other flicker

M1M2

There are three noise calculations that

M

need to be done since noise analysis isidentical for M1, M2 and M3, M4

M5


M3 M4 5 1 2,i i i

M

INiN1-i1 i2

iN1-i1

211 iiiN M1 M2iN1

211N

121 5.0 Niii

ro5

i1 i2i5

121 5.0 Niii

1NN iI ro5 1NN

2 4i R kT R1 1 143ON N O m Ov i R kTg R


Consider next the noise contribution due to noise current of transistor M3:

M MiN3 M3 M4IN

i

iN3

i

iN3- i1 iN3- i13nN iI

M1M2

i2i1

i2i5

i1

ro5

5

2 4i R kT R


3 3 343ON N O m Ov i R kTg R

M3 M421 iiIN

M M2

INi1

i1i2 i1 ~i2 and so IN ~0.

M1 2

i1 i2

ro5 iN5

i5

N i ib i d i i d i h M5 li ibl ThiNoise contribution due to noise currents associated with M5 are negligible. Thisis understandable since the noise currents constitute common mode signals


Noise1

1 1 11 1

2 2 443 3

tt m t

m m

i kTi kT g eg g

M M

1 13 3m mg g

22 43t

kTe M3 M4

VO lf Fi k

213

tmg

M1M2 l 2

1 1 1

f Ff f AFm ox

e eg f C W L

3 32 2i g

M5

3 33 3 3 21 1

2 24 43 3

t mt m t

m m

i gi kT g e kTg g

5

4 34 21 1

2 43

t mt

m m

i ge kTg g

23 33 4 21 3 3 1

f F mf f AFm

i k ge eg f C W L g

2 2 2 21 3 32( )ntotal t t fl fe e e e e


1 3 3 1m ox mg f C W L g

Noise

M3 M4

VOM1

M2

VO

M5

342 (1 ) (1 )3

m F Pntotal AF

kT g k KPeg g f C W L KP

1 1 13 m m ox Ng g f C W L KP

Make the size of NMOS transistors M1 and M2 large to reduce Noise


Make the size of NMOS transistors M1 and M2 large to reduce Noise

Example VDD

M3 M410/1 10/1 91.8 / @1ntotale nV Hz kHz

M1

3 4

VO

M2 Vi2Vi1 16.54 / @1ntotale nV Hz MHz

V

M5

10/1

10/1

-2.408V

20A10/1

@ntotal

VSS


Power Supply Rejection Ratio

M3 M4vdd M3

vddM3 M4

VO VO

M1 M2 M1

2ro5

M5

o5

dmAPSRR 1 1 52 11 2

o o m o

dd

v r g rv r g r

o

dd

vv

1 1 53

2o m om

r g rg


dmPSRR A

M3 M4

M3 M4

VO

3 4

VO

M1 M2

M1 M2

r

M5

gm5vss ro5

vssM3

V

dm

o

APSRR v

M1

VO

53

10.5o mv gv g

o

ssv2ro50.5gm5vss

3ss mv g


Mismatch


80

100

60

80

Cou

nt

20

40C


-0.010 -0.005 0.000 0.005 0.0100

VTN (V)

80

1002

2 2 2( ) VTT VTAV S D

W L

20

40

60

Cou

nt

W L

13 ;5 / for NMOS

VT

VT

A mV mS V m

-0.010 -0.005 0.000 0.005 0.010

0

20

VTN (V)

5 / for NMOS22 ;5 / for PMOS

VT

VT

VT

S V mA mV mS V m

VT

To minimize mismatch,make device larger andmake separation betweenthem zero (?)


20.02 ;A m 2

2 2 2( )A

S DW L

62 10 / for NMOS

0 03 ;

S m

A m

6

0.03 ;

2 10 / for PMOS

A m

S m

2( )D GS TI V V

2( ) ( )D GS T GS T TI V V V V V ( )

2D GS T( ) ( )

2D GS T GS T TI V V V V V

2DI 2( )

DT

D GS T

I VI V V

2 2 22

4( ) ( ) ( )( )

DT

D GS T

I VI V V


D1

G1

D2

G210/1 10/1D1 D2

M1 M2

G1S1 S2

G210/1 10/1

S1

G1 G2S2

22 2 2( ) VTT VT

AV S DW L

( ) 4.1VTTAV mV

W L

0.5GS TV V V

22 2 2( )

AS D

W L

3( ) 9.5 10A

W L

W L W L

4I 2 22

4( ) ( ) ( ) 0.019( )

DT

D GS T

I VI V V

I( ) 4.2% for V 0.2D GS T

D

I V VI

3 ( ) 12.6% DD

II


Accuracy –Power tradeoff

Effect of Mismatch on Differential Pair

1 2685 ; 690T TV mV V mV

1 2 690T TV V mV

1 2695 ; 690T TV mV V mV


1 2695 ; 690T TV mV V mV 1 2690 ; 690T TV mV V mV

Th ff t f i t h b d ib d i t f i t ff t lt


The effect of mismatches can be described in terms of input offset voltage

VDD VDD

M3 M4

V

M3 M4

VO

M2M1

VO

V V I

M2M1Vi2Vos

ISSM5VBias

Vi1 Vi2 ISS

V

M5VBiasVi1

VSSVSS

A differential amplifier with mismatches can be modeled as a differentialamplifier with no mismatches but with a non-zero input offset voltage

( , , , )OS TN N TP PV f V V


VDD

Input Offset Voltage due to M1-M2 mismatch

M3 M4

MM

VO 2( )2 2SS

D GS TII V V

ISS

M2

M

M1

VBi

Vos

VSS

M5VBias

11

0DS DS DSDS T OST GS

I I II V VV V

1( )4 N

SSOS T

IV V


1 14 N

Input Offset Voltage due to M3-M4 mismatch: VT mismatch

VDD

M4M3 M4

1/gm3

4

VO

3

VTP4

VTP INV=0

M2M1

ISS

M1 M2

M5VBias

VSSSS

4N TPI g V 1 4 0N OS TPI g V g V 4N m TPI g V 1 4 0N m OS m TPI g V g V


4

1POS T

V V

Input Offset Voltage due to M3-M4 mismatch: β mismatch

VDD VDD

M4M3 M4M3

VO

4

VO

3

VGS3 4

M2M1

ISS

M2M1

ISSM5VBias

VSS

M5VBias

VSSSS

2( )2D GS T

I V V 0D DD GSGS

I II VV

GSD

DSGS

IIV I

4 3SS

OS GSIV V


2GS DGS

V IV

1 1 34

OS GSV V

VDD

Net Offset Voltage

DD

M3 M43 4

VO

ISS

M2M1

V

Vos

VSS

M5VBias

1 3 3( )SSIV V V 1 1 3 1

( )4OS TN TP

V V V


●While making a differential pair or a current mirror wherematching between the transistors is important, one should ensureh h i l iblthat the two transistors are as close as possible.

D1 D2D1

G1 G2

D2

M1 M2S1 S2

D DD1G1

D2G2

S1 S2


Noting that source is common to both the transistors, one candraw the following more compact layout where distance betweendraw the following more compact layout where distance betweenthe two transistors is also smaller

D1D D 1G1

S

D1

G G

D2

SG2

M1 M2

G1 G2S1 S2

D2

G2


An even better layout is shown below:

D DD1G1

S S

D2G2

SG2

SG1

D2 D1

Each transistor is made of two fingers and it can be seen that the centroid oftwo transistors coincide, in other words effective separation between the two iszero! The above scheme can be conveniently represented by the followingy p y gschematic:

M1 M21

M

2

M


M2 M1

For five finger mosfets, the common centroid layout can bedescribed asdescribed as

M1 M2

M2 M1

M1 M2

M2

M

M1

MM1 M2


CMOS Analog Circuitshome.iitk.ac.in/~baquer/L14_diff_amp_2.pdf · 2018. 7. 24. · CMOS Analog...

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Transcript of CMOS Analog Circuitshome.iitk.ac.in/~baquer/L14_diff_amp_2.pdf · 2018. 7. 24. · CMOS Analog...