Analog Cmos Amplifiers
Transcript of Analog Cmos Amplifiers
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A n a l o g CMOS 1
Chapter 3
Fundamental Building BlocksCourse home page: http://www.fysel.ntnu.no/courses/tfe4185/
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September 2004
MOS Fu n d am e n t a l B u i l d i n g B l o ck s
CMOS Current Mirrors
Simple
Source-Degenerated
High-Output-Impedance
CMOS Single Transistor Amplifiers Common-Source
Source-Follower (Common-Drain)
Common-Gate
Cascode Gain Stage
MOS Differential Pair and Gain Stage
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B JT Fu n d am e n t a l B u i l d i n g B l o c k s
Bipolar Current Mirrors
Simple
Base current compensated
Emitter-Degenerated
Bipolar Gain Stages
Emitter Follower
Differential Pair
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September 2004
I n t r o d u c t i o n t o A m p l i f i e r s
212
210 )()()()( inininn
innininout VVVtVatVatVaatV ++++= K
A VoutVin
The input-output characteristic of anamplifier is generally a non-linear functionthat can be approximated by a its truncatedTaylor series over some signal range:
The signal is shown here as a voltage. It can also be current or charge.
For a sufficiently small input signal range, we can keep the constantand the first order terms only:
)()( 10 tVaatV inout +=
Here, a0 can be considered the operating point and a1 the small-signalgain.
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Am p l i f i e r Pe r f o r m a n c e Pa r a m e t e r s
Gain
Speed
Noise
Linearity
Supply voltage
Voltage swing
Power dissipation
Input/output impedance
Most of these parameterstrade with each other.Such trade-offs lead tomany challenges in thedesign of high-
performance amplifiers.
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September 2004
Com m o n - So u r c e A m p l i f i e r
with Resistive Load
VinQ1
Vout
VDD
RD
2)(2
tninoxn
DDDout VVL
WCRVV
=
Assuming that the transistor is biased instrong inversion, active region:
Here we have neglected channel length
modulation.
Taking the derivative of Voutwith respect toVin, we get
Dm
tninoxnDin
outv
Rg
VVL
WCR
dV
dVA
=
== )(
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September 2004
CS Am p l i f i e r w i t h Re s is t i v e L o a d
vin vin gm1vin RD~
vout
Finding the gain using the small-signal equivalent circuit
Dmin
outv
Dinmout
Rgv
vA
Rvgv
===
All the current in the current source go through the resistor:
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September 2004
CS Am p l i f i e r
with Ideal Current Source as Load
VinQ1
Vout
VDD
Ib
vin gm1vin gds
vout
Effect of channel length modulation included.
dsmds
mv rg
g
gA ==
The quantity gm/gds is called the intrinsic gainof a transistor. Represents the maximum gainthat can be achieved using a single device.
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September 2004
Ex am p l e o f I n t r i n s i c Ga i n
for a 0.35m CMOS technology
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Veff [V]
-0
200
400
600
800
Intrinsicgain
W/L = 5m/1.05m
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Veff [V]
0u
50u
100u
150u
200u
250u
300u
Draincurrent
[A]
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September 2004
Si m p l e CMOS Cu r r e n t M i r r o r
Assume transistors in activeregion, = 0, and same size
Iout=Iin
Iin
Iout
routV1
vyvgs1gm1vgs1 rds1
v1
Q1 Q2
~
iy
1111
1
11||mm
dsy
yym
ds
yy
ggr
ivvg
rvi =+=
Q1
v1
1/gm1
Q1
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September 2004
Si m p l e CMOS Cu r r e n t M i r r o r
1/gm1
Q1
vgs2 gm2vgs2 rds2
Q1 Q2
rout
rds2
Small Signal Equivalent Circuit (Low Frequency )
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September 2004
Cu r r e n t M i r r o r D e s ig n Ex am p l e
Design a current mirror such that Veffis > 0.5 V androut> 300 k at an input current of 100A.
Given: nCox = 92 A/V2; Vtn= 0.8 V;rds = 1/ID = 8000L(m)/ID (mA)
m34
m8.34V25.0
V
A92
m42A100
2
m4
m75.38000
1.0k300k300
)mA(
)m(80001
22
2
=
=
>=
==
W
WVL
WCI
L
LI
L
Irr
effoxn
D
DDdsout
Solution:
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September 2004
CS w i t h A c t i v e L o a d
routVinQ1
Ibias
Vout
Q2Q3
vin vgs1 gm1vgs1 R2= rds1|| rds2~
Rinvout
)||( 211 dsdsmin
outv rrg
v
vA ==
Active load
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September 2004
So u r c e - Fo l l o w e r ( Co m m o n - D r a in )
Voltage gain close to unity
Used as voltage buffers
Can provide current gain
Ibias
Q3 Q2
VinQ1
Vout
vgs1 gm1vgs1 rds1
vout
vin
rds2
gs1vout
2111
1
1121 0)()(
dsdssm
m
in
out
outinmsdsdsout
gggg
g
v
v
vvggggv
+++=
=++
Writing the nodal equation at vout:
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September 2004
Com m o n - Ga t e A m p l i f i e r
routVbiasQ1
Ibias
Vout
Q2Q3
Vin
vgs1gm1vin rds1
vin
gs1vin
Used for:
Low input impedance stages
Amplifying current
vout
+
++
+==
++=
11111
1
111
11
1
)(
ds
L
mdssm
L
ds
in
inin
dsoutininsinmin
r
R
gggg
G
g
i
vr
gvvvgvgi
rin
1
1
1
111
111 0)()(
dsL
m
dsL
dssm
in
out
inmsoutLdsinout
gG
g
gG
ggg
v
v
vggvGgvv
+
+++
=
=++
Voltage gain: Input impedance:
RL
Assumes zeroRS
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September 2004
So u r c e - D e g e n e r a t e d Cu r r e n t M i r r o r
Iin
Iout
Ix
Vs
Q1 Q2
RsRs
sxsgs
sxs
Rivv
Riv
==
=
)1( 22
22
22
msdsx
xout
ds
sxxsmx
ds
sxgsmx
gRri
vr
r
RivRgi
r
vvvgi
+=
+=
+=
ix is equal to the total current through gm2 vgs2and gds2:
Note: To include the body effect, replace gm2with gm2+ gs2
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September 2004
Ca s co d e Cu r r e n t M i r r o r
IinVout
rout
Q3 Q4
Q1
Iout
Q2
[ ]
[ ]
[ ]
424
4424
44424
4444
)(1
)(1
)(1
mdsds
smdsds
dssmdsds
dssmsdsout
grr
ggrr
gggrr
gggRrr
++
+++=
+++=
Serious disadvantage:Voutmust be larger than 2Veff + Vtnto keep all transistors in the active
region
Trond Ytterdal, Department of Electronics and Telecommunication, NTNU, Norway
NTNU
September 2004
W i l so n Cu r r e n t M i r r o r
IinVout
rout
Q3 Q4
Q1
Iout
Q2
rin
211
4dsm
dsoutrg
rr
About one-half of the outputimpedance for that of a cascodecurrent mirror
Serious disadvantage:Voutmust be larger than 2Veff + Vtnto keep all transistors in the activeregion
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September 2004
Ca s c o d e Ga i n St a g e s
rd2
Vin Q1
Vout
Q2Vbias
Ibias
Telescopic-cascode amplifier
Vin Q1
Ibias1
Q2
Vout
Vbias
Folded-cascode amplifier
Ibias2
rL
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September 2004
Ca s c o d e Ga i n St a g e s
Analysis
2122
2 ||
dsdsmd
Ldout
rrgr
rrr
=
=
Assume that rl is of a similar formand that all transistors are matched.Dropping the indices, we get:
2
2dsm
outrg
r
Output impedance
Looking into the source of the common-gate, orcascode, transistor Q2 we get:
Voltage Gain
ds
mds
ds
m
Lds
m
Lds
dssmin g
gg
g
g
g
g
g
g
g
gggy
+
=
+
+
++=
/111 22
2
2
2222
ds
m
inds
m
in
s
g
g
yg
g
v
v
221
12 +
=
2
2
2
2
2
2
1
2
+=
ds
m
dsL
m
ds
m
s
out
in
sv
g
g
gg
g
g
g
v
v
v
vA
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September 2004
MOS D i f f e r e n t i a l Pa i r
Q1
ID2
Q2V+ V
Ibias
ID1
v+ v
id1 = is1 id2 = is2
is1 is2
inm
d
inm
mm
in
ss
insd
mmm
in
vg
i
vg
gg
v
rr
vii
ggg
vvv
2
2/1/1
22
212111
21
=
=+
=+
====
+
inmout
ddout
vgi
iii
=
21
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September 2004
MOS D i f f - Pa i r w i t h A c t i v e Lo a d
Q1Q2
V+ V
Ibias
is1
Q3 Q4 id4
Vout
outmv
inoutmoutdsout
sdd
inm
sd
rgA
vrgriiv
iii
vg
ii
1
141
134
111
)(
2
=
==
==
==
vin gm1vin rout
vout
+
-
CL
is1
Differential-input, single-ended output gain stage
Voltage Gain
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September 2004
MOS D i f f - Pa i r w i t h A c t i v e Lo a d
Output resistance
is1 is2
is1 is2
vx~
ix
rds1 rds2
rds3 || rs3 rds4gm4va
+
-va
rs2rs1
ix2 ix3
ix1 ix4
ix5
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September 2004
MOS D i f f - Pa i r w i t h A c t i v e Lo a d
Output resistance analysis
42
24
4321
3214
54
221
22
41
||
2
dsdsout
ds
x
ds
x
x
xxxx
x
x
xout
xssx
xx
ds
xss
ds
xx
ds
xx
rrr
r
v
r
v
v
iiii
v
i
vr
iiii
ii
r
vii
r
vi
r
vi
=
+=
+++==
===
=
==
=
(assuming rds1, rds2 >> rs1, rs2)
(assuming rs1= rs2)
(current mirror)
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September 2004
B ip o l a r Cu r r e n t M i r r o r s
Simple
Iin
rout
Q1 Q2
Iout
inout II 2/21
1
+=
Better
Iin
rout
Q1 Q2
Iout
inout II +=
/21
1rout=ro
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September 2004
Em i t t e r - D e g e n e r a t e d Cu r r e n t
M i r r o r s
Iin
Iout
Ix
Q1 Q2
ReRe
)1( 22 emoout Rgrr +
Almost identical to the MOS version:
One additional condition:
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September 2004
B i p o l a r G a in St a g e s
Emitter Follower
Q2
RE
Vin
RS
Vout
ib
ie
ro
re
RS
RE =RE || ro
vout
vin
ib
RbRe
vb
rb ignored
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September 2004
B ip o l a r Em i t t e r Fo l l o w e r
Voltage Gain
mE
E
SEe
Ee
in
out
mE
E
b
out
Sb
b
in
b
Eeb
bb
EebEeeb
be
gR
R
RRr
Rr
v
v
gR
Rv
vRR
Rvv
Rri
vR
RriRriv
ii
/1))(1(
))(1(
/1;
))(1(
))(1()(
)1(
'
'
'
'
''
'
''
++++
++=
+=
+=
++==
++=+=
+=
Impedance reflection rule: At low frequencies,resistances in series with the emitter appear +1times larger when seen looking into the base.
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September 2004
B ip o l a r Em i t t e r Fo l l o w e r
Output Impedance
ib
iere
RS
Re
ix
vx = ve
Shall find:
exS
x
exSb
exbx
riR
i
riRi
rivv
++
=
+=
+=
1
vb
11 +
=+
= xebii
i
x
xe
i
vR =
eS
x
xe r
R
i
vR +
+==
1
(REexcluded)
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NTNU
September 2004
B i p o l a r D i f f e r e n t i a l Pa i r
Small Signal
Q1
IC2
Q2V+ V
IEE
IC1
Voltage gain same as for MOSdifferential pair. However,input resistance is not infinite.
ic1 = ie1 ic2 = ie2
ie1 ie2
))(1( 21 eeid rrr ++=
re2re1rid
Using the impedancereflection rule, we get:
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September 2004
Fr e q u e n c y R es p o n s e
Common-Source Amplifier
Full coverage
Source-Follower Amplifier
Important results only
Cascode Gain Stage
Full coverage
SPICE Simulation Example Simulating frequency response
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September 2004
Com m o n - So u r c e A m p l i f i e r
Frequency Response
vin gm1v1 R2~
Rinvout
Cgs1
Cgd1
C2
v1
bssa
g
CsRg
v
v
vgsCvsCsCGv
sCvGvsCsCGv
m
gdm
in
out
mgdgdout
gdoutiningdgsin
21
121
1111212
1111
1
1
0)(
0)(
++
=
=+++
=++
Writing the nodal equations at v1 and vout: C2 = Cdb1+Cdb2+CLR2= rds1|| rds2
( )21211122122111 )()1(
CCCCCCRRb
CCRRgCCRa
gdgsgsgdin
gdmgdgsin
++=
++++=
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September 2004
Com m o n - So u r c e A m p l i f i e r
3 dB Frequency
)()]1([
1
)}()]1([{11
2122111dB3
2122111
2121
CCRRgCCR
CCRRgCCRs
Rg
sa
Rg
v
v
gdmgdgsin
gdmgdgsin
mm
in
out
++++
+++++
=+
At frequencies where the gain has started to decrease, but is still much greaterthan unity, we can write:
If the first term in the denominator dominates:
)]1([1
11dB3
ACCR gdgsin ++
Miller capacitance
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September 2004
SP I CE Ex am p l e
VinQ1
Ibias
Vout
Q2Q3
Common-Source Amplifier
Vb
MOS Common-Source Amplifier
.lib mos025u.mdl
vdd vdd 0 dc 2.5
vss vss 0 dc 0
m1 vout vin 0 0 n1 l=2u w=10u
m2 vout vb vdd vdd p1 l=2u w=10u
m3 vb vb vdd vdd p1 l=2u w=10uib vb vss 10u
cl vout vss 2p
* setting DC operating point
l1 vout vin 1g
* AC decoupling
c1 vinc vin 1g
vac vinc vss dc 0 ac 1
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September 2004
So u r c e - Fo l l o w e r Am p l i f i e r
Frequency Response
Ibias
Q1
Rin CinVout
CL
Iin
The transfer function can be written as:
20
2
0
2
11
1
)()0()(
+
+
=++
+==
s
Q
s
sNA
cssba
gsC
i
vsA
mgs
in
outNote that when Q > 0.5,poles will be complexconjugate, and the circuitwill exhibit overshoot
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NTNU
September 2004
So u r c e - Fo l l o w e r Am p l i f i e r
Q factor and pole frequency
Q factor and pole frequency 0:
111'
1
1111'
1'
111
1'
1
110
;;
)(
)]()[(
)(
)(
ssgdininLsbs
sgssminsin
sgsinsgssmin
sgsinsgs
smin
gGCCCCCC
GCGgCCG
CCCCCGgGQ
CCCCC
GgG
+=+=
+++
+++=
++
+=
If Cs, Cin, or both become large, Qbecomes small => we are safe
When Cin and Gs1become small, Q will be large => large ringing
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September 2004
Ca s c o d e Ga i n St a g e
Vin Q1
Vout
Q2Vbias
Ibias
vin
gm1vg1 rds1
Rin
vout
Cgs1
Cgd1
Cs2
vg1
gm2vs2
vs2
rds2 Cd2 GL
Cs2 = Cdb1+Csb2+Cgs2
Cd2 = Cgd2+Cdb2+CL+Cbias
Trond Ytterdal, Department of Electronics and Telecommunication, NTNU, Norway
NTNU
September 2004
Th e Z e r o - V a l u e T i m e - Co n s t a n t
A n a l y s i s M e t h o d
Set all independent sources to zero
Calculate a time constant for each capacitor byassuming all other capacitors are zero, replacingthe capacitor in question with a voltage source,and then calculating the resistance seen by thatcapacitor by taking the ratio of the voltage sourceto the current flowing from the voltage source.
The -3-dB value is estimated to be 1 divided bythe sum of all the individual capacitor timeconstants.
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September 2004
Ca p a c i t a n c e T im e Co n s t a n t s
gm1vg1 Rd1Rin
~- vx + ix
Rd1 is the parallel combinationof rds1and the impedance seenlooking into the source of Q2
~vx Rd1
Rin
vy
vg1ix
gm1vy
Cgd1
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September 2004
Ca p a c i t a n c e T im e Co n s t a n t s
Analysis
[ ]
[ ]
)1(2
)1(2
)2(12
)(1
)(;
111
111
1111
11
inmds
gdCgd
inmds
mdsinds
Cgd
mdindx
xCgd
ymdyxxinxy
Rgr
C
Rgr
ggRr
r
gGRRi
vr
vgGvviRiv
+
+++
++==
==
(3.52)][see21 dsd rR 2
2
222
22
11
dsmdCd
dssCs
ingsCgs
rgC
rC
RC
=
totaldB
CdCsCgdCgstotal
+++=
13
2211