ECE680: Physical VLSI Design

ECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI Design

Ch t IIICh t III

CMOS Device InverterCMOS Device Inverter

Chapter IIIChapter III

CMOS Device, Inverter, CMOS Device, Inverter, Combinational circuit Logic and LayoutCombinational circuit Logic and Layout

Part 3 Part 3 Combinational Logic GatesCombinational Logic Gatesgg(textbook chapter 6)(textbook chapter 6)

19/18/2008 GMU, ECE 680 Physical VLSI Design

Combinational vs. Sequential Logic

Combinationali O tI

Combinationali

OutInLogicCircuit

OutIn LogicCircuit

C bi ti l S ti l

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

2

p f(In) p ( , )


Static CMOS Circuit

At every point in time (except during the switching y p ( p g gtransients) each gate output is connected to eitherVDD or Vss via a low-resistive path.

Th t t f th t t ll ti th lThe outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on therelies on temporary storage of signal values on the capacitance of high impedance circuit nodes.


Static Complementary CMOSStatic Complementary CMOSVDD

In1In2 PUN

PMOS only

F(In1,In2,…InN)InN

In1In2

InN

PDNNMOS only

PUN and PDN are dual logic networks


Example Gate: NAND


Example Gate: NOR


Constructing a Complex GateConstructing a Complex Gate

VDD VDD

SN1 SN4

SN2F

F A

B

C

C

SN2

SN3D

A

DB C

D

AB

B

(a) pull-down network

D

F

A(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

CBsub-nets

(c) complete gate

7

( ) p g


Properties of Complementary CMOS GatesProperties of Complementary CMOS Gates

High noise margins: VOH and VOL are at VDD and GND, respectively. OH OL DD

No static power consumption:There never exists a direct path between VDD and p DDVSS (GND) in steady-state mode.

Comparable rise and fall times:Comparable rise and fall times:(under appropriate sizing conditions)


CMOS PropertiesCMOS Properties• Full rail‐to‐rail swing; high noise margins• Logic levels not dependent upon the relative device sizes; ratioless

• Always a path to Vdd or Gnd in steady state; lowAlways a path to Vdd or Gnd in steady state; low output impedance

• Extremely high input resistance; nearly zero d isteady‐state input current

• No direct path steady state between power and ground; no static power dissipationground; no static power dissipation

• Propagation delay function of load capacitance and resistance of transistors


Switch Delay ModelSwitch Delay Model

A

ReqAA

Rp RpRp

A

Rp

A

Rp

R

A BB

Rp Cint

A

Rn CL

CLB

Rn A

R R

int

A

A

Rn Cint A

Rn

B

Rn CL

INV NOR2

10

NAND2 INV


Input Pattern Effects on DelayInput Pattern Effects on Delay

• Delay is dependent on the

(consider a NAND gate with A and B input)

• Delay is dependent on thepattern of inputs

• Low to high transitionA

RpB

RpLow to high transition– both inputs go low

• delay is 0.69 Rp/2 CLi l

CLA

Rn

– one input goes low• delay is 0.69 Rp CL

• High to low transition

A

Rn Cint g– both inputs go high

• delay is 0.69 2Rn CL

B


Delay Dependence on Input Patterns

2

2.5

3

A=B=1→0Input Data

PatternDelay(psec)

A=B=0→1 69

1

1.5

2

A=1, B=1→0

ge [V

]

A=B=0→1 69

A=1, B=0→1 62

A= 0→1, B=1 50

0

0.5

1

A=1 →0, B=1

Volta

g A 0→1, B 1 50

A=B=1→0 35

A=1, B=1→0 76

-0.5

00 100 200 300 400

time [ps]

A= 1→0, B=1 57

NMOS = 0.5μm/0.25 μm

12

PMOS = 0.75μm/0.25 μmCL = 100 fF

Transistor SizingTransistor Sizing(assume inverter Wp/Wn = 2)

A

Rp

B

RpB

Rp2 2 4

CLA

RnA

Rp Cint2

4

A

Rn CintRn Rn CL2

1B

intA B

11


Transistor Sizing a Complex CMOSTransistor Sizing a Complex CMOS Gate

A

B

C4

8

3

6

D

C

4

8

6

6

OUT = D + A • (B + C)

A 2

D

B C

1

2 2


Fan‐In ConsiderationsFan In Considerations

DCBA

B

A CL

C3

Distributed RC model(Elmore delay)

D

C

C3

C2

C

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a f i f f i d i ll i hD C1 function of fan‐in – quadratically in the worst case.


tp as a Function of Fan‐Inp

1250

Gates with a fan‐in 1000

quadratic

(psec)

greater than 4 should be avoided.

500

750

tpHL tp

tpLH

t p

250linear

fan‐in

02 4 6 8 10 12 14 16

16

tp as a Function of Fan‐Outp

All t h th

tpNOR2

All gates have the same drive current.

tpNAND2

(psec)

tpINV

t p Slope is a function of “driving strength”

2 4 6 8 10 12 14 16eff fan‐out

17

eff. fan out

Dynamic CMOSDynamic CMOS

• In static circuits at every point in time (except when y p ( pswitching) the output is connected to either GND or VDD via a low resistance path.

f i f i 2 ( N P ) d i– fan‐in of n requires 2n (n N‐type + n P‐type) devices

• Dynamic circuits rely on the temporary storage of• Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.– requires on n + 2 (n+1 N‐type + 1 P‐type) transistors


Dynamic GateDynamic Gate

MpClk

Out Out

Clk Mp

In1In2 PDN

In3

CLA

BC

3

MeClk

Clk

B

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)


Dynamic GateDynamic Gate

offMpClk

Out Out

Clk Mpon 1

off

((AB)+C)In1In2 PDN

In3

CLA

BC

((AB)+C)

3

MeClk

Clk

B

Me

offon

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)


Properties of Dynamic GatesProperties of Dynamic Gates

• Logic function is implemented by the PDN onlyg p y y– number of transistors is N + 2 (versus 2N for static complementary CMOS)

• Full swing outputs (VOL = GND and VOH = VDD)

• Non‐ratioed ‐ sizing of the devices does not affect the logic levels

• Faster switching speeds– reduced load capacitance due to lower input capacitance (Cin)

reduced load capacitance due to smaller output loading (Cout)– reduced load capacitance due to smaller output loading (Cout)

– no Isc, so all the current provided by PDN goes into discharging CL


Properties of Dynamic Gatesp y

• Overall power dissipation usually higher than static CMOS– no static current path ever exists between VDD and GND (including P )(including Psc)

– no glitching– higher transition probabilities– extra load on Clk

• PDN starts to work as soon as the input signals exceed V V V d V l VVTn, so VM, VIH and VIL equal to VTn

– low noise margin (NML)

N d h / l t l k

22

• Needs a precharge/evaluate clock


Issues in Dynamic Design 2: Charge Sharing

Clk Mp

Charge stored originally on CL is redistributed (shared) over CL and CAleading to reduced robustness

CLA

Outleading to reduced robustness

Clk

CA

CB

B=0

Me


Charge Sharing ExampleCharge Sharing Example

f

Clk

A AOut

CL=50fFA A

B B B !BCa=15fF C =15fFB !B

CC

a

Cc=15fF

Cb=15fF

Cd=10fF

Clk


Charge SharingCharge Sharingcase 1) if ΔVout < VTn

VDD

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

or

Clk

Out

Mp

or

ΔVout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

X

CLA Ma

C

case 2) if ΔVout > VTnB = 0CaMb

ΔVout VDDCa

Ca CL+----------------------⎝ ⎠⎜ ⎟⎛ ⎞

–=CbClk Me


Solution to Charge RedistributionSolution to Charge Redistribution

Clk Mp

AOut

MkpClk

A

B

Clk Me

Precharge internal nodes using a clock‐driven transistor (at the cost of increased area and power)


Issues in Dynamic Design 3: ssues y a c es g 3Backgate Coupling

ClkOut1Mp =1

CL1A=0

Out1Out2

CL2In

1=0

Clk

B=0

Me

Dynamic NAND Static NAND


Backgate Coupling Effectg p g

3

2

3

1 Clk

Out1

0In Out2

-10 2 4 6Time, ns

28

Issues in Dynamic Design 4: Clock y gFeedthrough

Clk Mp

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can

CLA

Outdrain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Clk

B

Me


Clock FeedthroughClock Feedthrough

Clock feedthrough

2.5Clk

In1Out

Clock feedthrough

1.5

1

In2

In3 In &0.5

Clk

In3

In4

In &Clk

Out

-0.50 0.5 1

Clk

Time, ns

Clock feedthrough

30

Clock feedthrough


Other EffectsOther Effects

• Capacitive couplingCapacitive coupling

• Substrate coupling

i i h i j i• Minority charge injection

• Supply noise (ground bounce)


Cascading Dynamic GatesCascading Dynamic GatesV

Clk

Out1

Mp MpClk

Out2Clk

I

Clk

In

Me MeClk

In

Out1VTn

e e Out1

Out2ΔV

t

Only 0→ 1 transitions allowed at inputs!

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Only 0 → 1 transitions allowed at inputs!


Domino LogicDomino Logic

MpClkOut1

MpClkOut2

Mkp

1→ 1

In1In2 PDN In4 PDN

1 → 11 → 0

0 → 00 → 1

In2 PDN

In3

MeClk

4

In5

MeClk


Why Domino?Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Clk

Inj Inj Inj Inj

Like falling dominos!

34

Like falling dominos!


Properties of Domino LogicProperties of Domino Logic

• Only non‐inverting logic can be implemented

• Very high speed• Very high speed– static inverter can be skewed, only L‐H transition

– Input capacitance reduced – smaller logical effortInput capacitance reduced smaller logical effort


Designing with Domino LogicDesigning with Domino LogicVDD VDD

VDD

MpClkOut1

MpClk Mr

DD

PDNIn1In2 PDNIn

Out2

M

PDNIn2In3

PDNIn4

Can be eliminated!

MeClk MeClk

Inputs = 0during precharge

36

during precharge


Footless DominoFootless Domino

VDD

Clk Mp

O

VDD

Clk Mp

O

VDD

Clk Mp

OOut1

In1

Out2

In2

Outn

InnIn3

0 1 0 1 0 1

1 0 1 0 1 0 1 0

The first gate in the chain needs a foot switchPrecharge is rippling – short‐circuit currentA solution is to delay the clock for each stage

37

A solution is to delay the clock for each stage


ECE680: Physical VLSI Design

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