VLSI Physical Design Automation.pdf

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10/20/2011 Rajesh Bathija, Mewar University 1

Lecture 3

VLSI Physical Design Automation




Physical Design Cycle

Partitioning

Floorplanning

Placement Global & Detail Routing

Layout Compaction

Layout verification




Partitioning

Partitioning is the task of dividing a circuit into

smaller parts . The objective is to partition the

circuit into parts, so that the size of each

component is within prescribed ranges and thenumber of connections between the

components is minimized .

Different ways to partition correspond to

different circuit implementations . Therefore, agood partitioning can significantly improve

circuit performance and reduce layout costs .




Floorplanning

Floorplanning is the determination of the approximate location of each module in a rectangular chip area, given a circuitrepresented by a hypergraph the shape of each module and thelocation of the pins on the boundary of each module may also bedetermined in this phase . The floorplanning problem in chiplayout is analogous to floorplanning in building design, where we

have a set of rooms (modules) and wish to decide theapproximate location of each room based on some proximitycriteria . An important step in floorplanning is to decide therelative location of each module . A good floorplanning algorithmshould achieve many goals, such as making the subsequentrouting phase easy, minimizing the total chip area, and reducingsignal delays .

Each module has a set of implementations, each of which has adifferent area, aspect ratio, delay, and power consumption, andthe best implementation for each module should be obtained .




Placement

Placement, when each module is fixed,that is, has fixed shape and fixedterminals, is the determination of the

best position for each module . Usually,some modules have fixed positions (e .g., 1/O pads) . Although area is the major concern, it is hard to control it . Thus,

alternative cost functions are employed .There are two prevalent cost functions :wire-length-based and cut-based.




Global routing

Global routing decomposes a large routing

problem into small, manageable problems for

detailed routing . The method first partitions

the routing region into a collection of disjointrectilinear subregions . This decomposition is

carried out by finding a "rough" path (i .e.,

sequence of "subregions" it passes) for each

net in order to reduce the chip size, shortenthe wire length, and evenly distribute the

congestion over the routing area .




Detailed routing

Detailed routing follows the global routing to effectivelyrealize interconnections in VLSI circuits. Thetraditional model of detailed routing is the two-layer Manhattan model with reserved layers, where

horizontal wires are routed on one layer and verticalwires are routed in the other layer. For integratedcircuits, the horizontal segments are typically realizedin metal while the vertical segments are realized inpolysilicon . In order to interconnect a horizontal and

vertical segment, a contact (via) must be placed at theintersection points . More recently, the unpreservedlayer model has also been discussed, where verticaland horizontal wires can run in both layers .




Layout optimization & verification

Layout optimization is a post-processing

step . In this stage the layout is

optimized, for example, by compacting

the area .

Layout verification is the testing of a

layout to determine if it satisfies design

and layout rules .




placement & routing problem

We shall refer to the problems related to

location of modules (i .e ., partitioning,

floorplanning, and placement) as the

placement problem, and the problemsrelated to interconnection of terminals (i

.e ., global and detailed routing) as the

routing problem . In addition, there areother post- processing problems, such

as via and bend minimization,




Types of partitioning

The partitioning of a system into a group of

PCBs is called the system level partitioning.

The partitioning of a PCB into chips is called

the board level partitioning while thepartitioning of a chip into smaller subcircuits is

called the chip level partitioning.

At each level, the constraints and objectives of

the partitioning process are different asdiscussed below




System Level Partitioning

The circuit assigned to a PCB must satisfy certainconstraints. Each PCB usually has a fixed area, and afixed number of terminals to connect with other boards. The number of terminals available in one

board (component) to connect to other boards(components) is called the terminal count of the board(component). For example, a typical board hasdimensions 32 cm×15 cm and its terminal count is 64.Therefore, the subcircuit allocated to a board must be

manufacturable within the dimensions of the board. Inaddition, the number of nets used to connect thisboard to the other boards must be within the terminalcount of the board.




System Level Partitioning

The reliability of the system is inversely proportional to thenumber of boards in the system. Hence, one of the objectives of partitioning is to minimize the number of boards. Another important objective is the optimization of the system performance.Partitioning must minimize any degradation of the performancecaused by the delay due to the connections between components

on different boards. The signal carried by a net that is cut bypartitioning at this level has to travel from one board to another board through the system bus. The system bus is very slow asthe bus has to adhere to some strict specifications so that avariety of different boards can share the same bus. The delaycaused by signals traveling between PCBs (off-board delay) playsa major role in determining the system performance as this delayis much larger than the on-board or the on-chip delay.




Board Level Partitioning

The board level partitioning faces a different set of constraints and fulfills a different set of objectives asopposed to system level partitioning. Unlike boards,chips can have different sizes and can accommodatedifferent number of terminals. Typically the dimensions

of a chip range from 2 mm×2 mm to 25 mm×25 mm.The terminal count of a chip depends on the packageof the chip. A Dual In-line Package (DIP) allows only64 pins while a Pin Grid Array (PGA) package mayallow as many as 300 pins. While system level

partitioning is geared towards satisfying the area andthe terminal constraints of each partition, board levelpartitioning ventures to minimize the area of each chip.




Board Level Partitioning

The shift of emphasis is attributable to the cost of manufacturing a chip that is proportional to its area. Inaddition, it is expedient that the number of chips usedfor each board be minimized for enhanced boardreliability. Minimization of the number of chips is

another important determinant of performancebecause the off-chip delay is much larger than the on-chip delay. This differential in delay arises because thedistance between two adjacent transistors on a chip isa few while the distance between two adjacent chips is

in mm. In addition to traversing a longer distance, thesignal has to travel between chips, and through theconnector. The connector used to attach the chip tothe board typically has a high resistance andcontributes significantly to the signal delay.




Chip Level Partitioning

The circuit assigned to a chip can be fabricated as a single unit,therefore, partitioning at this level is necessary. A chip can accommodateas many as three million or more transistors. The fundamental objectiveof chip level partitioning is to facilitate efficient design of the chip. After partitioning, each subcircuit, which is also called a block, can bedesigned independently using either full custom or standard cell designstyle. Since partitioning is not constrained by physical dimensions, there

is no area constraint for any partition. However, the partitions may berestrained by user specified area constraints for optimization of thedesign process. The terminal count for a partition is given by the ratio of the perimeter of the partition to the terminal pitch. The minimum spacingbetween two adjacent terminals is called terminal pitch and is determinedby the design rules. The number of nets which connect a partition toother partitions cannot be greater than the terminal count of the partition.

In addition, the number of nets cut by partitioning should be minimized tosimplify the routing task.




Chip Level Partitioning

The minimization of the number of nets cut by partitioning is oneof the most important objectives in partitioning. A disadvantage of the partitioning process is that it may degrade the performance of the final design. Thus, during partitioning, these criticalcomponents should be assigned to the same partition. If such anassignment is not possible, then appropriate timing constraints

must be generated to keep the two critical components closetogether. Chip performance is determined by several componentsforming a critical path. Assignment of these components todifferent partitions extends the length of the critical path. Thus, amajor challenge for improvement of system performance isminimization of the length of critical path. After a chip has beenpartitioned, each of the subcircuits has to be placed on a fixedplane and the nets between all the partitions have to beinterconnected. The placement of the subcircuits is done by theplacement algorithms and the nets are routed by using routingalgorithms.




Objectives of Partition problem

At any level of partitioning, the input to the partitioning algorithmis a set of components and a netlist. The output is a set of subcircuits which when connected, function as the original circuitand terminals required for each subcircuit to connect it to theother subcircuits. In addition to maintaining the originalfunctionality, partitioning process optimizes certain parameters

subject to certain constraints. The constraints for the partitioningproblem include area constraints and terminal constraints. Theobjective functions for a partitioning problem include theminimization of the number of nets that cross the partitionboundaries, and the minimization of the maximum number of times a path crosses the partition boundaries. The constraintsand the objective functions used in the partitioning problem varydepending upon the partitioning level and the design style used.The actual objective function and constraints chosen for thepartitioning problem may also depend on the specific problem.




Parameter concern in partitioning

Interconnections between partitions: The number of interconnections at any level of partitioning have to be minimized.Reducing the interconnections not only reduces the delay butalso reduces the interface between the partitions making it easier for independent design and fabrication. A large number of interconnections increase the design area as well as complicate

the task of the placement and routing algorithms. Minimization of the number of interconnections between partitions is called themincut problem. The minimization of the cut is a very importantobjective function for partitioning algorithms for any level or anystyle of design.

Delay due to partitioning: The partitioning of a circuit might

cause a critical path to go in between partitions a number of times. As the delay between partitions is significantly larger thanthe delay within a partition, this is an important factor which has tobe considered while partitioning high performance circuits. This isan objective function for partitioning algorithms for all levels of design.





Number of terminals: Partitioning algorithms at any level mustpartition the circuit so that the number of nets required to connecta subcircuit to other subcircuits does not exceed the terminalcount of the subcircuit. In case of system level partitioning, thislimit is decided by the maximum number of terminals available ona PCB connector which connects the PCB to the system bus. In

case of board level partitioning, this limit is decided by the pincount of the package used for the chips. In case of chip levelpartitioning, the number of terminals of a subcircuit is determinedby the perimeter of the area used by the subcircuit.





Area of each partition: In case of system level partitioning, thearea of each partition (board) is fixed and hence this factor appears as a constraint for the system level partitioning problem.In case of board level partitioning, although it is important toreduce the area of each partition (chip) to a minimum to reducethe cost of fabrication, there is also an upper bound on the area

of a chip, Hence, in this case also, the area appears as aconstraint for the partitioning problem. At chip level, the size of each partition is not so important as long as the partitions arebalanced.





Number of partitions: The number of partitions appears as a constraintin the partitioning problem at system level and board level partitioning.This prevents a system from having too many PCBs and a PCB fromhaving too many chips. A large number of partitions may ease the designof individual partitions but they may also increase the cost of fabricationand the number of interconnections between the partitions. At the sametime, if the number of partitions is small, the design of these partitions

might still be too complex to be handled efficiently. At chip level, thenumber of partitions is determined, in part, by the capability of theplacement algorithm. The constraint on the number of partitions can bestated as, Multiway partitioning is normally reduced to a series of two-way or bipartitioning problem. Each component is hierarchicallybipartitioned until the desired number of components is achieved. In thischapter, we will restrict ourselves to bipartitioning. When the two

partitions have the same size, the partitioning process is calledbisectioning and the partitions are called bisections.




Partition for different design style

Full custom design style: In a full custom design style, partitions canbe of different sizes and hence there are no area constraints for thepartitioning algorithms. Thus, the partitioning in full custom design stylehas the most flexibility. During chip level partitioning, the number of terminals allowed for each partition is determined by the perimeter of theblock corresponding to a partition. Since, the cost of manufacturing acircuit is directly proportional to the layout size, it is essential to keep the

area of the layout to a minimum. The area of circuit layout is the sum of the areas occupied by components, areas used for routing the nets, andthe unused areas. Since the areas occupied by the components arefixed, it is only possible to minimize the routing areas and unused areas.The routing area will be largely used by the nets that go across theboundaries of the blocks. The amount of unused areas will bedetermined by the placement. Therefore in addition to the terminal

constraints, partitioning algorithms have to minimize the total number of nets that cross the partition boundaries.




Standard cell design style

The primary objective of the partitioning algorithms in standardcell design style is to partition the circuit into a set of disjointsubcircuits such that each subcircuit corresponds to a cell in astandard cell library. In addition, the partitioning procedure isnonhierarchical. The complexity of partitioning depends on thetype of the standard cells available in the standard cell library. If

the library has only a few simple cell types available, there arefew options for the partitioning procedure and the partitioningproblem has to satisfy constraints and However, if there are manycell types available, some of which are complex, then thepartitioning problem is rather complicated. The objective functionto be optimized by the partitioning algorithms for standard celldesign is For high performance circuits, and are used ascombined objective functions.




Gate array design style

The circuit is bipartitioned recursively

until each resulting partition corresponds

to a gate on the gate array. The objective

for each bipartitioning is to minimize thenumber of nets that cross the partition

boundaries.




Classification of Partitioning

Algorithms

The mincut problem is NP-complete, it follows that general partitioningproblem is also NP-complete [GJ79]. Partitioning algorithms can beclassified in three ways. The first method of classification depends onavailability of initial partitioning. There are two classes of partitioningalgorithms under this classification scheme:

Constructive algorithms and

Iterative algorithms. The input to a constructive algorithms is the circuit components and

thenetlist. The output is a set of partitions and the new netlist.Constructive algorithms are typically used to form some initial partitionswhich can be improved by using other algorithms. In that sense,constructive algorithms are used as preprocessing algorithms for partitioning. They are usually fast, but the partitions generated by these

algorithms may be far from optimal. Iterative algorithms, on the other hand, accept a set of partitions and the

netlist as input and generate an improved set of partitions with themodified netlist. These algorithms iterate continuously until the partitionscannot be improved further.





Algorithms

The partitioning algorithms can also be classified based on thenature of the algorithms. There are two types of algorithms:

Deterministic algorithms and

Probabilistic algorithms.

Deterministic algorithms produce repeatable or deterministic

solutions. For example, an algorithm which makes use of deterministic functions, will always generate the same solution for a given problem.

On the other hand, the probabilistic algorithms are capable of producing a different solution for the same problem each timethey are used, as they make use of some random functions.





Algorithms

The partitioning algorithms can also be

classified on the basis of the process

used for partitioning. Thus we have the

following categories:

Group Migration algorithms,

Simulated Annealing and Evolution

based algorithms and

Other partitioning algorithms.




Process Used For Partitioning

Algorithm

The group migration algorithms [FM82, KL70] start with some partitions, usuallygenerated randomly, and then move components between partitions to improvethe partitioning. The group migration algorithms are quite efficient. However, thenumber of partitions has to be specified which is usually not known when thepartitioning process starts. In addition, the partitioning of an entire system is amulti-level operation and the evaluation of the partitions obtained by thepartitioning depends on the final integration of partitions at all levels, from thebasic subcircuits to the whole system. An algorithm used to find a minimum cut at

one level may sacrifice the quality of cuts for the following levels. The groupmigration method is a deterministic method which is often trapped at a localoptimum and can not proceed further.

The simulated annealing/evolution algorithms carry out the partitioning processby using a cost function, which classifies any feasible solution, and a set of moves, which allows movement from solution to solution. Unlike deterministicalgorithms, these algorithms accept moves which may adversely effect thesolution. The algorithm starts with a random solution and as it progresses, the

proportion of adverse moves decreases.These degenerate moves act as asafeguard against entrapment in local minima. These algorithms arecomputationally intensive as compared to group migration and other methods.

Among all the partitioning algorithms, the group migration and simulatedannealing or evolution have been the most successful heuristics for partitioningproblems. The use of both these types of algorithms is ubiquitous and extensiveresearch has been carried out on them.




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