Dataflow VHDL

Dataflow VHDL

Major instructionsjConcurrent statements

• concurrent signal assignment ()

di i l i l i• conditional concurrent signal assignment(when-else)

l d i l i• selected concurrent signal assignment(with-select-when)

t h f ti• generate scheme for equations (for-generate)

Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens

MLU Block Diagramg

A A1

MUX_0

NEG_AIN0

IN1

IN2

IN3 OUTPUT Y

Y1MUX_1MUX_2

IN3 OUTPUT

SEL1

SEL0

NEG Y

Y

B1B MUX_4_1 NEG_YB1

MUX_3

NEG_BL0L1


MLU Entity Declarationy

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY mlu ISPORT(

NEG_A : IN STD_LOGIC;NEG B : IN STD LOGIC;NEG_B : IN STD_LOGIC;NEG_Y : IN STD_LOGIC;A : IN STD_LOGIC;B : IN STD LOGIC;B : IN STD_LOGIC;L1 : IN STD_LOGIC;L0 : IN STD_LOGIC;Y : OUT STD LOGICY : OUT STD_LOGIC

);END mlu;


MLU Architecture: Declarations

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;SIGNAL B1 : STD LOGIC;SIGNAL B1 : STD_LOGIC;SIGNAL Y1 : STD_LOGIC;SIGNAL MUX_0 : STD_LOGIC;SIGNAL MUX_1 : STD_LOGIC;SIGNAL MUX_2 : STD_LOGIC;SIGNAL MUX 3 : STD LOGIC;SIGNAL MUX_3 : STD_LOGIC;SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);


MLU Architecture: BodyyBEGIN

A1<= NOT A WHEN (NEG_A='1') ELSEAA;

B1<= NOT B WHEN (NEG_B='1') ELSE B;

Y <= NOT Y1 WHEN (NEG Y='1') ELSE( _ )Y1;

MUX_0 <= A1 AND B1;MUX 1 <= A1 OR B1;MUX_1 < A1 OR B1;MUX_2 <= A1 XOR B1;MUX_3 <= A1 XNOR B1;

L <= L1 & L0;L < L1 & L0;

with (L) selectY1 <= MUX_0 WHEN "00",

MUX_1 WHEN "01",MUX_2 WHEN "10",MUX_3 WHEN OTHERS;


END mlu_dataflow;

FOR … GENERATE

F G tFor - Generate

label: FOR identifier IN range GENERATEBEGIN{Concurrent Statements}

END GENERATE;


PARITY Example


PARITY: Entity Declarationy


ENTITY parity ISPORT(

it i IN STD LOGIC VECTOR(7 DOWNTO 0)parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);parity_out : OUT STD_LOGIC

);END parity;


PARITY: Block Diagramg

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor out(5)xor_out(5) xor_out(6)


PARITY: ArchitectureARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: std_logic_vector (6 downto 1);

BEGIN

t(1) it i (0) XOR it i (1)xor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor out(6) <= xor out(5) XOR parity in(6);_ ( ) _ ( ) p y_ ( );parity_out <= xor_out(6) XOR parity_in(7);

END parity dataflow;Microprocessors & Digital Systems Laboratory

© 2009 National Technical University of Athens

END parity_dataflow;

PARITY: Block Diagram 2g

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor out(5)

xor_out(0)

xor_out(5) xor_out(6)xor_out(7)


PARITY: Architecture 2

ARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);

BEGINBEGIN

xor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);

t(4) < t(3) XOR it i (4)xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor out(7) <= xor out(6) XOR parity in(7);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7);

END parity dataflow;Microprocessors & Digital Systems Laboratory



PARITY: Architecture 3

ARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

xor out(0) <= parity in(0);_ ( ) p y_ ( );

G2: FOR i IN 1 TO 7 GENERATExor out(i) <= xor out(i-1) XOR parity in(i);xor_out(i) < xor_out(i 1) XOR parity_in(i);

end generate G2;

parity out <= xor out(7);parity_out <= xor_out(7);



Simple Rules

For combinational logic,For combinational logic,use only concurrent statements

• concurrent signal assignment ()• conditional concurrent signal assignment• conditional concurrent signal assignment

(when-else)• selected concurrent signal assignment• selected concurrent signal assignment

(with-select-when)• generate scheme for equations• generate scheme for equations

(for-generate)


Simple Rules

F i it d fFor circuits composed of - simple logic operations (logic gates)- simple arithmetic operations (addition,subtraction, multiplication)subt act o , u t p cat o )

- shifts/rotations by a constantuseuse

• concurrent signal assignment ()


Simple Rules

For circuits composed of - multiplexers- decoders, encodersdecoders, encoders- tri-state buffers

useuse

diti l t i l i t• conditional concurrent signal assignment(when-else)

l t d t i l i t• selected concurrent signal assignment(with-select-when)


Left vs Right Side of Assignmentsg g

<=Left side Right side<= when-elsewith-select <=

g

with select <

Expressions including:• Internal signals (defined

in a given architecture)• Ports of the mode

Expressions including:• Internal signals (defined

in a given architecture)• Ports of the mode

- out- inout

• Ports of the mode- in

inoutinout- buffer

- inout- buffer


Arithmetic Operators

Synthesizable arithmetic operations:Sy t es ab e a t et c ope at o s Addition, + Subtraction, -Subtraction, Comparisons, >, >=, <, <= Multiplication *Multiplication, Division by a power of 2, /2**6

(equivalent to right shift)( q g ) Shifts by a constant, SHL, SHR


Arithmetic Operators

The result of synthesis of an arithmeticoperation is a- combinational circuitcombinational circuit- without pipelining.

The exact internal architecture used (and thus delay and area of the circuit)(and thus delay and area of the circuit)may depend on the timing constraints specifiedd i th i ( th t d iduring synthesis (e.g., the requested maximumclock frequency).


QuestionsQuestions


Anatomy of a Processy

OPTIONALOPTIONAL

[label:] process [(sensitivity list)][declaration part]

begingstatement part

end process [label];end process [label];


Statement Part

Contains Sequential Statements to be Executed Each Time the Process Is Activated

Analogous to Conventional Programming Languages


What is a Process

A process is a sequence of instructions referred to as sequential statements

A process can be given a unique name using an optional LABEL TESTING: process

sequential statements.The Keyword PROCESS

using an optional LABEL

This is followed by the keyword PROCESS

pbegin

TEST_VECTOR<=“00”;wait for 10 ns;TEST VECTOR<=“01”;

The keyword BEGIN is used to indicate the start of the process

TEST_VECTOR<= 01 ;wait for 10 ns;TEST_VECTOR<=“10”;wait for 10 ns;TEST VECTOR “11” All statements within the process are

executed SEQUENTIALLY. Hence, order of statements is important.

TEST_VECTOR<=“11”;wait for 10 ns;

end process;

A process must end with the keywords END PROCESS.


Execution of Statements

Testing: PROCESS

The execution of statements

BEGINtest_vector<=“00”;WAIT FOR 10 ns; The execution of statements

continues sequentially till the last statement in the process.

After execution of the last r of e

xecu

tion

WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;

After execution of the last statement, the control is again passed to the beginning of the process

Ord

er test_vector<=“10”;WAIT FOR 10 ns;test vector<=“11”;process. test_vector< 11 ;WAIT FOR 10 ns;

END PROCESS;

Program control is passed to the first statement after BEGIN


BEGIN

WAIT Statement

The last statement in the Testing: PROCESSPROCESS is a WAIT instead of WAIT FOR 10 ns.

This will cause the PROCESS

BEGINtest_vector<=“00”;WAIT FOR 10 ns;to suspend indefinitely when

the WAIT statement is executed.

WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;

r of e

xecu

tion

This form of WAIT can be used in a process included in a testbench when all possible

test_vector<=“10”;WAIT FOR 10 ns;test vector<=“11”;

Ord

er

combinations of inputs have been tested or a non-periodical signal has to be generated.

test_vector< 11 ;WAIT;

END PROCESS;

Program execution stops here


here

WAIT FOR vs WAIT

WAIT FOR: waveform will keep repeating p p gitself forever

0 1 2 3 0 1 2 3 …

WAIT : waveform will keep its state after theWAIT : waveform will keep its state after the last wait instruction.

…Microprocessors & Digital Systems Laboratory


Sensitivity Listy

List of signals to which the gprocess is sensitive.

Whenever there is an t f thevent on any of the

signals in the sensitivity list, the process fires.

label: process (sensitivity list)declaration part , p

Every time the process fires, it will run in its

ti t

beginstatement part

entirety. WAIT statements are

NOT ALLOWED in a

end process;

NOT ALLOWED in a processes with SENSITIVITY LIST.


Process Suitabilityy

Processes Describe Sequential Behavior

Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to

represent by a real circuit Not every process can be synthesized Not every process can be synthesized

Use Processes with Caution in the Code to Be Synthesized

Use Processes Freely in Testbenches


Component Equivalent of a Process

yclk

priority: PROCESS (clk)BEGIN

IF w(3) = '1' THEN

wa z

prioritybc

All signals which appear on the left of signal assignment statement (<=)

t t

IF w(3) = 1 THENy <= "11" ;

ELSIF w(2) = '1' THEN y <= "10" ; are outputs e.g. y, z

All signals which appear on the right of signal assignment statement (<=)

y < 10 ;ELSIF w(1) = c THEN

y <= a and b;ELSE g g ( )

or in logic expressions are inputse.g. w, a, b, c

All signals which appear in the

ELSEz <= "00" ;

END IF ;END PROCESS ; g pp

sensitivity list are inputs e.g. clk Note that not all inputs need to be

included in the sensitivity list

;


included in the sensitivity list

IF Statement - Syntaxy

If Statement

if boolean expression thenstatementsstatements

elsif boolean expression thenstatements

else boolean expression thenstatements

end if;

else and elsif are optional


p

IF Statement: Example

SELECTOR: processbegin

WAIT UNTIL Cl k'EVENT AND Cl k '1'WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Sel = “00” THEN

f <= x1;f <= x1;ELSIF Sel = “10” THEN

f <= x2;;ELSE

f <= x3;END IFEND IF;

end process;


2-to-4 Decoder

y 0

w 1

w 0 En y

1 y 2

y 3

w y0

0 1

0 1

1 0

1

1

0

0

0

0

0 w

0 y 0

w 1

y 1

1

1

0

1

1

1

0

0

0

0

1

0

0

1 En

y 2

y 3

x x 0 0 0 0 0

( ) T th t bl (b) G hi l(a) Truth table (b) Graphical symbol


Dataflow DescriptionLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD LOGIC ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= “0001" WHEN "100","0010" WHEN "101"0010 WHEN 101 ,"0100" WHEN "110",“1000" WHEN "111","0000" WHEN OTHERS ;


0000 WHEN OTHERS ;END dataflow ;

Behavioral DescriptionLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 ISENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISBEGIN

PROCESS ( w En )PROCESS ( w, En )BEGIN

IF En = '1' THENCASE w IS

WHEN "00" => y <= "1000" ;WHEN 00 => y <= 1000 ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;

END CASE ;END CASE ;ELSE

y <= "0000" ;END IF ;

END PROCESS ;


END PROCESS ;END Behavior ;

7 Segment Displayg yLIBRARY ieee ; USE ieee.std_logic_1164.all ;ENTITY seg7 IS

PORT ( bcd : IN STD LOGIC VECTOR(3 DOWNTO 0) ;PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGINBEGIN

PROCESS ( bcd )BEGIN

CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN 0000 leds 1111110 ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN 0100 leds 0110011 ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN 1000 leds 1111111 ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;

END CASE ;END PROCESS ;



ComparatorLIBRARY ieee ;USE ieee.std logic 1164.all ;USE ieee.std_logic_1164.all ;

ENTITY compare1 ISPORT ( A, B : IN STD LOGIC ;( , _ ;

AeqB : OUT STD_LOGIC ) ;END compare1 ;

ARCHITECTURE Behavior OF compare1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

A B '1'AeqB <= '1' ;END IF ;



END Behavior ;

Latch InferenceLIBRARY ieee ;USE ieee.std logic 1164.all ;_ g _ ;

ENTITY implied ISPORT ( A B : IN STD LOGIC ;PORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A B )PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;


END Behavior ;

Latch Inference

A B AeqBB AeqB


Combinational Circuits with Processes

Rules that need to be followed:

1. All inputs to the combinational circuit should be includedincluded in the sensitivity list

2. No other signals should be included gin the sensitivity list

3. None of the statements within the process should be sensitive to rising or falling edges

4. All possible cases need to be covered in the internalIF and CASE statements in order to avoidIF and CASE statements in order to avoidimplied latches


Covering all Combinations with IFg

Using ELSE

IF A = B THENAeqB <= '1' ;q ;

ELSEAeqB <= '0' ;

Using default values

AeqB <= '0' ;IF A = B THENIF A B THEN

AeqB <= '1' ;


Covering all Combinations with CASEg

Using WHEN OTHERSCASE ISCASE y IS

WHEN S1 => Z <= "10";WHEN S2 => Z <= "01";

CASE y ISWHEN S1 => Z <= "10";WHEN S2 => Z <= "01";WHEN S2 Z 01 ;

WHEN OTHERS => Z <= "00";END CASE;

WHEN S3 => Z <= "00";WHEN OTHERS => Z <= „--";

END CASE;

Using default values

;

Z <= "00";CASE y IS

WHEN S1 => Z <= "10";WHEN S1 => Z <= 10 ;WHEN S2 => Z <= "10";

END CASE;


Sequential Logic: D LatchgTruth table Graphical symbol

Clock D 0 1

–0 0

Q(t+1)Q(t)

D Q

Cl k 1 1

0 1

0 1

Clock

t 1 t 2 t 3 t 4

Timing diagram

Clock

D

Ti

D

Q


Time

Sequential Logic: D Flip-flopgTruth table Graphical symbol

Clk D

0 1

0 1

Q(t+1)D Q

1 1 Q(t)

Clock 0 –

Q(t)1 –

t 1 t 2 t 3 t 4

Timing diagramQ(t)

Clock

D

Ti

D

Q


Time

VHDL Code: D Latch

LIBRARY ieee ; USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT ( D Clock : IN STD LOGIC ;

D Q

Clock PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ;

END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clock ) ( )BEGIN

IF Clock = '1' THENQ <= D ;

END IF ; END PROCESS ;

END Behavior;


VHDL Code: D Flip-flop


ENTITY flipflop IS PORT ( D, Clock : IN STD LOGIC ;

D Q

Cl kPORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ;

END flipflop ;

Clock

ARCHITECTURE Behavior_1 OF flipflop IS BEGIN

PROCESS ( Clock ) BEGIN

IF Clock'EVENT AND Clock = '1' THEN Q <= D ;


END Behavior_1 ;




ENTITY flipflop IS PORT ( D, Clock : IN STD LOGIC ;

D Q


END flipflop ;

Clock


PROCESS ( Clock ) BEGIN

IF rising_edge(Clock) THEN Q <= D ;


END Behavior_1 ;



LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D Cl k IN STD LOGIC

D Q


END flipflop ;

Clock


PROCESSPROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;Q <= D ;Q < D ;

END PROCESS ; END Behavior_2 ;




ENTITY flipflop IS PORT ( D Clock : IN STD LOGIC ;

D Q


END flipflop ;

Clock


PROCESSPROCESSBEGIN

WAIT UNTIL rising_edge(Clock) ;Q <= D ; ;

END PROCESS ; END Behavior_2 ;


VHDL Code: D Flip-flop Async ResetyLIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD LOGIC) ;

D Q

ClockQ : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS

Clock

Resetn

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Resetn, Clock ) BEGINBEGIN

IF Resetn = '0' THEN Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THENELSIF Clock EVENT AND Clock 1 THEN Q <= D ;



;END Behavior ;

VHDL Code: D Flip-flop Sync ResetyLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fli fl ISENTITY flipflop IS

PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ;

END flipflop ;

D Q

ClockEND flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

Clock

Resetn

BEGINPROCESS BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;WAIT UNTIL Clock EVENT AND Clock 1 ;IF Resetn = '0' THEN

Q <= '0' ; ELSEELSE

Q <= D ; END IF ;

END PROCESS ;


;END Behavior ;

QuestionsQuestions


Variables: Example

LIBRARY iLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY Numbits ISPORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ;

Count : OUT INTEGER RANGE 0 TO 3) ;END Numbits ;


Variables: Example

ARCHITECTURE Behavior OF Numbits IS

BEGIN

PROCESS(X) – count the number of bits in X equal to 1PROCESS(X) count the number of bits in X equal to 1VARIABLE Tmp: INTEGER;

BEGINTmp := 0;p 0;FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THENTmp := Tmp + 1;p p

END IF;END LOOP;Count <= Tmp;

END PROCESS;

END Behavior ;


Variables: Features

Can only be declared within processes and subprograms (functions & procedures)subprograms (functions & procedures)

Initial value can be explicitly specified in the Initial value can be explicitly specified in the declaration

When assigned take an assigned value immediately

Variable assignments represent the desired behavior, not the structure of the circuit

Should be avoided, or at least used with caution in a synthesizable code


synthesizable code

Variable vs Signal – Variable Exampleg

ARCHITECTURE Behavior OF Numbits IS

BEGIN

PROCESS(X) – count the number of bits in X equal to 1PROCESS(X) count the number of bits in X equal to 1VARIABLE Tmp: INTEGER;

BEGINTmp := 0;p 0;FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THENTmp := Tmp + 1;p p

END IF;END LOOP;Count <= Tmp;

END PROCESS;

END Behavior ;


Variable vs Signal – Signal Exampleg gARCHITECTURE Behavior OF Numbits IS

SIGNAL Tmp : INTEGER RANGE 0 TO 3 ;

BEGIN

PROCESS(X) – count the number of bits in X equal to 1BEGIN

Tmp <= 0;FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THEN1Tmp <= Tmp + 1;

END IF;END LOOP;C t < TCount <= Tmp;

END PROCESS;

END Behavior ;


END Behavior ;

Variable vs Signal: NAND Gateg


ENTITY NANDn ISGENERIC (n: INTEGER := 8)PORT ( X : IN STD_LOGIC_VECTOR(1 TO n);

Y : OUT STD_LOGIC);END NANDn;


Variable vs Signal: NAND Gate - VargARCHITECTURE behavioral1 OF NANDn ISBEGINBEGIN

PROCESS (X) VARIABLE Tmp: STD LOGIC;VARIABLE Tmp: STD_LOGIC;

BEGINTmp := X(1);

AND_bits: FOR i IN 2 TO n LOOPTmp := Tmp AND X( i ) ;

END LOOP AND bitEND LOOP AND_bits ;

Y <= NOT Tmp ;

END PROCESS;


END behavioral1 ;

Variable vs Signal: NAND Gate - Signalg gARCHITECTURE behavioral2 OF NANDn IS

SIGNAL Tmp: STD LOGIC;SIGNAL Tmp: STD_LOGIC;BEGIN

PROCESS (X)PROCESS (X) BEGINTmp <= X(1);

AND_bits: FOR i IN 2 TO n LOOPTmp <= Tmp AND X( i ) ;

END LOOP AND bitEND LOOP AND_bits ;

Y <= NOT Tmp ;

END PROCESS;


END behavioral2 ;

Variable vs Signal: NAND Gate - Signalg g

ARCHITECTURE dataflow1 OF NANDn ISARCHITECTURE dataflow1 OF NANDn IS

SIGNAL Tmp: STD_LOGIC_VECTOR(1 TO n);

BEGINTmp(1) <= X(1);

AND_bits: FOR i IN 2 TO n GENERATETmp(i) <= Tmp(i-1) AND X( i ) ;

END LOOP AND_bits ;

Y <= NOT Tmp(n) ;p( ) ;

END dataflow1 ;


QuestionsQuestions


Structural VHDL

Major instructions

component instantiation (port map)

j

p (p p) generate scheme for component instantiations

(for-generate)( g ) component instantiation with generic

(generic map, port map)(g p, p p)


Structural VHDL

Major instructions


j

p (p p) component instantiation with generic

(generic map, port map)(g p, p p) generate scheme for component instantiations

(for-generate)( g )


Structural VHDL: Examples(0)

0r(0) p(0) En

w 0 y 0 w 0

y 0

1r(1)

p(1)q(0)

(1) (0) (0)Enable

y0

y 1

z

w 1

w 2

0 0 w

1 y 1

y

r(2)

r(3)p(2)

q(1)

ena

z(0)

z(1)

z(0)

z(1)D Q

w 3z

En

y 2

y 3

0r(4) p(3)z(2)

z(3)dec2to4

priority z(2)

z(3)regn1r(5) dec2to4 regn

Clk Clock


s(1)

2-to-1 Multiplexer

fss

0 w0f

w0 0

1

0

w1

fw

1 1

(a) Graphical symbol (b) Truth table


VHDL Code for 2-to-1 Multiplexer

LIBRARY ieee ;LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux2to1 ISPORT (w0, w1, s : IN STD_LOGIC ;

f OUT STD LOGIC )f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE dataflow OF mux2to1 ISBEGIN

f <= w0 WHEN s = '0' ELSE w1 ;END dataflow ;


Priority Encodery

w 0 y 0

y 1w 1

w

w 3z

w 2

w0 y1 y0 zw1w2w3

d00

01

d 011

1x

001

000

000

0

01

10

1 1 1

11

xxx

1xx

01x

001


VHDL Code for Priority EncoderyLIBRARY ieee ;USE ieee.std_logic_1164.all ;_ g _

ENTITY priority ISPORT ( w : IN STD LOGIC VECTOR(3 DOWNTO 0) ;PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;END priority ;

ARCHITECTURE dataflow OF priority ISBEGINBEGIN

y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN (1) '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;


END dataflow ;

2-to-4 Decoder

y 0

w 1

w 0 En y

1 y 2

y 3

w y0

0 1

0 1

1 0

1

1

0

0

0

0

0 w

0 y 0

w 1

y 1

1

1

0

1

1

1

0

0

0

0

1

0

0

1 En

y 2

y 3

x x 0 0 0 0 0

( ) T th t bl (b) G hi l(a) Truth table (b) Graphical symbol


VHDL Code for 2-to-4 DecoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD LOGIC ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= “0001" WHEN "100","0010" WHEN "101"0010 WHEN 101 ,"0100" WHEN "110",“1000" WHEN "111","0000" WHEN OTHERS ;


0000 WHEN OTHERS ;END dataflow ;

N-bit Register with EnablegLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;( ( )

Enable, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS (Clock) EnableN NBEGIN

IF (Clock'EVENT AND Clock = '1' ) THENIF Enable = '1' THEN

Q <= D ;

QD

Q <= D ;END IF ;

END IF;END PROCESS ;

Clock

regn


END Behavior ;

Circuit Built with Componentss(0)

0r(0) p(0) En

w 0 y 0 w 0

y 0

1r(1)

p(1)q(0)

(1) (0) t(0)Enable

y0

y 1

z

w 1

w 2

0 0 w

1 y 1

y

r(2)

r(3)p(2)

q(1)

ena

z(0)

z(1)

t(0)

t(1)D Q

w 3z

En

y 2

y 3

0r(4) p(3)z(2)

z(3)dec2to4

priority t(2)

t(3)regn1r(5) dec2to4 regn

Clk Clock


s(1)

Structural DescriptionLIBRARY ieee ;USE ieee.std logic 1164.all ;_ g _ ;

ENTITY priority_resolver ISPORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;( ( )

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;clk : IN STD_LOGIC;en : IN STD_LOGIC;t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END priority_resolver;

ARCHITECTURE t t l OF i it l ISARCHITECTURE structural OF priority_resolver IS

SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;SIGNAL STD LOGIC VECTOR (1 DOWNTO 0)SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ;SIGNAL ena : STD_LOGIC ;


Structural DescriptionCOMPONENT mux2to1

PORT (w0, w1, s : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;

END COMPONENT ;

COMPONENT priorityPORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END COMPONENT ;END COMPONENT ;

COMPONENT dec2to4PORT ( IN STD LOGIC VECTOR(1 DOWNTO 0)PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;


END COMPONENT ;

Structural Description

COMPONENT regnGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Enable, Clock : IN STD_LOGIC ;Q : OUT STD LOGIC VECTOR(N-1 DOWNTO 0) ) ;Q _ _ ( ) ) ;

END COMPONENT ;


Structural DescriptionBEGIN

u1: mux2to1 PORT MAP (w0 => r(0)u1: mux2to1 PORT MAP (w0 => r(0) ,w1 => r(1),s => s(0),f => p(0));

p(1) <= r(2);p(1) <= r(3);

u2: mux2to1 PORT MAP (w0 => r(4)u2: mux2to1 PORT MAP (w0 => r(4) ,w1 => r(5),s => s(1),f => p(3));

u3: priority PORT MAP (w => p,y => q,z => ena);z => ena);

u4: dec2to4 PORT MAP (w => q,En => ena,


y => z);

Structural Description

u5: regn GENERIC MAP (N => 4)u5: regn GENERIC MAP (N > 4)

PORT MAP (D => z ,

Enable => En ,Cl k ClkClock => Clk,Q => t );

END structural;


Structural Description – Pos. Assoc.

BEGIN

u1: mux2to1 PORT MAP (r(0), r(1), s(0), p(0));

p(1) <= r(2);

p(1) <= r(3);

u2: mux2to1 PORT MAP (r(4) r(5) s(1) p(3));u2: mux2to1 PORT MAP (r(4) , r(5), s(1), p(3));

u3: priority PORT MAP (p, q, ena);

u4: dec2to4 PORT MAP (q, ena, z);

u5: regn GENERIC MAP(4) PORT MAP (z, En, Clk, t);

END structural;


Configuration Declarationg

CONFIGURATION SimpleCfg OF priority_resolver IS

FOR structural

FOR ALL: mux2to1USE ENTITY k 2t 1(d t fl )USE ENTITY work.mux2to1(dataflow);

END FOR;

FOR u3: priorityFOR u3: priority USE ENTITY work.priority(dataflow);

END FOR;

FOR 4 d 2t 4FOR u4: dec2to4USE ENTITY work.dec2to4(dataflow);

END FOR;

END FOR;

END SimpleCfg;


Configuration SpecificationgLIBRARY ieee ;USE ieee.std_logic_1164.all ;USE k G t Pk llUSE work.GatesPkg.all;

ENTITY priority_resolver ISPORT (r : IN STD LOGIC VECTOR(5 DOWNTO 0) ;( _ _ ( ) ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END priority_resolver;

ARCHITECTURE structural OF priority_resolver IS

SIGNAL p : STD LOGIC VECTOR (3 DOWNTO 0) ;p _ _ ( ) ;SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;SIGNAL ena : STD_LOGIC ;

FOR ALL 2t 1 USE ENTITY k 2t 1(d t fl )FOR ALL: mux2to1 USE ENTITY work.mux2to1(dataflow);FOR u3: priority USE ENTITY work.priority(dataflow);FOR u4: dec2to4 USE ENTITY work.dec2to4(dataflow);


Structural VHDL

Major instructions


j

p (p p) component instantiation with generic

(generic map, port map)(g p, p p) generate scheme for component instantiations

(for-generate)( g )


16-to-1 Multiplexer

s 1

s 0

w 0

w 3

w 4 s 3

s 2

w 7

f

w 8

w 11

w 12


w 15

VHDL Code for 4-to-1 MultiplexerLIBRARY ieee ;USE ieee.std logic 1164.all ;_ g _ ;

ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;(

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE Dataflow OF mux4to1 ISBEGIN

WITH SELECTWITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",2 WHEN "10"w2 WHEN "10",

w3 WHEN OTHERS ;END Dataflow ;


Straightforward Code for 16-to-1 MUXg

LIBRARY ieee ;USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;

ENTITY Example1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;

s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;f : OUT STD LOGIC ) ;f : OUT STD_LOGIC ) ;

END Example1 ;


Straightforward Code for 16-to-1 MUX g

ARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD LOGIC VECTOR(1 DOWNTO 0) ;_ _ ( ) ;f : OUT STD_LOGIC ) ;

END COMPONENT ;

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGINM 1 4t 1 PORT MAP ( (0) (1) (2) (3) (1 DOWNTO 0) (0) )Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;Mux4: mux4to1 PORT MAP ( w(12) w(13) w(14) w(15) s(1 DOWNTO 0) m(3) ) ;Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


Modified Code for 16-to-1 MUXARCHITECTURE Structure OF Example1 IS

COMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;_ _ ( )f : OUT STD_LOGIC ) ;

END COMPONENT ;

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;


QuestionsQuestions


Array Attributesy

A’left(N) left bound of index range of dimension N of A

A’right(N) right bound of index range of dimension N of A

A’low(N) lower bound of index range of dimension N of AA low(N) lower bound of index range of dimension N of A

A’high(N) upper bound of index range of dimension N of A

A’range(N) index range of dimension N of A

A’reverse range(N) reversed index range of dimension N of AA reverse_range(N) reversed index range of dimension N of A

A’length(N) length of index range of dimension N of A

A’ascending(N) true if index range of dimension N of A

is an ascending range, false otherwiseMicroprocessors & Digital Systems Laboratory


is an ascending range, false otherwise

Array Attributes: Exampley

type A is array (1 to 4, 31 downto 0);

A’left(1) = 1A left(1) = 1

A’right(2) = 0

A’low(1) = 1

A’high(2) = 31A high(2) = 31

A’range(1) = 1 to 4

A’length(2) = 32

A’ascending(2) = falseMicroprocessors & Digital Systems Laboratory


A ascending(2) false

Attributes of Scalar Typesy

T’left first (leftmost) value in TT’ i ht l t ( i ht t) l i TT’right last (rightmost) value in TT’low least value in TT’hi h t t l i TT’high greatest value in T

N t il bl i VHDL 87Not available in VHDL-87:T’ascending

t if T i di f ltrue if T is an ascending range, falseotherwise

T’image(x)a string representing the value of xT image(x)a string representing the value of xT’value(s) the value in T that is represented by s


Attributes of Scalar Types: Examplesy

type index range is range 21 downto 11;type index_range is range 21 downto 11;

i d ’l ft 21index_range’left = 21index_range’right = 11index_range’low = 11index_range’high = 21_ g gindex_range’ascending = falseindex range’image(14) = “14”index_range image(14) 14index_range’value(“20”) = 20


Attributes of Discrete Typesy

T’pos(x) position number of x in Tp ( ) pT’val(n) value in T at position nT’succ(x) value in T at position one greaterT succ(x) value in T at position one greater

than position of xT’ d( ) l i T t iti lT’pred(x) value in T at position one less

than position of xT’leftof(x) value in T at position one to the

left of xT’rightof(x) value in T at position one to the

right of xMicroprocessors & Digital Systems Laboratory


g

Attributes of Discrete Types:Examplesy

type logic level is (unknown low undriven high);type logic_level is (unknown, low, undriven, high);

l i l l’ ( k ) 0logic_level’pos(unknown) = 0logic_level’val(3) = highlogic_level’succ(unknown) = lowlogic_level’pred(undriven) = lowg _ p ( )logic_level’leftof(unknown) errorlogic level’rightof(undriven) = highlogic_level rightof(undriven) high


Attributes of Signalsg signal_name'event

returns true if there is a change in a value of the signal.returns true if there is a change in a value of the signal. signal_name'active

returns true if a value was assigned to the signal (even if the new value is the same as the current signal value).the same as the current signal value).

signal_name‘transactionbit that returns true if a value was assigned to the signal (even if the new value is the same as the current signal value).value is the same as the current signal value).

signal_name'last_eventreturns the elapsed time since the last event that happened to the signal.

signal name'last active signal_name last_activereturns the elapsed time since the last time that the signal was active.

signal_name'last_valuereturns the last value that was assigned to the signalreturns the last value that was assigned to the signal.


QuestionsQuestions


Testbenches

Testbench

Processes

GeneratingDesign Under

Test (DUT)Generating

StimuliTest (DUT)

Observed OutputsObse ed Outputs


Testbench Definition

Testbench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.

The results can be viewed in a waveform window or written to a file.

Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability)restricted to a single simulation tool (portability).

The same Testbench can be easily adapted to test different implementations (i e differenttest different implementations (i.e. different architectures) of the same design.


Testbench TemplateENTITY tb IS

--TB entity has no ports END tb;

ARCHITECTURE arch_tb OF tb IS

--Local signals and constants

COMPONENT TestComp --All Design Under Test component declarationsPORT ( );

END COMPONENT;-----------------------------------------------------BEGIN

testSequence: PROCESS-- Input stimuli

END PROCESS;

DUT:TestComp PORT MAP( -- Instantiations of DUTs);

END arch tb;


a c _tb;

Generating Selected ValuesgSIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

BEGIN.......

testing: PROCESStesting: PROCESS BEGIN

test_vector <= "000";WAIT FOR 10 ns;test_vector <= "001";WAIT FOR 10 ns;test_vector <= "010";WAIT FOR 10WAIT FOR 10 ns;test_vector <= "011";WAIT FOR 10 ns;test vector <= "100";test_vector < 100 ;WAIT FOR 10 ns;

END PROCESS;........


END behavioral;

Generating all Valuesg

SIGNAL test vector : STD LOGIC VECTOR(3 downto 0):="0000";SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):= 0000 ;

BEGIN.......

testing: PROCESSBEGINBEGIN

WAIT FOR 10 ns;test_vector <= test_vector + 1;

d TESTINGend process TESTING;

........END b h i lEND behavioral;


Generating all ValuesgSIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);SIGNAL test sel : STD LOGIC VECTOR(1 downto 0);SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);

BEGIN.......

double_loop: PROCESSBEGIN

test_ab <="00";_test_sel <="00";for I in 0 to 3 loop

for J in 0 to 3 loopwait for 10 ns;

test_ab <= test_ab + 1;end loop;test_sel <= test_sel + 1;

end loop;END PROCESS;

........END b h i l


END behavioral;

Generating Periodic Signalsg gCONSTANT clk1_period : TIME := 20 ns;CONSTANT clk2_period : TIME := 200 ns;_pSIGNAL clk1 : STD_LOGIC;SIGNAL clk2 : STD_LOGIC := ‘0’;

BEGIN.......clk1_generator: PROCESS

clk1 <= ‘0’;WAIT FOR clk1_period/2;clk1 <= ‘1’;;WAIT FOR clk1_period/2;

END PROCESS;

clk2 <= not clk2 after clk2_period/2;.......

END behavioral;


END behavioral;

Generating 1 Time Signalsg gCONSTANT reset1_width : TIME := 100 ns;CONSTANT reset2_width : TIME := 150 ns;SIGNAL reset1 : STD_LOGIC;SIGNAL reset2 : STD_LOGIC := ‘1’;

BEGINBEGIN.......reset1_generator: PROCESS

reset1 <= ‘1’;WAIT FOR reset_width;reset1 <= ‘0’;WAIT;

END PROCESSEND PROCESS;reset2_generator: PROCESS

WAIT FOR reset_width;reset2 <= ‘0’;reset2 < 0 ;WAIT;

END PROCESS;.......


END behavioral;

QuestionsQuestions


Structure of a Digital Systemg y

Data Inputs Control InputsData Inputs Control Inputs

Control

Execution Unit

ControlUnit

Signals

Unit(Datapath)

Unit(Control)

Data Outputs Control Outputs


Datapath

Provides All Necessary Resources and I t t A Th t P f S ifi dInterconnects Among Them to Perform Specified Task

Examples of ResourcesAdders Multipliers Registers Memories etco Adders, Multipliers, Registers, Memories, etc.


Control

Controls Data Movements in an Operational Circuit b S it hi M lti l d E bli Di bliby Switching Multiplexers and Enabling or Disabling Resources

Follows Some ‘Program’ or Schedule

Often Implemented as Finite State Machine or collection of Finite State Machinescollection of Finite State Machines


Moore FSM

Output Is a Function of a Present State Only

Next StateInputsfunction

Present StateNext State

Present StateR i t

Present StateNext State

clockt Registerreset

Outputfunction

Outputs


function

Mealy FSMy Output Is a Function of a Present State and

InputsInputs

Next StateInputsfunction

Present StateNext State Present StateNext State

Present StateR i t

clockt Registerreset

Outputfunction

Outputs


function

Moore FSM

transitioncondition 1

state 1 / state 2 /

condition 1

output 1 output 2transitioncondition 2


Mealy FSMy

transition condition 1 /output 1

state 1 state 2

output 1

state 1 state 2transition condition 2 /

output 2


FSMs in VHDL

Finite State Machines Can Be Easily Described With te State ac es Ca e as y esc bed tProcesses

Synthesis Tools Understand FSM Description If Certain Rules Are Followedo State transitions should be described in a process sensitive to

clock and asynchronous reset signals onlyOutputs described as concurrent statements outside theo Outputs described as concurrent statements outside the process


Moore FSM in VHDL

TYPE state IS (S0, S1, S2);SIGNAL M t t t tSIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)BEGIN

IF(reset = ‘1’) THENMoore state <= S0;Moore_state S0;

ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS

WHEN S0 =>WHEN S0 =>IF input = ‘1’ THEN

Moore_state <= S1; ELSE

Moore_state <= S0;END IF;


Moore FSM in VHDL

WHEN S1 =>IF input = ‘0’ THENIF input = 0 THEN


Moore state <= S1;Moore_state < S1; END IF;

WHEN S2 =>IF input = ‘0’ THENp


Moore_state <= S1; _END IF;

END CASE;END IF;

END PROCESS;

Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;


State Diagramg

Moore FSM that Recognizes Sequence “10”

00

1

1S0 / 0 S1 / 0 S2 / 111

0reset


Mealy FSM in VHDLy

TYPE state IS (S0, S1);SIGNAL M l t t t tSIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)BEGIN

IF(reset = ‘1’) THENMealy state <= S0;Mealy_state S0;

ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS

WHEN S0 =>WHEN S0 =>IF input = ‘1’ THEN

Mealy_state <= S1; ELSE

Mealy_state <= S0;END IF;


Mealy FSM in VHDLy

WHEN S1 =>IF input = ‘0’ THENIF input = ‘0’ THEN

Mealy_state <= S0; ELSE

M l S1Mealy_state <= S1;END IF;

END CASE;END IF;

END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;


State Diagramg

Mealy FSM that Recognizes Sequence “10”

0 / 0 1 / 0 1 / 0

S0 S1

0 / 1reset


Thank you for your attentionThank you for your attention

QuestionsQuestions


Dataflow VHDL

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