1 ECE 545 – Introduction to VHDL Dataflow Modeling of Combinational Logic Simple Testbenches ECE...

ECE 545 – Introduction to VHDL 1

Dataflow Modeling of

Combinational Logic

Simple Testbenches

ECE 656. Lecture 2


Resources

• Volnei A. Pedroni, Circuit Design with VHDL

Chapter 5, Concurrent Code (without 5.5)

Chapter 4.1, Operators

• Sundar Rajan, Essential VHDL: RTL Synthesis

Done Right

Chapter 3, Gates, Decoders and Encoders (see errata at http://www.vahana.com/bugs.htm)


Register Transfer Level (RTL) Design Description

Combinational Logic

Combinational Logic

Registers

…

Today’s Topic


Describing

Combinational Logic

Using

Dataflow Design Style


VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Registers• State machines• Test benches

Sequential statements


Data-flow VHDL

• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)

Major instructions



MLU: Block Diagram

B

A

NEG_A

NEG_B

IN0

IN1

IN2

IN3 OUTPUT

SEL1

SEL0

MUX_4_1

L0L1

NEG_Y

Y

Y1

A1

B1

MUX_0

MUX_1

MUX_2

MUX_3


MLU: Entity Declaration

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY mlu IS PORT(

NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC

);END mlu;


MLU: Architecture Declarative Section

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;SIGNAL B1 : STD_LOGIC;SIGNAL Y1 : STD_LOGIC;SIGNAL MUX_0 : STD_LOGIC;SIGNAL MUX_1 : STD_LOGIC;SIGNAL MUX_2 : STD_LOGIC;SIGNAL MUX_3 : STD_LOGIC;SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);


MLU - Architecture BodyBEGIN

A1<= NOT A WHEN (NEG_A='1') ELSEA;

B1<= NOT B WHEN (NEG_B='1') ELSE B;

Y <= NOT Y1 WHEN (NEG_Y='1') ELSEY1;

MUX_0 <= A1 AND B1;MUX_1 <= A1 OR B1;MUX_2 <= A1 XOR B1;MUX_3 <= A1 XNOR B1;

L <= L1 & L0;

with (L) select Y1 <= MUX_0 WHEN "00",

MUX_1 WHEN "01", MUX_2 WHEN "10",

MUX_3 WHEN OTHERS;

END mlu_dataflow;


Data-flow VHDL


Major instructions



For Generate Statement

For - Generate

label: FOR identifier IN range GENERATE BEGIN

{Concurrent Statements} END GENERATE;


PARITY Example


PARITY: Block Diagram


PARITY: Entity Declaration

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY parity IS PORT(

parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC

);END parity;


PARITY: Block Diagram

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor_out(5) xor_out(6)


PARITY: Architecture

ARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: std_logic_vector (6 downto 1);

BEGIN

xor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);parity_out <= xor_out(6) XOR parity_in(7);

END parity_dataflow;


PARITY: Block Diagram (2)

xor_out(1)xor_out(2)

xor_out(3) xor_out(4)xor_out(5) xor_out(6)

xor_out(7)

xor_out(0)


PARITY: Architecture


SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);

BEGIN

xor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7);



PARITY: Architecture (2)


SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

xor_out(0) <= parity_in(0);

G2: FOR i IN 1 TO 7 GENERATExor_out(i) <= xor_out(i-1) XOR parity_in(i);

end generate G2;

parity_out <= xor_out(7);



Combinational Logic Synthesis

for

Beginners



Simple rules for beginners

For combinational logic,

use only concurrent statements


• concurrent signal assignment ()


For circuits composed of

- simple logic operations (logic gates)

- simple arithmetic operations (addition,

subtraction, multiplication)

- shifts/rotations by a constant

use



For circuits composed of

- multiplexers

- decoders, encoders

- tri-state buffers

use

• conditional concurrent signal assignment

(when-else)• selected concurrent signal assignment

(with-select-when)


Left vs. right side of the assignment

<=

<= when-else

with-select <=

Left side Right side

• Internal signals (defined

in a given architecture)• Ports of the mode

- out

- inout

- buffer

Expressions including:• Internal signals (defined

in a given architecture)• Ports of the mode

- in

- inout

- buffer


Arithmetic operations

Synthesizable arithmetic operations:

• Addition, +

• Subtraction, -

• Comparisons, >, >=, <, <=

• Multiplication, *

• Division by a power of 2, /2**6(equivalent to right shift)

• Shifts by a constant, SHL, SHR


Arithmetic operations

The result of synthesis of an arithmeticoperation is a - combinational circuit - without pipelining.

The exact internal architecture used (and thus delay and area of the circuit)may depend on the timing constraints specifiedduring synthesis (e.g., the requested maximumclock frequency).


Operations on Unsigned Numbers

For operations on unsigned numbers

USE ieee.std_logic_unsigned.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTOR

OR

USE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeUNSIGNED


Operations on Signed Numbers

For operations on signed numbers

USE ieee.std_logic_signed.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTOR

OR

USE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeSIGNED


Signed and Unsigned Types

Behave exactly like

STD_LOGIC_VECTOR

plus, they determine whether a given vector

should be treated as a signed or unsigned number.

Require

USE ieee.std_logic_arith.all;


Addition of Unsigned Numbers

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;

X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;

END Behavior ;


Addition of Unsigned Numbers

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;


X, Y : IN UNSIGNED(15 DOWNTO 0) ;S : OUT UNSIGNED(15 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : UNSIGNED(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;

END Behavior ;


Addition of Signed Numbers (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;


X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;


Addition of Signed Numbers (2)LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;


X, Y : IN SIGNED(15 DOWNTO 0) ;S : OUT SIGNED(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;


Multiplication of signed and unsigned numbers (1)LIBRARY ieee;USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all ;

entity multiply is port(

a : in STD_LOGIC_VECTOR(15 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(23 downto 0); cs : out STD_LOGIC_VECTOR(23 downto 0)

);end multiply;

architecture dataflow of multiply is

SIGNAL sa: SIGNED(15 downto 0);SIGNAL sb: SIGNED(7 downto 0);SIGNAL sres: SIGNED(23 downto 0);

SIGNAL ua: UNSIGNED(15 downto 0);SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL ures: UNSIGNED(23 downto 0);


Multiplication of signed and unsigned numbers (2)begin

-- signed multiplicationsa <= SIGNED(a);sb <= SIGNED(b);sres <= sa * sb;cs <= STD_LOGIC_VECTOR(sres);

-- unsigned multiplicationua <= UNSIGNED(a);

ub <= UNSIGNED(b); ures <= ua * ub;cu <= STD_LOGIC_VECTOR(ures);

end dataflow;


Integer Types

Operations on signals (variables)

of the integer types:

INTEGER, NATURAL,

and their sybtypes, such as

TYPE day_of_month IS RANGE 0 TO 31;

are synthesizable in the range

-(231-1) .. 231 -1 for INTEGERs and their subtypes

0 .. 231 -1 for NATURALs and their subtypes


Integer Types

Operations on signals (variables)

of the integer types:

INTEGER, NATURAL,

are less flexible and more difficult to control

than operations on signals (variables) of the type

STD_LOGIC_VECTOR

UNSIGNED

SIGNED, and thus

are recommened to be avoided by beginners.


Addition of Signed Integers

ENTITY adder16 ISPORT ( X, Y : IN INTEGER RANGE -32767 TO 32767 ;

S : OUT INTEGER RANGE -32767 TO 32767 ) ;END adder16 ;

ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;


Testbenches


Generating selected values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

BEGIN

.......testing: PROCESS

BEGIN

test_vector <= "000";

WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;

END PROCESS;

........

END behavioral;


Generating all values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";

BEGIN

.......

testing: PROCESS

BEGIN

WAIT FOR 10 ns;

test_vector <= test_vector + 1;

end process TESTING;

........

END behavioral;


SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);

SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

.......

double_loop: PROCESSBEGIN

test_ab <="00";test_sel <="00";for I in 0 to 3 loop for J in 0 to 3 loop

wait for 10 ns; test_ab <= test_ab + 1;

end loop; test_sel <= test_sel + 1;end loop;

END PROCESS;

........

END behavioral;

Generating all possible values of two inputs


Generating periodical signals, such as clocks

CONSTANT clk1_period : TIME := 20 ns;

CONSTANT clk2_period : TIME := 200 ns;

SIGNAL clk1 : STD_LOGIC;

SIGNAL clk2 : STD_LOGIC := ‘0’;

BEGIN

.......

clk1_generator: PROCESS

clk1 <= ‘0’;

WAIT FOR clk1_period/2;

clk1 <= ‘1’;

WAIT FOR clk1_period/2;

END PROCESS;

clk2 <= not clk2 after clk2_period/2;

.......

END behavioral;


Generating one-time signals, such as resets

CONSTANT reset1_width : TIME := 100 ns;

CONSTANT reset2_width : TIME := 150 ns;

SIGNAL reset1 : STD_LOGIC;

SIGNAL reset2 : STD_LOGIC := ‘1’;

BEGIN

.......

reset1_generator: PROCESS

reset1 <= ‘1’;

WAIT FOR reset_width;

reset1 <= ‘0’;

WAIT;

END PROCESS;

reset2_generator: PROCESS

WAIT FOR reset_width;

reset2 <= ‘0’;

WAIT;

END PROCESS;

.......

END behavioral;


Typical error

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

SIGNAL reset : STD_LOGIC;

BEGIN

.......

generator1: PROCESS

reset <= ‘1’;

WAIT FOR 100 ns

reset <= ‘0’;

test_vector <="000";

WAIT;

END PROCESS;

generator2: PROCESS

WAIT FOR 200 ns


WAIT FOR 600 ns


END PROCESS;

.......

END behavioral;


Wait for vs. Wait

Wait for: waveform will keep repeating itself forever

Wait : waveform will keep its state after the last wait instruction.

0 1 2 3

…

0 1 2 3 …


Asserts & Reports


Assert

Assert is a non-synthesizable statement

whose purpose is to write out messages

on the screen when problems are found

during simulation.

Depending on the severity of the problem,

The simulator is instructed to continue

simulation or halt.


Assert - syntax

ASSERT condition

[REPORT "message"

[SEVERITY severity_level ];

The message is written when the condition

is FALSE.

Severity_level can be:

Note, Warning, Error (default), or Failure.


Assert - Examples

assert initial_value <= max_value

report "initial value too large"

severity error;

assert packet_length /= 0

report "empty network packet received"

severity warning;

assert false

report "Initialization complete"

severity „note”;


Report - syntax

REPORT "message"

[SEVERITY severity_level ];

The message is always written.

Severity_level can be:

Note (default), Warning, Error, or Failure.


Report - Examples

report "Initialization complete";

report "Current time = " & time'image(now);

report "Incorrect branch" severity error;


Generating reports in the message window

reports: process(clk_trigger) begin

if (clk_trigger = '0' and clk_trigger'EVENT) then

case segments is

when seg_0 => report time'image(now) & ": 0 is displayed" ;










end case;

end if;

end process;


Anatomy of a Process

[label:] process [(sensitivity list)] [declaration part]begin statement partend process;


Sequential Statements (1)

• If statement

• else and elsif are optional

if boolean expression then statementselsif boolean expression then statements

else boolean expression then statementsend if;



• Loop Statement

• Repeats a section of VHDL code

for i in range loop statementsend loop;



• Case statement

• Choices have to cover all possible values of the condition• Use others to specify

all remaining cases

case condition is when choice_1 => statements when choice_2 => statements

when others => statementsend case;

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