Egyidejű VHDL Signal assignment Concurrency Delta time When statement With...
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Egyidej VHDLSignal assignmentConcurrencyDelta timeWhen statementWith statementBehaviour and dataflowDataflow model of multiplexorGenericsThe assert command - error management in VHDLTypes, subtypes
Comparison of concurrent and sequential statementsSequential statements are handled according to the order in which they appear in the models code
On the other hand, concurrent statements are the ones to execute or at least simulate to execute in parallel
- Signal assignmentVariables: sequential objectsSignals: concurrent objectsIn hardware: it usually feels natural to work concurrently using signal assignment statementsSyntax:
- Simple exampleEntity NOR_gate is port (a,b: in std_logic; c: out std_logic); end; Architecture rtl of NOR_gate is begin c
- Example with component delay Architecture rtl of NOR_gate is begin c
- Usage of the after for synthesisIn the previous example a waveform can be obtained for signal c depending on the value of signal bThis description method is not supported by the synthesis toolsOther rule, that the delay after the after command must be in ascending orderIncorrect code:c
- ConcurrencyHardware is parallel by nature, and so is VHDL.This means that all concurrent language constructions in VHDL code can be executed concurrently, making the order in which the code is written irrelevantExample2: Architecture rtl1 of sign_ass is begin b
- Example of two buffersAs the hardware shows, signal a does not change before signal b changes value.Similarly, signal b does not change value before signal c changes value.It is the same in the VHDL code, as it is event-controlled.This means that all the concurrent VHDL commands can be written in any order without the function of the design being changedE.g. the order of the concurrent signal assignment is irrelevant, since the concurrent VHDL commands are event-controlled. E.g.:a
- LabelAll concurrent statements can be identified with a label:Label_name: b
- Delta time IDelta time is used in VHDL for queuing up sequential events.The time between two sequential events is called a delta delay.A delta delay has no equivalent in real time but is executed while the simulation clock is standing still.In a signal assignment, the value is not assigned to the signal directly, but after a delta at the earliest:b
- Delta time IITo prevent VHDL simulators jamming, most simulators stop after 1000 delta times, e.g.The number can usually be set.The following example is correct VHDL, but generates a design which oscillates ad infinitum: q
- When statementSyntax:
- Examples for when statementExample: Entity ex is port (a,b,c: in std_logic; data: in std_logic-vector (1 downto 0); q: out std_logic); end; Architecture rtl of ex is begin q
Three-state buffer & the others statementThe when command is very useful, e.g. when designing a three-state buffer:dbus Z) assignment, the entire vector, regardless of the vector length, will be assigned the value Z.This manner of assigning the entire vector a value is very effective and makes the code easier to maintain.If the length of the vector is to be changed, only the declaration for the vectors has to be modified and not the code in the architecture.
- Detailed properties of the when statementIt is permissible to use several different signals in the expression, making the command very flexible and useful for design.Example: q
- Upper-case and lower-case lettersVHDL syntax does not differentiate between upper-case and lower-case letters.The only exception is inside single quotation marks ( ) or double quotation marks ( ), e.g. when the value Z is assigned to a signal of type std_logic or mvl, the Z must be upper-case:sig
- With statementSyntax: with select
- Behavioural and dataflowTwo design approaches can be used when writing VHDL code:behavioural anddataflow design.An example of the dataflow is:Architecture dtf of ex is begin q
- Dataflow model of a multiplexorThese two dataflow models of a multiplexor are equivalent.The first architecture uses a when statement and the second a with statement.Both models can also be synthesized, ignoring the 10 ns delay.Entity mux is port (sel0,a,b: in std_logic; c: out std_logic);end;Architecture dtf1 of mux is begin c
- GenericsGenerics can be used to introduce information into a model, e.g. timing information.The generic must be declared in the entity before the port command.A generic can have any data typeThere are some restrictions with regard to what synthesis tools will accept.Example:Entity gen_ex is generic (delay: time:=10 ns); port (a,b: in std_logic; c: out std_logic); end;Architecture dtf of gen_ex is begin c
Assert commandSyntax:assert signal_reset = '1' ; It is checked whether signal_reset is not equal to 1 .assert -- e.g.: variable_reset = '1' report -- e.g.: "Reset is active !" severity ; If variable_reset is not equal to 1 the report ``Reset is active`` is given.Assert is an interesting language construction which makes it possible to test function and time constraints on a model inside a VHDL component.If the condition for an assert is not met during simulation of a VHDL design, a message of a certain severity is sent to the user (the simulator).Using assert it is possible to test prohibited signal combinations or whether a time constraint is not being met, type set-up, or whether there are unconnected inputs to the component.If the condition is not met, the assert message is sent to the user plus the name of the (unit) process which was cancelled.
Report statementreport_statement ::= [ label : ] report expression [ severity expression ] ;Examples:report "End of simulation!" severity failure ; This assertion stops (severity_level = failure) the simulation at the time evaluated.report "Entering process clkdiv" ; This entering of process clkdiv will be reported.There are four different severity levels for the message (error levels):NoteWarningErrorFailure
Error managementThe message and error level are reported to the simulator and are usually displayed in plain text in the VHDL simulators command window.It is normally possible to set the error level at which the VHDL simulator should abort the simulation.The default for most simulators is severity level Error.Assert can be used to verify external signals to the component or the internal behaviour, both time and function verification.As assert is both a sequential and a concurrent command, it can be used virtually anywhere in the code.The error management code is only present during the simulation.Example: assert in_0 /= X and in_1 /= X report "in is not connected" severity error; The error management code checks that in_0 and in_1 are connected, or that they have an undefined value.
Variable nowVariable now is defined in the VHDL standard.It contains the simulators internal absolute time.With the assert command it is possible to check that the simulator time does not exceed, say 1000 ns:process (clk) begin assert now < 1000 ns report "Stopping simulator (max. simulation time 1000 ns)" severity failure; end process;The statement assert in this example is a sequential assertion statement.
Concurrent assertionIf the assert is used in the concurrent part of the VHDL code, the statement will only be executed if an event on its sensitivity list takes place.If the assert only checks the time with variable now, no event will occur and the assert will never be executed.So, assert must be placed in a process which is executed at each clock edge.Where the assert is used in the concurrent part, it can be used in the next entity:Entity ex is port (a,b: in std_logic; q: out std_logic); begin assert a/=1 or b/=1 report "a=1 and b=1 at the same time" severity warning; end; Architecture ...Building a test bench, assert is good for verifying the response from the circuit.
Sequential reportin VHDL-87 and in VHDL-93If the report is used in the sequential part of VHDL code the assert can be left out in VHDL-93 standardExample:Example in VHDL-87: process (a,b)begin if a=1 and b=1 then assert false report a=1 and b=1; end if;...end process;Example in VHDL-93: process (a,b)begin if a=1 and b=1 then report a=1 and b=1; end if;...end process;
Std_logic and Std_ulogicThe VHDL is a strongly typed language:It is not permissible to join two signals (e.g. in hierarchical design) if they do not have the same data type.Solution: IEEE-defined data types are introduced:std_logicstd_ulogic (difference between them is discussed later)
Std_ulogic typeDeclared in the ieee package std_logic_1164Assume the following values:U -- UninitializedX -- Forcing Unknown0 -- Forcing 01 -- Forcing 1Z -- High ImpedanceW -- Weak UnknownL -- Weak 0H -- Weak 1- -- Dont care
Std_logic typeDeclared in the ieee package std_logic_1164Std_ulogic can assume the same values as std_logicThe difference is that std_logic is defined as:subtype std_logic is resolved std_ulogic;
Example: DBUS driver
- DBUS driver with std_logicEntity ex is port (d,c,en1,en2: in std_logic; dbus: out std_logic);end;Architecture rtl of ex isbegin dbus
- DBUS driver with std_ulogicE R R O R !Entity ex is port (d,c,en1,en2: in std_ulogic; dbus: out std_ulogic);end;Architecture rtl of ex isbegin dbus
ComparisonStd_logic is preferred, since easiest to use the same data type throughout the designThe disadvantage, that no error occurs if you have two drivers for the same signal in the VHDL code by mistake
Composite types - ArrayA named array is a collection of elements that are o