CONTACT TECHNOLOGYportal.unimap.edu.my/portal/page/portal30/Lecture... · Rco –contact resistance...

CONTACT TECHNOLOGY

Semester II,

2018/2019

•Able to identify ALL back-end process modules from wafer cross

section.

•Understand the important of ohmic contact and able to describe

step by step ohmic contact formation.

•Understand the importance of contact resistance monitoring,

extraction method and test structure.

• Understand the application of diffusion barrier layer

• Able to describe silicide and salicide processes.

LECTURE OBJECTIVES

2

Standard CMOS Process Flow

3

Main Process Modules (CMOS 1P2M 3.3V)

Device Isolation (LOCOS)

Vt Adjust

Polygate Definition

Source & Drain Formation

Pre Metal Dielectrics Deposition (PMD)

Contact DefinitionMetal-1 Deposition & Patterning

Inter-Metal Dielectrics Deposition (IMD)

Via Definition

Metal-2 Deposition & Patterning

Passivation

1.Wells Formation

2.Active Area Definition

3.

4.

5.

6.

7.8.

9.

10.

11.

12.

13.

14. Pad Definition

Full integration may require 300-500 process steps

FRONT END PROCESS

(creating an electrically

isolated devices)

BACK END PROCESS

(connecting the devices to

form the desired

circuit function.)

The need for contact

4

•When ICs are fabricated, isolated active-device regions are

created within the single-crystal substrate

•The technology used to connect these isolated devicesthrough

specific electrical paths employs high conductivity, thin film

conductor materials fabricated above the SiO2 insulator that

covers the silicon surface

•Wherever a connection is needed between a conductor filmand

the silicon substrate, an opening in the SiO2 must be provided to

allow such contact to occur

•In MOSFET, current enters the contact perpendicular to thewafer

surface, then travels parallel to the surface to reach channel.

•The parasitic series resistance, RS of the current path from the

contact to the edge of the channel can be modeledas:

Rs = Rco + Rsh + Rsp + Rac

Where:

▪Rco – contact resistance between the metal and the S/D region

▪Rsh – sheet resistance of S/D regions

▪Rsp – resistance due to current crowding effect near thechannel

end of the source▪Rac – accumulation layer resistance


5

GATE

Xj

Rac

RspRsh

Rco

METAL


6

- Rco – contact resistance between the metal and the S/Dregion

- Rsh – sheet resistance of S/D regions

- Rsp – resistance due to current crowding effect near thechannel end of

the source

- Rac – accumulation layer resistance

▪ Ideal non-rectifying contacts would exhibit no resistance to the

flow of current in bothdirections.

▪ In general, metal-semiconductor contacts tend to exhibit non-

ohmic I-V (due to the work-function different of metal and

semiconductor, potential energy barrier exist between metal-

semiconductorat thermal equilibrium). For e.g. Metal-n type S/C

potential barrier is 0.5V.

Theory of Metal-Semicon

contact

7

V

I

VV

I I

Ideal ohmic contact


contact

8

Rectifying contact Low-resistance ohmic

contact

Ev

Ec EF

EF

qΦm

metal n-type s/conductor

qΦs

Ec

e

e e

e

Energy band diagram of metal-semiconductor contact

potential barrier

vacuum level

EF


contact

9

Rectifying contact

▪However, it is still possible to fabricate metal - s/c contacts with I-V

characteristics that approach those of ideal case. This actual contact

is referred as low- resistance ohmic contact.

▪Surface concentration in silicon is high, ND > 1019 cm-3

▪Contact sintering (furnace anneal ~450ºC after metal deposition)


contact

10

Specific Contact Resistivity, ρc

▪Physical parameter that characterise the interface resistivity of

metal – semiconductor contact.

▪The ρc describes the incremental resistance of an infinitely

small area of interface, ie, the interface quality

▪ Unit-cm2

Specific Contact Resistivity

11

SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION

GATE

A – area of contact interface

Assume the current density over the entire area A isuniform;

ρc = Rk / A, where Rk is V/I

V


12

SPECIFIC CONTACT RESISTIVITY, ρc EXTRACTION

Three most commonly used structures

• Cross-bridge Kelvin Resistor – CBKR

• Contact-end resistor – CER

• Transmission line tap resistor - TLTR

In all of these structures,

▪a specific current is sourced from the diffusion level up to metal

level through the contact window.

▪a voltage is measured between the two levels using two other

terminals.


13

metal

diffusion

LL

I

43

2

CROSS-BRIDGE KELVIN RESISTOR

1

ℓ δ


14

PROCEDURE FOR EXTRACTING ρc FROM CBKR

1. 2 sets of CBKR test structures of varying contact sizes, ℓ varying in

length between 1 to 25 um, with at least 2 different δ for each set

of test structures.

2. The diffused region under the contacts for CBKR should be

fabricated to closely emulate the actual junctions to be built in

the actual devices. Normally both contacts on p+ and n+need

to be built. The sheet resistance(ρsh) of diffused layers is to be

measured.

3. After test structures have been fabricated, the value ofKelvin

contact resistance, Rk = V/I, of each contact is measured.


15

δ

ℓPROCEDURE FOR EXTRACTING ρc FROM CBKR


16

4. The value of log10 (Rk/ ρsh) is calculated for each

contact.

5. The value of log10 (ℓ/δ ) is calculated for each contact.

6. The values of log10 (Rk/ ρsh) versus log10 (ℓ/δ ) are plotted

for every set of different δ

7. Two value of y = ℓt / δ could be extracted from the curves

where ℓt is the transfer length and defined as ℓt = √ ρc/ρsh (ℓt is effective length of current crowding effect)

8. Since the δ values are known, ℓt can be found from ℓt = yδ

9. Since ℓt = √ ρc/ρsh , ρc is found from ρc = ℓt2ρsh

SPECIFIC CONTACT RESISTIVITIES OF VARIOUS METAL-SI CONTACTS

METAL-SI ρc (Ω-cm2)

AlSi to n+ Si 15

AlSi-TiN to n+ Si 1.0

AlSi-TiN to p+ Si 20

CVD W to n+ Si 11

Al-Ti:W – TiSi2 to p+ Si 60-80

Al-Ti:W – TiSi2 to n+ Si 13-25


17

Contact chain for RCO monitoring

▪Generally, accurate value of Rco cannot be

extracted from resistance data obtained from simple

contact chain structure.

▪However, these kinds of contact chains are useful to

provide rapid monitoring of the contact-fabrication

process.


18

contact metal diffused region

PMD

PAD 1 PAD 2

P-substrate


19

n+ n+n+

R12 = V12 / I12

Rco = R12 / number of contact

Conventional Contact• BASIC PROCESS SEQUENCE OF CONVENTIONAL

OHMIC- CONTACT

▪ Creation of heavily doped regions (n+ or p+)

▪ A window is etched in the oxide (contact hole etched in PMD)

▪ Contact pre-clean (remove particles, contaminants and native

oxide)

▪ Metal deposition

▪ Sintering or annealing process

20

FORMATION OF HEAVILY DOPED REGIONS

▪Dopants selectively introduced through ion implantation ordiffusion

process

▪Masking layer is used to restrict the introduction of dopants intothe

desired regions

▪Heavy doping is needed, however the maximum doping

concentration is limited by the solid solubility ofmaterial.

▪ Clustering effect may reduce the electrically activedopants

ND > 1019

Conventional Contact

21

FORMATION OF CONTACT OPENING

▪Key step in the fabrication of contact structure

▪The minimum size of contact holes usually determined by the

minimum resolution capability of patterning technology. Contact

size normally the same as gate length for e.g 0.5um CMOS

technology, gate length = 0.5um, contact size = 0.5um (refer to the

design rules).

▪In older technology (>2.0um process), wet etching is used for

contact etch. Wetting and by product is introduced into theoxide

etchant plus the application of ultrasonic agitation.


22

FORMATION OF CONTACT OPENING

▪Due to the isotropic nature of wet etching, it is ineffective forthe

etching of smaller contact holes.

▪ Dry etching of contact etch is developed.

ND > 1019 ND > 1019 ND > 1019


23

▪ Dry etch introduced a new set of problems;

▪polymer contamination – by product of dry etching.

▪damage of silicon surface (high energy radicals in plasma), this

plasma also could damaged gate oxide (plasma damaged,

antenna structure is used to monitor this effect to oxidereliability)

▪ selectivity problem

▪ Several approaches used;▪ additional step to remove polymer

▪ combined isotropic and anisotropic dry etch

▪ combination of dry and wet etch

ND > 1019


24

Evolution of contact processes

25

Widely tapered

contact hole.

PVD metal fill

Narrow contact

hole, void with

PVD metal fill

Narrow contact

hole, WCVD for

tungsten plug

AlSiCu AlSiCu AlCu

W SiO2SiO2SiO2

Void

Si Si Si

▪ To give a shape that will result in good step coverage ofmetal.

▪ Several approaches used;

▪ reflow, high temperature furnace annealing after contactetch

▪ wet etching followed by dry etch process

▪ PR contouring followed by dry etch

▪ many others

Sloped opening

Issues: Sidewall contouring

26

Issues: Removal of native

oxide▪ Native oxide could result in high Rco

▪ 2 – 5 Å oxide posed not problem since it

can be consumed by metals during

sintering/annealing

▪ Metal must be immediately deposited

after native oxide removal

▪ Methods of removing native oxide

▪ H2O:HF (100:1) dip for 1 minute,

followed by rinsing and drying

▪ Sputter etch contact in sputtering

system prior to metallisation

▪ in-situ dry-etch (no commercial

product available)

27

10 1000100

50

Time (min)

Thic

kn

ess

(Å)

Native oxide growth rate on Si exposed to room air

100

▪Major issue is metal step coverage in thecontact

holes

▪ Metal deposition technique is important:

▪CVD is more capable to produce good step

coverage (W plug, blanket or selective deposition)

▪The drawback is process complexity and increase

cost per process step

▪Preferred deposition technique for highaspect

ratio contact, > A.R of 3

▪ PVD at elevated temperature (300-350 C)

▪ Hot aluminum PVD process (400-500 C)

Issues: Metal D&P

28

▪Performed to allow any interface layer that exists

between the metal and silicon to be consumed bya

chemical reaction.

▪to allow metal and silicon to come into intimate

contact through inter-diffusion.

▪ Methods:

▪400-500C for 30 minutes in the presence of H2 or

forming gas (a mixture of H2 (10%) and N2 (90%)

▪ RTP, laser annealing and several others.

Issues: Sintering for contacts

29

▪Aluminum is chosen as metal interconnect because

of:

▪Al-Si ohmic contact could be fabricated with low

Rco to n+ and p+

▪ low resistivity (2.7 Ohm-cm)

▪excellent compatibility with SiO2 (good

adhesion).

▪the drawback is low melting point (660C) and

low eutectic temperature of Al/Si mixtures (577 C)

Issues: Aluminium junction

spiking

30

▪Grain boundaries of polycrystalline aluminumprovide

fast diffusion path for Si at temperature > 400 C .

▪As a result, large quantity of Si from Al-Si interface can

diffuse into the Al film

▪Simultaneously Al from film will move rapidly to fill the

voids created by the departing Si.

▪If the penetration of Al is deeper than the p-n junction

depth below the contact, the junction will exhibit large

leakage current / electrically shorted.

▪ This effect is referred as junctionspiking.


spiking

31

Si Si Si

Beginning of heat treatment

During heat treatment


spiking

32

Method to reduce junction spiking

▪Silicon is added to the Al film during deposition.

▪sputter depositing the film from a single target containingboth

Al and Si.

▪ co-evaporation of Si and Al

▪Silicon diffusion into Al will not occur if added Si concentration

exceeds the Si solubility at process temperature (normally 1 to 2

wt % Si is added).

However, this solution is only suitable for technology of 3um and

above due to Si precipitation, thus increasing the Rco. The

introduction of Diffusion Barrier between Al and Si (typical solution to

junction spiking in the sub-micron CMOSprocess)


spiking

33

▪The role of this material is to prevent the inter- diffusion of Al and

Si.

▪A diffusion barrier used is a thin film inserted between an overlying

metal and underlying semiconductor material.

▪ Such diffusion barriers should have the followingcharacteristics;

▪ diffusion of Al and Si through it should be low

▪ barrier materials should be stable in the presence of Al andSi

▪ barrier materials should adhere well to both Al and Si

▪ barrier materials should have low contact resistivity to Al and Si

▪ barrier materials should have good electrical conductivity

Diffusion barriers

34

▪3 types of barriers

▪passive barriers (chemically

inert with respect to Al and Si.

▪sacrificial barriers (react

with Al and Si)

▪stuffed barriers (its grain

boundaries is filled with other

materials to block inter

diffusion of Al and Si.Diffusion barrier

Diffusion barriers

35

Diffusion barrier material

▪Titanium – tungsten (Ti:W) – Stuffed Barrier

▪Normally sputter-deposired from a single

target.

▪ Initially used in Bipolar technology.

▪Major draw-back for VLSI application is

the film is quite brittle and of highstress.

▪ Polysilicon – Sacrificial Barrier

▪Easily integrated into NMOS technology

but not as compatible with CMOS

Diffusion barriers

36

Diffusion barrier material

▪ Titanium – Sacrificial Barrier

▪Good diffusion barrier to Si, has a relatively shortbarrier

capability lifetime.

▪ Titanium Nitride – Passive Barrier

▪The most compatible and successful diffusion barrier in

CMOS process.

▪ impermeable barrier to Si

▪ high activation energy for the diffusion of othermaterials.

▪ chemically and thermodynamically very stable.

▪ the lowest electrical resistivity among transitorymetals.

Diffusion barriers

37

THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS TRANSISTOR PERFORMANCE

▪Series resistance Rs is a combinationof;

▪Rs = Rco + Rsh + Rsp + Rac

GATE

Xj

Rac

PMD

ℓ

METAL

Contact length

Series resistance

Rco RspRsh 38

THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS

TRANSISTOR PERFORMANCE

▪When larger design rules were used, Rs was a minorcomponent

of the total MOS resistance.

▪ As devices got smaller, Rs grew larger due to;

▪shrinking contact size (Rco is dependence on contact size)

▪shallower source / drain regions (Rsh is dependence on

source / drain depth and width)

▪under such conditions, Rs would degrade the device

performance such as;

▪ Idsat, transconductance, Vt

Series resistance

39

THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS

TRANSISTOR PERFORMANCE

Rch = [Leff + VDS] / [ 0 Cox (VGS – VT – 0.5VDS]

▪Generally accepted that Rs to be kept < 10% of Rch.

▪A comprehensive analysis on the Rs components is needed to

find the major contributor to the Rs and ways to reduce it.

Series resistance

40

▪Rsh contribution is negligible

▪The value of (Rac + Rsp) is likely to dominate the value of Rs for

MOS devices with the channel length of < 0.5um. Minimum value

of (Rac + Rsp) are achieved by fabricating source/drain

junction with as steep a doping profile as possible.

▪Rco can also important in degrading MOS device

performance. Rco is essentially determined by;

▪value of specific contact resistivity, ρc▪contact length, ℓ. It was shown that ℓ will need to be 1 to 4

times the channel length, L, to produce with minimum value

of Rco.

Series resistance

41

GATE

ℓ Contact length

L

Series resistance

42

The requirement on minimum ℓ meaning the new way of performing

contact structure is needed for deep sub-micron process

technology.

It is not possible to increase the contact

size, ℓ, because it will defeat thepurpose

of device shrinkage.

Enlarge active area (to accommodatelarger ℓ) will also resulted in increased

parasitic junction capacitance, which

further degrade the device

performance2λ x 2λ

W=4λ

DRAIN

5λ

2λ

Z=2λ

n+ diffusion

λ

2λ

Series resistance

L=2λ 43

•self-aligned silicides (SALICIDE)

•buried-oxide MOS (BOMOS) contact

•elevated source / drain

•selective metal deposition

Alternative contact structures

44

Materials for Silicide Process

▪Group – VIII metal silicides

Silicides process

45

▪ PtSi

▪ CoSi2▪ NiSi2

▪ TiSi2

(28-30 ohm-cm)

(16-18 ohm-cm)

(50 Ohm-cm)

(13-20 ohm-cm)

▪TiSi2 and CoSi2 are the most developed silicide process mainly

because of:

▪ lowest resistivity among the group members

▪ stable at temperature ~ 850 C

1. Contact etch

2. Resist strip

Purpose : To reduce contact resistance, Rco between metal

and silicon interface

3. Titanium deposition by

sputtering technique

~ 400Å

GATE

GATE

n+

n+

Silicides process

46

GATE

n+

4. TiN (barrier) deposition by


~ 1000 Å

5. TiSi2 (titanium silicide)

formation by RTP annealing,

700C @ 30sGATE

n+ TiSi2

Silicides process

47

6. W Plug deposition ~ 6000 Å

(by CVD) and etch back.GATE

n+ TiSi2

7. AlSiCu deposition by

sputtering ~ 3000 Å

8. TiN deposition by sputtering

~ 1400 ÅGATE

n+ TiSi2

Silicides process

48

9. Metal-1 pattern and etch

GATE

n+TiSi2

Silicides process

49

1. After S/D implant

2. Resist stripGATE

n+

GATE

n+

3. Titanium deposition by


Salicides process

50

GATE

n+

4. TiSi2 (titanium silicide)

formation by RTP annealing,

700C @ 30s

GATE

n+

5. Unreacted metal is

selectively etched by

etchant that does not attack

the silicide, SiO2 and Si

substrate

TiSi2

TiSi2

Salicides process

51

GATE

n+

6. PMD Deposition and reflow

GATE

n+

7. Contact pattern and etch

Salicides process

52

Then to be deposited with TiN

(barrier), W plug, AlSiCu and

TiN

Advantages of SALICIDE over conventional

contact

▪The value of Rsh becomes negligible, ρsh silicide =

1-2 Ohm/sq versus diffused junction = 40-120 ohm/sq

▪ Rs = Rco + Rsh + Rsp + Rac

▪ Contact area of silicide and the Si is much larger,

thus, lower Rco for the same ρc

Salicides process

53

CONTACT TECHNOLOGYportal.unimap.edu.my/portal/page/portal30/Lecture... · Rco –contact resistance...

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