© 2002 L. MacEachern

Wiring Parasitics

Contact Resistance Measurement and Rules

© 2002 L. MacEachern

Contact Resistance•Connections between metal layers and non-metal layers are called contacts.

•Connections between metal layers are called vias.

•For non-critical design, a simple lumped resistance based on process measurements is substituted. •• Parasitic Resistance Extraction (PRE) programs typically Parasitic Resistance Extraction (PRE) programs typically

model contact resistance as a small network.model contact resistance as a small network.

© 2002 L. MacEachern

Resistance Magnitude•Contact resistance is a function of layout geometry, the layers contacted, and the particular manufacturing process.

•Contact resistance is generally considered “very low”, although it may range from 10’s of mΩ to 10’s of Ω.

Component Resistance Typical Use

metal very low power and signal lines

metal2 very low power lines

polysilicon low signal lines andtransistor gates

n-typediffusion

medium signal lines and sourcesand drains of transistors

p-typediffusion

medium signal lines and sourcesand drains of transistors

contact very low signal connection(routing)

via very low signal connectionbetween metal layers(routing)

© 2002 L. MacEachern

CMOS Joining Rules

•Typical two-metal-layer process.

n-typediffusion

p-typediffusion poly metal metal2

n-typediffusion ü û T C ûp-typediffusion û ü T C ûpoly T T ü C ûmetal C C C ü Vmetal2 û û û V ü

Symbol Meaning

ü allowed

û not allowed

T Transistorformed

C contactrequired

V via required

© 2002 L. MacEachern

Effects of Contact Resistance

••Contact resistance is Contact resistance is an unwanted feature an unwanted feature which must be which must be accounted for in both accounted for in both high speed analog high speed analog and digital designs.and digital designs.

••As feature size As feature size decreases, the decreases, the significance of significance of contact resistance contact resistance contributions to contributions to circuit behaviour circuit behaviour increases.increases.

•• Propagation delay time can be Propagation delay time can be dominated by contact resistance dominated by contact resistance for 0.1for 0.1µµm CMOS with m CMOS with ρρcc>2>2..1010--77

ΩΩcmcm22

© 2002 L. MacEachern

Measuring Contact Resistance•Process Evaluation Devices (PEDs) are typically placed on each wafer.

•Process dependent parameters are monitored using these sacrificial dice. It is important to maximize the usage of these dice.

PED

© 2002 L. MacEachern

“Meander” Contact Chain

metalmetalnn--diff, pdiff, p--diff, polydiff, poly

contactcontact

•Typical layout for measuring contact resistance.

•The metal resistance and the secondary layer (e.g. n-diff) resistance is also included in the measurement.

•There is an inherent spatial orientation bias.

© 2002 L. MacEachern

The Hilbert Curve

The HilbertThe Hilbert--Peano Curve Peano Curve is conveniently described is conveniently described by an Lby an L--System using an System using an initial state of either “L” or initial state of either “L” or “R” and the paired “R” and the paired transformation rules, transformation rules,

L + R F - L F L - F R +R - L F + R F R + F L -

(When plotting the curve, (When plotting the curve, the characters “L” and “R” the characters “L” and “R” are ignored.)are ignored.)

© 2002 L. MacEachern

Hilbert Contact Chains

•The Hilbert-Peano Curve algorithm implemented in the layout package generates the contact chain.

•Hilbert-Peano curve properties reduce spatial orientation bias in the measurements.

© 2002 L. MacEachern

Layout Rules for Contacts

© 2002 L. MacEachern

Basic DefinitionsWIDTH :

SPACE :

CLEARANCE :

EXTENSION :

OVERLAP :

© 2002 L. MacEachern

Reserved Mask Names …

NW --- Definition of N-Well

PW --- Definition of P-Well

OD --- Definition of thin oxide for device and interconnection

OD2 --- Definition of thick oxide for 5V device

PO --- Definition of Poly-1 Si for gate and capacitor bottom plate

PO2 --- Definition of Poly-2 Si for resistor and capacitor top plate

3VN --- Definition of NLDD implantation for 3V device

5VN --- Definition of NLDD implantation for 5V device

PP --- Definition of P+ implantation

NP --- Definition of N+ implantation

© 2002 L. MacEachern

… Reserved Mask Names

3VESD --- Definition of ESD implantation for 3V I/O

5VESD --- Definition of ESD implantation for 5V I/O

CO --- Definition of contact window from M1 to OD, PO or PO2

M1 --- Definition of 1st metal for interconnection

VIA1 --- Definition of via1 hole between M2 and M1

M2 --- Definition of 2nd metal for interconnection

VIA2 --- Definition of via2 hole between M3 and M2

M3 --- Definition of 3rd metal for interconnection

VIA3 --- Definition of via1 hole between M4 and M3

M4 --- Definition of 4th metal for interconnection

CB --- Definition of bonding pad

© 2002 L. MacEachern

Contact Rules Contact Rule (156)Rule No. Description Layout Rule

Layer : CO --- Contact Window

CO.W.1 Minimum and maximum width of a CO region A 0.4 um

CO.S.1 Minimum space between two CO regions B 0.4 um

CO.C.1 Minimum clearance from a CO on OD regionto a PO gate

C 0.3 um

CO.C.2 Minimum clearance from a CO on PO regionto an OD region

D 0.4 um

CO.E.1 Minimum extension of an OD region beyonda CO region

E 0.15 um

CO.E.2 Minimum extension of a PO region beyond aCO region

F 0.2 um

CO.E.3 Minimum extension of a PP region beyond aCO region

G 0.25 um

CO.E.4 Minimum extension of an NP region beyond aCO region,

H 0.25 um

CO.R.1 Poly contact on OD area is forbidden

CO.R.2 Butted Contact is not allowed. I

* Please use fully contacted layout for device source and drain.

© 2002 L. MacEachern

Contact Rules: Reference Layout

C

E

B

A

E

G

N+

COCO

OD

PP

PO

D

F

PO

PP

N+E

NPH

© 2002 L. MacEachern

I/O Pad Structure

M1 & M2 shorted, capacitivelyM1 & M2 shorted, capacitivelycoupled to substrate through oxide. coupled to substrate through oxide. Substrate acts as a resistor to Substrate acts as a resistor to ground, fouling matching and adding ground, fouling matching and adding “resistor” noise.“resistor” noise.

M1 & M2 capacitively coupled. M1 M1 & M2 capacitively coupled. M1 shorted to ground. M1 shields M2 shorted to ground. M1 shields M2 from substrate. Capacitance can be from substrate. Capacitance can be tuned out by offtuned out by off--chip inductor. chip inductor.

Typical I/O PadTypical I/O Pad RF PadRF Pad

bondingwire

substrate

M2

M1

bondingwire

via

M2

M1

substrate