CMOS Analog Design Lect 3
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Transcript of CMOS Analog Design Lect 3
![Page 1: CMOS Analog Design Lect 3](https://reader031.fdocuments.net/reader031/viewer/2022013108/55ae085c1a28abab788b4744/html5/thumbnails/1.jpg)
EE 290C
CMOS Analog Design Using All-region MOSFET Modeling
Lecture 3: Charge control compact MOSFET
model
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CMOS Analog Design Using All-Region MOSFET Modeling 2
The Unified Charge Control Model (UCCM) 1
1 1I C
ox b i
dQ dVC C C
′ + =
′ ′ ′+
Approximations:
1) depletion capacitance per unit area is constant along the
channel and is calculated neglecting inversion charge
2) Charge sheet model /i I tC Q φ′ ′= −
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The Unified Charge Control Model
(UCCM) 2
CMOS Analog Design Using All-Region MOSFET Modeling 3
1 1I C
ox b i
dQ dVC C C
′ + =
′ ′ ′+
/i I tC Q φ′ ′= −
1 tI C
ox I
dQ dVnC Q
φ ′ − =
′ ′
( )1 bGB
ox
Cn n V
C
′= + =
′where
Integrating from an arbitrary channel potential VC to a
reference potential VP yields the unified charge control
model (UCCM)
lnIP I IP C t
ox t IP
Q Q QV V
nC Qφ
φ
′ ′ ′−− = +
′ ′ is the value of
for V=VP. IPQ′
IQ′
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The “Regional” Strong and Weak
Inversion Approximations
CMOS Analog Design Using All-Region MOSFET Modeling 4
lnIP I IP C t
ox t IP
Q Q QV V
nC Qφ
φ
′ ′ ′−− = +
′ ′
( )I ox P CQ nC V V′ ′− ≅ −
P C tV V φ− � P C tV V φ− −�
ln 1IP C t
IP
QV V
Qφ ′
− ≅ − ′
or, equivalently
P C t
t
V V
I IPQ Q e
φ
φ
− +
′ ′=
strong inversion weak inversion
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Example
CMOS Analog Design Using All-Region MOSFET Modeling
5
(a) Calculate the value of the inversion charge density,
normalized to , for which the value of the voltage
VP-VS calculated using the SI approximation differs from
that calculated using UCCM by 10 %; (b) Same using
the WI approximation ; (c) comment on ‘moderate’
inversion (MI)
(b) Answer: a)
SI approximation error of less than 10 % for q’I > 20
b) WI approximation
WI approximation error of less than 10 % for q’I < 0.22.
(c) MI region : SI and WI approximations give errors greater
than 10 % for the control voltage VP-VS. The inversion
charge density variation from the lower to the upper limit of
the MI region is approximately two orders of magnitude
(20/0.22).
ox tnC φ′−
( ) /I P C t
q V V φ′ ≅ −
P C t
t
V V
Iq e
φ
φ
− +
′ =
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The Pinch-off Voltage Charge Density
CMOS Analog Design Using All-Region MOSFET Modeling 6
The channel charge density corresponding to the
effective channel capacitance times the thermal
voltage, or thermal charge, defines pinch-off
( )IP ox b t ox t
Q C C nCφ φ′ ′ ′ ′= − + = −
The name pinch-off is retained herein for historical
reasons and means the channel potential
corresponding to a small (but well-defined)
amount of carriers in the channel.
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The Pinch-off Voltage VP
CMOS Analog Design Using All-Region MOSFET Modeling 7
The channel-to-substrate voltage (VC) for which the
channel charge density equals is called the pinch-off
voltage VP.
UCCM is asymptotically
correct in weak inversion if
in weak
inversion( ) ( )2 / 2 /
( 1)sa F C t sa F C tV V
I b t ox tQ C e C n eφ φ φ φ φ φ
φ φ− − − −′ ′ ′− = = −
2 1 ln1
P sa F t
nV
nφ φ φ
= − − + −
2P sa FV φ φ≅ −
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Threshold Voltage
Equilibrium threshold
voltage VT0, for VC=0,
gate voltage for which
Q’I = Q’IP = -nC’oxφt
or gate voltage for which
VP=0 2
P sa FV φ φ≅ −
G FB sa ox sa tV V Cφ γ φ φ′− = + −Recalling that
0 2 2 T FB F FV V φ γ φ≅ + +it follows that
8CMOS Analog Design Using All-Region MOSFET Modeling
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Example
CMOS Analog Design Using All-Region MOSFET Modeling
9
Estimate VT0 for an n-channel transistor with n+ polysilicon
gate, NA=1017 atoms/cm3 and tox=5 nm.
Answer:
(a) The flat-band voltage (Lec 2) is -0.98 V; φF=0.419;
C’ox= 690 nF/cm2.
For this low value of the threshold voltage, the off-current (for
VGS=0) is too high for digital circuits. Solution to control the
magnitude of the threshold voltage without an exaggerated
increase in the slope factor -> a non-uniform high-low channel
doping.
2 / 0.264 Vs A oxq N Cγ ε ′= =
0 0.98 0.838 0.264 0.838= 0.1VTV ≅ − + +
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CMOS Analog Design Using All-Region MOSFET Modeling n
VVV 0TGBP
−−−−≅≅≅≅
Pinch-off Voltage vs. Gate Voltage
Useful approximation:
-1.00E+00
0.00E+00
1.00E+00
2.00E+00
3.00E+00
4.00E+00
0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00
pinch-off voltage
0
0.5
1
1.5
2
slope factor
4.0
3.0
2.0
1.0
0
-1.0
0 1.0 2.0 3.0 4.0 5.0
2.0
1.5
1.0
0.5
0
VG (V)
VP
VT0 (equilibrium threshold voltage)
1sa oxP
G G b ox
d CdV
dV dV C C n
φ ′≅ = =
′ ′+
10
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MOS Transistor
0 0 0
i ix xW
D n nI J dxdz W J dx= − = −∫ ∫ ∫
11CMOS Analog Design Using All-Region MOSFET Modeling
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‘Exact’ I-V Model of the MOSFET 1
CMOS Analog Design Using All-Region MOSFET Modeling 12
n nn
d dnJ qn qD
dy dy
φµ
= − +
( )
0 0
C
C
q V
u ukTn n e n e
φ −−= =
C
t
dVdn n d
dy dy dy
φ
φ
= −
Using the Einstein
relationship
n n tD µ φ= C Cn n n n
dV dVd dJ qn qn qn
dy dy dy dy
φ φµ µ µ
= − + − = −
drift +diffusion current
S C DV V V≤ ≤
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‘Exact’ I-V Model of the MOSFET 2
CMOS Analog Design Using All-Region MOSFET Modeling 13
0 0 0
i ix xW
D n nI J dxdz W J dx= − = −∫ ∫ ∫
0
xiC C
D n In
dV dVI qW n dx QW
dy dyµ µ ′= = −∫
Cn n
dVJ qn
dyµ= −
0
xi
IQ q ndx′ = − ∫
D
S
Vn
D I CV
WI Q dV
L
µ′= − ∫
L is the channel length
Since the current is constant along the channel
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CMOS Analog Design Using All-Region MOSFET Modeling 14
IC s t
I
dQdV d
Qφ φ
′= −
′
( )I i C sdQ C dV dφ′ ′= −
CdVsdφ
GVI
i
t
QC
φ
′′ = −
IdQ′+ _
Charge-Sheet Formula for the Current
D drift diff
s In I n t
I I I
d dQWQ W
dy dy
φµ µ φ
= + =
′′− +
Cn n
dVJ qn
dyµ= −
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Charge Control Compact Model 1
sdφ
BdQ′
+_
GV
bC′ +
_
IdQ′
iC′
oxC′
CdV
( )I ox b s ox sdQ C C d nC dφ φ′ ′ ′ ′= + =
s ID n I n t
d dQI WQ W
dy dy
φµ µ φ
′′= − +
( )n ID I t ox
ox
W dQI Q nC
nC dy
µφ
′′ ′= − −
′
Integrating along the channel yields
( )2 2
2
n IS IDD t IS ID
ox
W Q QI Q Q
L nC
µφ
′ ′−′ ′= − −
′ 15CMOS Analog Design Using All-Region MOSFET Modeling
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MOSFET Modeling for Circuit Analysis and Design
16
Charge Control Compact Model - 2
( )2 2
2 2
n IS ID IS ID IS IDD t IS ID ox tn
ox ox
W Q Q Q Q Q QI Q Q W nC
L nC nC L
µφ φµ
′ ′ ′ ′ ′ ′− + − ′ ′ ′= − − = − ′ ′
drift + diffusion
0
2
IS ID s sLD ox tn
Q QI W nC
L
φ φφµ
′ ′+ − ′= −
average
charge average field
“virtual” charge
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Charge Control Compact Model 3
To emphasize the symmetry of the
rectangular geometry MOSFET
D F RI I I= −
2( )
( ) ( )2
IS D
F R t IS Dnox
QWI Q
L nCφµ
′′= −
′
(compare with Ebers-Moll model of the BJT)
17CMOS Analog Design Using All-Region MOSFET Modeling
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MOSFET Modeling for Circuit Analysis and Design 18
Drain Current vs. Gate-to-Bulk
Voltage
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MOSFET Modeling for Circuit Analysis and Design 19
Comparing UCCM and the Surface Potential
Model with Exact Numerical Solution of
Poisson Equation
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Modeling the Bulk Charge from
Accumulation to Inversion
CMOS Analog Design Using All-Region MOSFET Modeling
20
/sgn( ) ( 1)s t
B s ox s tQ C eφ φφ γ φ φ −′ ′= − + −
( )( ) ( )
/1
1 12sgn 1
sa t
sa t
b
oxsa sa t
eCn
C e
φ φ
φ φ
γ
φ φ φ
−
−
−′= + = +
′ + −
( ) ( )[ ]122−+=−− − tsaeVV tsasaFBG
φφφφγφ
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Modeling from Accumulation to Inversion: Surface Potential and Pinch-off Voltage (VP)
CMOS Analog Design Using All-Region MOSFET Modeling 21