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EE141

Memory

EE141- Fall 2003Lecture 27

EE141

Announcements

! Midterm2 returned today! Homework 10 due today! Remember: project presentations next Th

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Today’s Lecture

! Finish with impact of interconnects! Memory

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Midterm 2 Statistics (67 Students)

0

6

11

19

24

7

0

5

10

15

20

25

30

0 6 12 18 24 30 36Total Score (Out of 36)

Nu

mb

ero

fS

tud

ents

mean = 22.43median = 23.50std. dev = 6.61

min = 6.5max = 33

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Problem-3 was the Easiest

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5

10

15

20

25

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0 20 40 60 80 100

Relative Score (%)

Nu

mb

ero

fS

tud

ents

prob-1prob-2prob-3

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The Most Common Mistakes

! Problem-1 (Logical effort)» Cin not equal for all inputs» Logical effort calculation for dynamic gate

! Problem-2 (Pass-transistor logic)» Energy calculation» 4-way multiplexer implementation

! Problem-3 (Pipelined adder) issues» Calculating min Tclk» Correctly pipelining the design

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Common Project-2 Questions

! Account for delay in control logic orassume available control signals?

! Include set-up time for dividend anddivisor in overall divider delay?

! Average input-vector analysis or theworst-case input-vector analysis (theworst-case matters for min TClk)?

! Account for “ill-conditioned” cases wherereminder needs one more restoration?

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INTERCONNECT

Dealing with Inductance

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L di/dt

CL

V’DD

VDD

L i(t)

VoutVin

GND’

L

Impact of inductanceon supply voltages:• Change in current inducesthe change in voltage• Longer supply lines havelarger L

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L di/dt: Simulation

t

t

t

vout

iL

vL

20mA

40mA

5V

0.2V

0.0

1.0

2.0

3.0

4.0

5.0

Vou

t(V)

0

10

20

I L(m

A)

2 4 6 8 10t (nsec)

-0.3

-0.1

0.1

0.3

0.5

VL(V

)

tfall = 0.5 nsec

tfall = 4 nsec

Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.

The Results of an Actual Simulation are Shown on the Right Side.

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Choosing the Right Pin

ChipL

L´

Bonding wire

Mountingcavity

Leadframe

Pin

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Decoupling Capacitors

SUPPLY

Boardwiring

Bondingwire

Decouplingcapacitor

CHIPCd

�

�

Decoupling capacitors are added:• on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)

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De-coupling Capacitor Ratios

! EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x

! EV5» 13.9nF of switching capacitance» 160nF of de-coupling capacitance

! EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough!

Source: B. Herrick (Compaq)

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EV6 De-coupling CapacitanceDesign for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600

MHz» 0.32-µF of on-chip de-coupling capacitance was

added– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area

» 1-µF 2-cm2 Wirebond Attached Chip Capacitor(WACC) significantly increases “Near-Chip” de-coupling

– 160 Vdd/Vss bondwire pairs on the WACC minimizeinductance


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EV6 WACC

587 IPGA

MicroprocessorWACC

Heat Slug

389 Signal - 198 VDD/VSS Pins389 Signal Bondwires

395 VDD/VSS Bondwires

320 VDD/VSS Bondwires


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Design Techniques to address L di/dt

! Separate power pins for I/O pads and chip core! Multiple power and ground pins! Position of power and ground pins on package! Increase tr and tf! Advanced packaging technologies! Decoupling capacitances on chip and on board

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Memory

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Issues in Memory

" Memory Classification" Memory Architectures" The Memory Core" Periphery" Reliability" Case Studies

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Semiconductor MemoryClassification

Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO

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Memory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

DATA

WRITE

READ

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Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN�2

WordN�1

Storagecell

M bits M bits

N

w ord s

S0

S1

S2

SN�2

A0

A1

AK�1

K � log2N

SN�1

Word 0

Word 1

Word 2

WordN�2

WordN�1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals


D eco d er

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Row

Dec

oder

Bit line2L�K

Word line

AK

AK�1

AL�1

A0

M.2K

AK�1

Sense amplifiers / Drivers

Column decoder


Storage cell

Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

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Hierarchical Memory Architecture

Advantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings

Globalamplifier/driver

Controlcircuitry

Global data bus

Block selector

Block 0

Rowaddress

Columnaddress

Blockaddress

Block i Block P � 1

I/O

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Block Diagram of 4 Mbit SRAM

Subglobalrowdecoder

Globalrowdecoder

Subglobalrowdecoder

Block30

Block31

128KArrayBlock0

Block1

Clockgenerator

CS, WEbuffer

I/Obuffer

Y-addressbuffer

X-addressbuffer

x1/x4controller

Z-addressbuffer

X-addressbuffer

Predecoder and block selectorBit line load

Transfer gateColumn decoder

Sense amplifier and write driver

Localrowdecoder

[Hirose90]

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© Digital Integrated Circuits2nd Memories

ReadRead--Only Memory CellsOnly Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2


MOS OR ROMMOS OR ROM

WL[0]

VDD

BL[0]

WL[1]

WL[2]

WL[3]

Vbias

BL[1]

Pull-down loads

BL[2] BL[3]

VDD

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MOS NOR ROMMOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND


MOS NOR ROM LayoutMOS NOR ROM Layout

Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5λ x 7λ)

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MOS NOR ROM LayoutMOS NOR ROM Layout

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (11λ x 7λ)

Programmming usingthe Contact Layer Only


MOS NAND ROMMOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]

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MOS NAND ROM LayoutMOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8λ x 7λ)

Programmming usingthe Metal-1 Layer Only


NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)

Polysilicon

Threshold-alteringimplant

Metal1 on Diffusion

Programmming usingImplants Only

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Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM

" Word line parasitics# Wire capacitance and gate capacitance# Wire resistance (polysilicon)

" Bit line parasitics# Resistance not dominant (metal)# Drain and Gate-Drain capacitance

Model for NOR ROM VDD

Cbit

rword

cword

WL

BL


Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM

" Word line parasitics# Similar to NOR ROM

" Bit line parasitics# Resistance of cascaded transistors dominates# Drain/Source and complete gate capacitance

Model for NAND ROMVDD

CL

rword

cword

cbit

rbit

WL

BL

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Decreasing Word Line DelayDecreasing Word Line Delay

Metal bypass

Polysilicon word lineK cells

Polysilicon word lineWL

Driver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides


PrechargedPrecharged MOS NOR ROMMOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pre�

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NonNon--Volatile MemoriesVolatile MemoriesThe FloatingThe Floating--gate transistor (FAMOS)gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D


FloatingFloating--Gate Transistor ProgrammingGate Transistor Programming

0 V

��5 V 0 V

DS

Removing programmingvoltage leaves charge trapped

5 V

��2.5 V 5 V

DS

Programming results inhigher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection

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A “ProgrammableA “Programmable--Threshold” TransistorThreshold” Transistor

“0”-state “1”-state

�VT

VWL VGS

“ON”

“OFF”

ID


FLOTOX EEPROMFLOTOX EEPROM

Floating gate

Source

Substratep

Gate

Drain

n� n�

FLOTOX transistorFowler-NordheimI-V characteristic

20–30 nm

10 nm

-10 V

10 V

I

VGD

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EEPROM CellEEPROM Cell

WL

BL

VDD

Absolute threshold controlis hardUnprogrammed transistormight be depletion$$$$ 2 transistor cell


Flash EEPROMFlash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n� source n� drainprogramming

Many other options …

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CrossCross--sections of NVM cellssections of NVM cells

EPROMFlashCourtesy Intel


Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――EraseErase

S D

12 VG

cell arrayBL0 BL1

open open

WL0

WL1

0 V

0 V

12 V

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Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――WriteWrite

S D

12 V

6 VG

BL0 BL1

6 V 0 V

WL0

WL1

12 V

0 V

0 V


Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――ReadRead

5 V

1 VG

S D

BL0 BL1

1 V 0 V

WL0

WL1

5 V

0 V

0 V

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NAND Flash MemoryNAND Flash Memory

Unit Cell

Word line(poly)

Source line(Diff. Layer)

Courtesy Toshiba

Gate

ONO

FGGateOxide


NAND Flash MemoryNAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

Courtesy Toshiba

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Characteristics of StateCharacteristics of State--ofof--thethe--art NVMart NVM


ReadRead--Write Memories (RAM)Write Memories (RAM)" STATIC (SRAM)

" DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

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66--transistor CMOS SRAM Celltransistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WL

BL

VDD

M 5

M 6

M 4

M1VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit

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CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)

0

0

0.2

0.4

0.6

0.8

1

1.2

0.5

V olta g e rise [V ]

1 1.2 1.5 2Cell Ratio (CR)

2.5 3

Vol

tage

Ris

e(V

)


CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0Q = 1

M1

M4

M5

M6

VDD

VDD

WL

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CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)


6T6T--SRAMSRAM —— LayoutLayout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6

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ResistanceResistance--load SRAM Cellload SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

M3

RL RL

VDD

WL

Q Q

M1 M2

M4

BL BL


SRAM CharacteristicsSRAM Characteristics

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33--Transistor DRAM CellTransistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

WWL

BL1

M1 X

M3

M2

CS

BL2

RWL

VDD

VDD�VT

�VVDD�VTBL2

BL1

X

RWL

WWL


3T3T--DRAMDRAM —— LayoutLayout

BL2 BL1 GND

RWL

WWL

M3

M2

M1

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11--Transistor DRAM CellTransistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

M1

CS

WL

BL

CBL

VDD�VT

WL

X

sensing

BL

GND

Write 1 Read 1

VDD

VDD/2 VDD/2

∆V BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V


DRAM Cell ObservationsDRAM Cell Observations" 1T DRAM requires a sense amplifier for each bit line, dueto charge redistribution read-out." DRAM memory cells are single ended in contrast toSRAM cells."The read-out of the 1T DRAM cell is destructive; readand refresh operations are necessary for correctoperation." Unlike 3T cell, 1T cell requires presence of an extracapacitance that must be explicitly included in the design." When writing a “1” into a DRAM cell, a threshold voltageis lost. This charge loss can be circumvented bybootstrapping the word lines to a higher value than VDD

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Sense Amp OperationSense Amp Operation

�V(1)

V(1)

V(0)

t

VPRE

VBL

Sense amp activatedWord line activated


11--T DRAM CellT DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly

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SEM of polySEM of poly--diffusion capacitor 1Tdiffusion capacitor 1T--DRAMDRAM


Advanced 1T DRAM CellsAdvanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plateWord line

Insulating Layer

IsolationTransfer gate

Storage electrode

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