Lecture 13 CMOS Logic - University of California,...

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EECS141 1Lecture #13

EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits

Lecture 13Lecture 13CMOS LogicCMOS Logic

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AnnouncementsAnnouncementsHardware lab this weekHW#6 out this Thurs.

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Class MaterialClass Material

Last lectureWire models

Today’s lectureCMOS logic gates

Reading (Chapter 6)

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CMOS LogicCMOS Logic

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Combinational vs. Sequential LogicCombinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

CombinationalLogicCircuit

OutInCombinational

LogicCircuit

OutIn

State

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Static CMOS GatesStatic CMOS GatesAt every point in time (except during the switchingtransients) each gate output is connected to eitherVDD or VSS via a low resistive path.

The outputs of the gates assume at all times the valueof the Boolean function implemented by the circuit(ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit style, whichrelies on temporary storage of signal values on thecapacitance of high-impedance circuit nodes.

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Static Complementary CMOSStatic Complementary CMOSVDD

F(In1,In2,…InN)

In1In2

InN

In1In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networksPUN and PDN functions are complementary

……

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NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

Y = X if A AND B

Y = X if A OR B

Transistor ↔ switch controlled by its gate signalNMOS switch closes when switch control input is high

NMOS transistors pass a “strong” 0 but a “weak” 1

A B

X Y

X Y

A

B

AND

OR

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PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection

PMOS switch closes when switch control is low

PMOS transistors pass a “strong” 1 but a “weak” 0

X Y

A B

A

BX Y

NOR

NAND

Y = X if A AND B = A + B

Y = X if A OR B = AB

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Threshold DropsThreshold DropsVDD

VDD → 0PDN

0 → VDD

CL

CL

PUN

VDD

0 → VDD - VTn

CL

VDD

VDD

VDD → |VTp|

CL

S

D S

D

VGS

S

SD

D

VGS

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Complementary CMOS Logic StyleComplementary CMOS Logic StylePUP is the dual to PDN(can be shown using DeMorgan’s Theorems)

Static CMOS gates are always inverting

A + B = AB

AB = A + B

AND = NAND + INV

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Example Gate: NANDExample Gate: NAND

PDN: G = AB ⇒ Conduction to GNDPUN: F = A + B = AB ⇒ Conduction to VDD

G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)

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Example Gate: NORExample Gate: NOR

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Complex CMOS GateComplex CMOS Gate

OUT = D + A • (B + C)

DA

B C

D

AB

C

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Constructing a Complex GateConstructing a Complex Gate

C

(a) pull-down network

SN1 SN4

SN2

SN3D

FF

A

DB

C

D

F

A

B

C

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

D

A

A

B

C

VDD VDD

B

(c) complete gate

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Another ExampleAnother Example

Y = A+BC

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Cell DesignCell Design

Standard CellsGeneral purpose logicUsed to synthesize RTL/HDLSame height, varying width

Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cell

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Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980s

signals

Routingchannel

VDD

GND

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Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s 1990s -- TodayToday

M2

No routingchannels VDD

GNDM3

VDD

GND

Mirrored Cell

Mirrored Cell

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Standard CellsStandard Cells

Cell boundary

N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects

Cell height is “12 Mn pitch”

2λ

Rails ~10λ

InOut

VDD

GND

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InOut

VDD

GND

In Out

VDD

GND

With silicideddiffusion

With minimaldiffusionrouting

OutIn

VDD

M2

M1

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A

Out

VDD

GND

B

2-input NAND gate

B

VDD

A

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Stick DiagramsStick DiagramsContains no dimensionsRepresents relative positions of transistors

In

Out

VDD

GND

Inverter

A

Out

VDD

GNDB

NAND2

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Stick DiagramsStick Diagrams

C

A B

X = C • (A + B)

B

AC

i j

VDDX

X

i

GND

AB

C

PUN

PDNABC

Logic Graph

j

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Two Versions of C Two Versions of C •• (A + B)(A + B)

X

CA B A B C

X

VDD

GND

VDD

GND

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Consistent Euler PathConsistent Euler Path

j

VDDX

X

i

GND

AB

C

A B C

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OAI22 Logic GraphOAI22 Logic Graph

C

A B

X = (A+B)•(C+D)

B

A

D

VDDX

X

GND

AB

C

PUN

PDN

C

D

D

ABCD

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Example: x = Example: x = ab+cdab+cd

GND

x

a

b c

d

VDDx

GND

x

a

b c

d

VDDx

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

a c d

x

VDD

GND

(c) stick diagram for ordering {a b c d}b

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MultiMulti--Fingered TransistorsFingered TransistorsOne finger Two fingers (folded)

Less diffusion capacitance

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CMOS PropertiesCMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relative device sizes; ratiolessAlways a path to Vdd or Gnd in steady state; low output impedanceExtremely high input resistance; nearly zero steady-state input currentNo direct path steady state between power and ground; no static power dissipationPropagation delay function of load capacitance and resistance of transistors

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CMOS logic - properties

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