AnasimAnasim --ffPower integrity analyzer/optimizerPower integrity analyzer/optimizer

Bottomline BenefitsBottomline Benefits

Raj Nair, Raj Nair, AnasimAnasim Corporation Corporation Q3 2010Q3 2010

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10,000 Inductors +10,000 Inductors +

Through abstraction, pi-fp simulates grids of Through abstraction, pi-fp simulates grids of 100x100 bus pairs, or 10,000 inductors or 100x100 bus pairs, or 10,000 inductors or more, and other associated components, more, and other associated components, without issues typical in spice. without issues typical in spice.

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Speed independent of Speed independent of devicesdevices

Simulation time is determined only by chip Simulation time is determined only by chip area and spatial accuracy desired. Number of area and spatial accuracy desired. Number of wires, circuit blocks, capacitances, etc. do not wires, circuit blocks, capacitances, etc. do not affect simulation speed. affect simulation speed.

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Optimization capabilityOptimization capability

Simulation speed permits resource usage DOE Simulation speed permits resource usage DOE for aspects such as power grid wire width, bus for aspects such as power grid wire width, bus pitch, on-die capacitance requirements, etc., pitch, on-die capacitance requirements, etc., as determined by desired power noise (PI) & as determined by desired power noise (PI) & operating supply level.operating supply level.

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Constraint relaxation pre-Constraint relaxation pre-synth.synth.

Front-end analysis and optimization capability Front-end analysis and optimization capability permits relaxation of routing constraints prior permits relaxation of routing constraints prior to place & route, speeding timing and physical to place & route, speeding timing and physical design convergence. design convergence.

Q: What are some of the methodology issues that limit IC layout productivity?A: Having teams with separate front-end and back-end people. You need an automated way to pass constraints for the circuit designer on the front-end to the layout designer on the back-end. Even floorplanning constraints can be set by the circuit designer.From: http://www.chipdesignmag.com/payne/2010/08/12/cadence-virtuoso-update/

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True Electromagnetic True Electromagnetic SimulatorSimulator

-fp captures true on-chip/system noise

9 x 7mm chip

5nF /sq. cm distributedCAP

100mA peak noise pulseof 100pswidth

Power grid simulation

Explicit CAP LENS

Pulse noise source

Differential noise

R+L+C Dynamic Noise Simulation in -fp

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Backup

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Advanced SiP Solutions Advanced SiP Solutions AnalysisAnalysis

Near load systemsNear load systems Active Noise Regulator*Active Noise Regulator* Distributed Local Voltage Distributed Local Voltage

RegulatorsRegulators

Integrated SolutionsIntegrated Solutions On-Chip Dynamic Voltage On-Chip Dynamic Voltage

Scaling (DVS)Scaling (DVS) Energy Management in Energy Management in

Package (EMP)Package (EMP) Stacked power Stacked power

conversion silicon layerconversion silicon layer

Chip power grid noise

ANR attached to top left corner of gridReference:* Nair & Bennett, ComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373

Intel® CMOS Regulator chip

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