adc12j400

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ADC12J4000SLAS989B JANUARY 2014 REVISED SEPTEMBER 2014

A D C 1 2 J 4 0 0 0 1 2 -B i t 4 G S P S A D C W i t h In te g r a te d D D C

1 Features 2 Applications

1 Excellent Noise and Linearity up to and beyond Wireless Infrastructure

FIN = 3 GHz RF-Sampling Software Defined Radio

Configurable DDC Wideband Microwave Backhaul Decimation Factors from 4 to 32 (Complex Military Communications

Baseband Out) SIGINT Usable Output Bandwidth of 800 MHz at RADAR and LIDAR

4x Decimation and 4000 MSPS DOCSIS / Cable Infrastructure

Usable Output Bandwidth of 100 MHz at Test and Measurement

32x Decimation and 4000 MSPS

Bypass Mode for Full Nyquist Output Bandwidth 3 Description Low Pin-Count JESD204B Subclass 1 Interface The ADC12J4000 device is a wideband sampling and Automatically Optimized Output Lane Count digital tuning device. Texas Instruments' giga-sample

analog-to-digital converter (ADC) technology enables Embedded Low Latency Signal Range Indicationa large block of frequency spectrum to be sampled

Low Power Consumption directly at RF. An integrated DDC (Digital Down Key Specifications Converter) provides digital filtering and down-

conversion. The selected frequency block is made Max Sampling Rate: 4000 MSPSavailable on a JESD204B serial interface. Data is

Min Sampling Rate: 1000 MSPSoutput as baseband 15-bit complex information for

DDC Output Word Size: 15-Bit Complex (30 ease of downstream processing. Based on the digitalbits total) down-converter (DDC) decimation and link output

rate settings, this data is output on 1 to 5 lanes of the Bypass Output Word Size: 12-Bit Offset Binaryserial interface.

Noise Floor: 149 dBFS/Hz or150.8 dBm/HzA DDC bypass mode allows the full rate 12-bit raw IMD3: 64 dBc (FIN = 2140 MHz 30 MHz atADC data to also be output. This mode of operation13 dBFS)requires 8 lanes of serial output.

FPBW (3 dB): 3.2 GHzThe ADC12J4000 device is available in a 68-pin

Peak NPR: 46 dB VQFN package. The device operates over the Supply Voltages: 1.9 V and 1.2 V Industrial (40C TA 85C) ambient temperature

range. Power Consumption

Bypass (4000 MSPS): 2 WDevice Information(1)

Decimate by 10 (4000 MSPS): 2 WPA RT NUMB ER PA CK AGE B ODY SIZE (NOM)

Power Down Mode:

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ADC12J4000SLAS989B JANUARY 2014 REVISED SEPTEMBER 2014 www.ti.com

Table of Contents

7.5 Programming........................................................... 501 Feat ures .................................................................. 17.6 Register Map........................................................... 522 Appl icat ions ........................................................... 1

8 Application and Implementation ........................ 773 Des cript ion ............................................................. 18.1 Application Information............................................774 Revision History..................................................... 28.2 Typical Application .................................................77

5 Pin Configuration and Functions ......................... 3 8.3 Initialization Set-Up .................................................816 Specifications......................................................... 8

8.4 Dos and Don'ts........................................................ 816.1 Absolute Maximum Ratings ...................................... 8

9 Power Supply Recommendations ...................... 826.2 Handling Ratings.......................................................8

9.1 Supply Voltage........................................................826.3 Recommended Operating Conditions.......................9

10 Layout................................................................... 826.4 Thermal Information..................................................910.1 Layout Guidelines ................................................. 826.5 Electrical Characteristics...........................................910.2 Layout Example ....................................................836.6 Timing Requirements..............................................1410.3 Thermal Management...........................................856.7 Internal Characteristics ...........................................16

11 Device and Documentation Support .................856.8 Switching Characteristics........................................1711.1 Device Support......................................................856.9 Typical Characteristics ............................................1811.2 Documentation Support ........................................877 Detailed Description ............................................ 2611.3 Trademarks...........................................................877.1 Overview ................................................................. 2611.4 Electrostatic Discharge Caution............................877.2 Functional Block Diagram .......................................26

11.5 Glossary................................................................877.3 Feature Description................................................. 2712 Mechanical, Packaging, and Orderable7.4 Device Functional Modes........................................45

Information ........................................................... 87

4 Revision History

Changes from Revision A (February 2014) to Revision B Page

Changed the device status fromProduct Preview to Production Data .................................................................................. 1

2 Submit Documentation Feedback Copyright 2014, Texas Instruments Incorporated

Product Folder Links: ADC12J4000
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DNC

VA12

Tdiode+

VD12

DS7+/NCO_

2b

Tdiode

VA19

DS7-/NCO_

2a

VD12

VA19

VA12

VNEG

VA19

VNEG

VA12

VA19

VIN+

RSV

SYSREF

SYSREF+

VIN

VCMO

VA19

DEVCLK+

VA12

VBG

RBIAS+

VA12

SYNC~+/TMST+

VA12

VA12

RBIAS

DEVCLK

VD12

VNEG_

OUT

SYNC~

VD12

DS0

DS0+

VD12

VD12

DS2

DS2+

VD12

DS3

DS3+

RSV2

VA19

SCSb

SCLK

SDI

SDO

DS6+/NCO_1b

DS6/NCO_1a

VD12

DS5+/NCO_0b

DS5/NCO_0a

DS4+

DS4

VD12

VD12

SYNC~/TMST

VA19

OR_

T1

OR_

T0

VA19

DS1

DS1+

1

17

18

34

35

51

52

68

2

3

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ADC12J4000www.ti.com SLAS989B JANUARY 2014REVISED SEPTEMBER 2014

5 Pin Configuration and Functions

NKE Package68-Pin VQFN With Thermal Pad

Top View

DNC = Make no external connection

Copyright 2014, Texas Instruments Incorporated Submit Documentation Feedback 3


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IN+

VIN

VCM

To T&H+

To T&H

50

50

20 k

LPEAK

LPEAK

VA19

GND

VA19

GND

GND

VA19

VCM

Tdiode+

Tdiode

GND

VBIAS


Pin Functions

PINEQUIVALENT CIRCUIT TYPE DESCRIPTION

NAME NO.

ANAL OG

RBIAS+ 1

External Bias Resistor ConnectionsExternal bias resistor terminals. A 3.3 k (0.1%) resistor should be connectedbetween RBIAS+ and RBIAS. The RBIAS resistor is used as a reference for

I/Ointernal circuits which affect the linearity of the converter. The value and precisionRBIAS 2of this resistor should not be compromised. These pins must be isolated from allother signals and grounds.

TDIODE 63Temperature DiodeThese pins are the positive (anode) and negative (cathode) diode connections for

Passivedie temperature measurements. Leave these pins unconnected if they are notTDIODE+ 64used. See the Built-In Temperature Monitor Diode section for more details.

Bandgap Output VoltageThis pin is capable of sourcing or sinking 100 A and can drive a load up to 80 pF.

VBG 68 OLeave this pin unconnected if it is not used in the application. See the TheReference Voltage section for more details.

Common Mode VoltageThe voltage output at this pin must be the common-mode input voltage at the VIN+

VCMO 3 O and VIN pins when DC coupling is used. This pin is capable of sourcing or sinking100A and can drive a load up to 80 pF. Leave this pin unconnected if it is notused in the application.

VIN+ 8

Signal InputThe differential full-scale input range is determined by the full-scale voltage adjust

Iregister. An internal peaking inductor (LPEAK) of 5 nH is included for parasiticVIN 9compensation.


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VA19

GND

GND

VA19

VD12

GND

+

50

50

VA19

E

VD12

GND

+

50

50

VA19


Pin Functions (continued)


NAME NO.

DATA

DS0 32

DS0+ 33

DS1 35

DS1+ 36Data

DS2 38 CML These pins are the high-speed serialized-data outputs with user-configurableO

pre-emphasis. These outputs must always be terminated with a 100-differentialDS2+ 39resistor at the receiver.

DS3 41

DS3+ 42

DS4 44

DS4+ 45

DS5/NCO_0 47

DS5+/NCO_0 48 Data

DS6/NCO_1 50 DS5/NCO_0, DS5+/NCO_0, DS6/NCO_1, DS6+/NCO_1,DS7/NCO_2 and DS7+/NCO_2: When decimation is enabled, theseDS6+/NCO_1 51pins become LVCMOS inputs and allow the host device to select the

DS7/NCO_2 53 O/I specific NCO frequency or phase accumulator that is active. In this modethe positive (+) and negative () pins should be connected together andboth driven. An acceptable alternative is to let one of the pair float whilethe other pin is driven. Connect these inputs to GND if they are not usedDS7+/NCO_2 54in the application.

GROUND, RESERVED, DNC

Do Not ConnectDNC 67

Do not connect DNC to any circuitry, power, or ground signals.

ReservedConnect to Ground or Leave Unconnected: This reserved pin is a logic input for

RSV 66 possible future device versions. It is recommended to connect this pin to ground.Floating this pin is also permissible.

ReservedRSV2 61 Connect to Ground Connect this reserved input pin to ground for proper operation.

Ground (GND)The exposed pad on the bottom of the package is the ground return for all supplies.This pad must be connected with multiple vias to the printed circuit board (PCB)

Thermal Pad ground planes to ensure proper electrical and thermal performance.The exposed center pad on the bottom of the package must be thermally andelectrically connected (soldered) to a ground plane to ensure rated performance.

LVCMOS

OR_T0 25

Over-RangeO Over-range detection status for T0 and T1 thresholds. Leave these pins

OR_T1 26 unconnected if they are not used in the application.



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VA19

AGND

VA19

AGND

V(CM_CLK)

50

50

1 k

VA19

GND

GND

VA19




NAME NO.

Serial Interface ClockThis pin functions as the serial-interface clock input which clocks the serial data in

SCLK 58 Iand out. The Using the Serial Interface section describes the serial interface inmore detail.

Serial Data InSDI 57 I This pin functions as the serial-interface data input. TheUsing the Serial Interface

section describes the serial interface in more detail.

SYNC~This pin provides the JESD204B-required synchronizing request input. A logic-low

SYNC~ 30 I applied to this input initiates a lane alignment sequence. The choice of LVCMOS or differential SYNC~ is selected through bit 6 of the configuration register 0x202h.Connect this input to GND or VA19 if differential SYNC~ input is used.

Serial Chip Select (active low)SCS 59 I This pin functions as the serial-interface chip select. The Using the Serial Interface


Serial Data OutSDO 56 O This pin functions as the serial-interface data output. The Using the Serial Interface


DIFFERENTIAL INPUT

DEVCLK+ 15 Device Clock InputI The differential device clock signal must be AC coupled to these pins. The input

DEVCLK 16 signal is sampled on the rising edge of CLK.

SYSREF+ 19 SYSREFThe differential periodic waveform on these pins synchronizes the device per

I JESD204B. If JESD204B subclass 1 synchronization is not required and theseSYSREF 20 inputs are not utilized they may be left unconnected. In that case ensure

SysRef_Rcvr_En=0 and SysRef_Pr_En=0.

SYNC~+/TMST+ 22 SYNC~/TMSTThis differential input provides the JESD204B-required synchronizing request input.

A di fferential logic-low applied to these inputs initiates a lane alignment sequence.

For SYNC~ usage, ensure that SYNC_DIFF_PD = 0 and SYNC_DIFFSEL = 1.When the LVCMOS SYNC~ is selected these inputs can be used as the differential

ITIMESTAMP input. For TMST usage, ensure that SYNC_DIFF_PD = 0,SYNC~-/TMST 23SYNC_DIFFSEL = 0, and TIME_STAMP_EN = 1. For additional information seetheTime Stampsection.These inputs may be left unconnected if they are not used for either the SYNC~ orTIMESTAMP functions.



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NAME NO.

POWER

6

11

14Anal og 1.2 V pow er sup ply pin s

VA12 17 Bypass these pins to ground using one 10-F capacitor and two 1-F capacitors for bulk decoupling plus one 0.1-F capacitor per pin for individual decoupling.

18

21

65

4

7

10

Anal og 1.9 V pow er sup ply pin s13VA19 Bypass these pins to ground using one 10-F capacitor and two 1-F capacitors for

24 bulk decoupling plus one 0.1-F capacitor per pin for individual decoupling.

27

60

6228

31

34

37

Digital 1.2 V power supply pins40VD12 Bypass these pins to ground using one 10-F capacitor and two 1-F capacitors for

43 bulk decoupling plus one 0.1-F capacitor per pin for individual decoupling.

46

49

52

55

5 VNEGThese pins must be decoupled to ground with a 0.1-F ceramic capacitor near

VNEG I each pin. These power input pins must be connected to the VNEG_OUT pin with a

12 low resistance path. The connections must be isolated from any noisy digitalsignals and must also be isolated from the analog input and clock input pins.

VNEG_OUTThe voltage on this output can range from 1V to +1V. This pin must be decoupled

VNEG_OUT 29 O to ground with a 4.7-F, low ESL, low ESR multi-layer ceramic chip capacitor andconnected to the VNEG input pins. This voltage must be isolated from any noisydigital signals, clocks, and the analog input.



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I/O

GND

VA19

To InternalCircuitry


6 Specifications

6.1 Absolute Maximum Ratings

The soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (1)(2)(3)

MIN MAX UNIT

1.2-V supply VA12, VD12 1.4 V

Supply voltage 1.9-V supply VA19 2.2 V

1.2-V supply difference between VA12 and VD12 200 200 mV

On any input pin (except VIN+ or VIN) V(VA19)+0.15 V0.15Voltage

On VIN+ or VIN 0 2 V

Voltage difference (VIN+) (VIN), (VIN) (VIN+)(4) 2 V

On VIN+, VIN, with proper input common mode maintained. FIN 3 GHz, 11.07Z(SOURCE)= 100 , Input_Clamp_EN = 0 or 1

On VIN+, VIN, with proper input common mode maintained. FIN = 1 GHz,RF input power, PI 14.95 dBmZ(SOURCE)= 100 , Input_Clamp_EN = 1

On VIN+, VIN, with proper input common mode maintained. FIN 100 MHz, 20.97Z(SOURCE)= 100 , Input_Clamp_EN = 1

At any pin other than VIN+ or VIN(5) 25 25 mA

VIN+ or VIN 50 50 mA DCInput current

Package(5) (sum of absolute value of all currents forced in or out, not including100 mA

power supply current)

(1) Reflow temperature profiles are different for lead-free and non-lead-free packages.(2) Stresses beyond those listed underAbsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability andspecifications.

(4) The analog inputs are protected as in the following circuit. Input-voltage magnitudes beyond theAbsolute Maximum Ratingsmaydamage this device.

(5) When the input voltage at any pin (other than VIN+ or VIN) exceeds the power supply limits (that is, less than GND or greater thanVA19), the current at that pin must be limited to 25 mA. The 100-mA maximum package input current rating limits the number of pinsthat can safely exceed the power supplies. This limit is not placed upon the power pins or thermal pad (GND).

6.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range 65 150 CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

2000 2000pins (1)Electrostatic

V(ESD) Vdischarge Charged device model (CDM), per JEDEC specification JESD22-500 500

C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.


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6.3 Recommended Operating Conditions

All voltages are measured with respect to GND = 0 V, unless otherwise specified.

MIN MAX UNIT

1.2-V supply: VA12, VD12 1.14 1.26 VVDD Supply voltage

1.9-V supply: VA19 1.8 2 V

Supply sequence (power-up and power-down) 1.9 supply 1.2 Vsupply

VCMI Analog input common mode voltage V(VCMO) 0.15 V(VCMO)+ 0.15 V

VIN+, VIN voltage (maintaining common mode) 0 V(VA19) V

CLK pin voltage range 0 V(VA19) V

Differential CLK amplitude 0.4 2 VPP

TA Ambient temperature 40 85 C

TJ Junction temperature 135 C

6.4 Thermal InformationVQFN

THERMAL METRIC (1) UNIT(68 PINS)

RJA Thermal resistance, junction-to-ambient 19.8

RJCbot Thermal resistance, junction-to-case (bottom) 2.7 C/W

JB Characterization parameter, junction-to-board 9.1

(1) For more information about traditional and new thermal metrics, see theIC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for V(VA12)= V(VD12)= 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default

setting (725 mVPP), VIN = 1 dBFS, differential AC-coupled sinewave input clock, (DEVCLK)= 4 GHz at 0.5 VPPwith 50% duty

cycle, R(RBIAS)= 3.3 k 0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at

TA= 25C.(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC PERFORMANCE CHARACTERISTICS

RES ADC core resolution Resolution with no missing codes 12 bits

TA= 25C 2INL Integral non-linearity LSBTA= TMIN to TMAX 3

TA= 25C 0.25DNL Differential non-linearity LSB

TA= TMIN to TMAX 0.3

500-kHz tone spacing from 1 MHz to S/ 21MHz, DDC bypass modePeak NPR Peak noise power ratio 46 dB25-MHz wide notch at 320 MHz

Third-order intermodulation F1 = 2110 MHz at13 dBFSIMD3 64 dBcdistortion F2 = 2170 MHz at13 dBFS

DDC BYPASS Mode

FIN = 350 MHz, 1 dBFS, 12-bit DDC bypass mode 55

TA= 25C 54.8

TA= TMINto TMAX 52.5Signal-to-noise ratio, FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassintegrated across entire modeSNR1 TA= 25C, calibration = BG 53.9 dBFSNyquist bandwidthInterleaving spurs included TA= TMINto TMAX, calibration = BG 49.4

FIN = 1500 MHz, 1 dBFS, 12-bit DDC bypass mode 51.2


TA= 25C(3) 55

Signal-to-noise ratio,TA= TMINto TMAX

(3) 53i nteg ra te d a cr oss e ntir e FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassSNR2 dBFSNyquist bandwidth mode TA= 25C, calibration = BG

(3) 55Interleaving spurs excluded

TA= TMINto TMAX, calibration = BG(3) 53

(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one ormore bypass capacitors.

(2) Interleave related fixed frequency spurs at S/ 4 and S / 2 are excluded from these calculations unless otherwise noted. The magnitudeof these spurs is provided separately.

(3) Interleave related spurs at S / 2 FIN, S/ 4 + FIN and S / 4 FIN are excluded from these performance calculations. The magnitudeof these spurs is provided separately.


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Electrical Characteristics (continued)




TA= 25C.(1)(2)



TA= 25C 54.7

TA= TMINto TMAX 52.3Signal-to-noise and distortion FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassratio, integrated across entire modeSINAD1 TA= 25C, calibration = BG 53.8 dBFSNyquist bandwidthInterleaving spurs included TA= TMINto TMAX, calibration = BG 49.2



TA= 25C(3) 54.9

Signal-to-noise and distortionTA= TMINto TMAX

(3) 52.7ratio, integrated across DDC FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassSINAD2 dBFSoutput bandwidth mode TA= 25C, calibration = BG

(3) 54.9Interleaving spurs excluded

TA= TMINto TMAX, calibration = BG(3) 52.7


TA= 25C 8.8

TA= TMINto TMAX 8.4Effective number of bits, FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassintegrated across entire modeENOB1 TA= 25C, calibration = BG 8.7 BitsNyquist bandwidth

Interleaving spurs included TA= TMINto TMAX, calibration = BG 7.9



TA= 25C(3) 8.8

Effective number of bits,TA= TMINto TMAX

(3) 8.5i nteg ra te d a cr oss e ntir e FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassENOB2 BitsNyquist bandwidth mode TA= 25C, calibration = BG

(3) 8.8Interleaving spurs excluded

TA= TMINto TMAX, calibration = BG(3) 8.5


TA= 25C 70.7

TA= TMINto TMAX 60FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassSpurious-free dynamic range modeSFDR1 TA= 25C, calibration = BG 63.4 dBFSInterleaving spurs included

TA= TMINto TMAX, calibration = BG 51.8



TA= 25C(4) 73

TA= TMINto TMAX(4) 61.6

Spurious-free dynamic range FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassSFDR2 dBFSTA= 25C, calibration = BG(4) 74Interleaving spurs excluded mode

TA= TMINto TMAX, calibration = BG 62.8(4)mode


TA= 25C 76

TA= TMINto TMAX 60FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassInterleaving offset spur at modeS/2 TA= 25C, calibration = BG 68 dBFSsampling rate

TA= TMINto TMAX, calibration = BG 55




TA= 25C 70

TA= TMINto TMAX 55FIN = 600 MHz, 1 dBFS, 12-bit DDC bypassInterleaving offset spur at modeS/4 TA= 25C, calibration = BG 61 dBFSsampling rate

TA= TMINto TMAX, calibration = BG 47.4



(4) Interleave related spurs at S / 2 FIN, S/ 4 + FIN and S / 4 FIN are excluded from these performance calculations. The magnitudeof these spurs is provided separately.



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TA= 25C.(1)(2)


10.2Effective number of bits, FIN = 600 MHz, 1 dBFS, decimate-by-8integrated across DDC output modeENOB1 Calibration = BG 10.0 BitsbandwidthInterleaving spurs included FIN = 2400 MHz, 1 dBFS, decimate-by-8 mode 8.8

Effective number of bits, 10.2FIN = 600 MHz, 1 dBFS, decimate-by-8integrated across DDC output

ENOB2 Bitsbandwidth mode(5) Calibration = BG 10.2Interleaving spurs excluded

74.9Spurious-free dynamic range FIN = 600 MHz, 1 dBFS, decimate-by-8SFDR1 dBFSInterleaving Spurs Included mode Calibration = BG 68.3

77.8FIN = 600 MHz, 1 dBFS, decimate-by-8Spurious-free dynamic rangeSFDR2 dBFS

Interleaving spurs excluded mode(5) Calibration = BG 77.8

73Interleaving offset spur at FIN = 600 MHz, 1 dBFS, decimate-by-8S/2 dBFSsampling rate(6) mode Calibration = BG 72

70Interleaving offset spur at FIN = 600 MHz, 1 dBFS, decimate-by-8S/4 dBFSsampling rate(6) mode Calibration = BG 66

Interleaving spur at 76FIN = 600 MHz, 1 dBFS, decimate-by-8S/2 FIN sampling rate input dBFSmode Calibration = BG 67frequency(6)

Interleaving spur at 72FIN = 600 MHz, 1 dBFS, decimate-by-8S/4 + FIN sampling rate + input dBFSmode Calibration = BG 64frequency(6)

Interleaving spur at 74FIN = 600 MHz, 1 dBFS, decimate-by-8S/4 FIN sampling rate input dBFSmode Calibration = BG 67frequency(6)

70FIN = 600 MHz, 1 dBFS, decimate-by-8modeTHD Calibration = BG 72 dBFSTotal harmonic distortion(6)

FIN = 2400 MHz, 1 dBFS, decimate-by-8 mode 71

80FIN = 600 MHz, 1 dBFS, decimate-by-8modeHD2 Calibration = BG 79 dBFSSecond harmonic distortion(6)

FIN = 2400 MHz, 1 dBFS, decimate-by-8 mode 78

74

FIN = 600 MHz, 1 dBFS, decimate-by-8modeHD3 Calibration = BG 80 dBFSThird harmonic distortion(6)

FIN = 2400 MHz, 1 dBFS, decimate-by-8 mode -77

DDC CHARACTERISTICS

Alias protection (7) 80 dB

% ofAlias protected bandwidth(7) 80

output BW

Spurious-free dynamic rangeSFDR-DDC 100 dB

of digital down-converter(7)

Implementation loss(7) 0.5 dB

ANALOG INPUT CHA RACTERISTICS

Minimum FSR setting(8) 500

Full-scale analog-differentialVID(VIN) Default FSR setting, TA= TMINto TMAX 650 725 800 mVPPinput range

Maximum FSR setting(8) 950

Differential 0.05 pFC

I(VIN)

Analog input capacitance(7)

Each input pin to ground 1.5 pF

RID(VIN) Differential input resistance 80 95 110

3 dB calibration = BG 2.8FPBW Full power bandwidth GHz

3 dB calibration = FG 3.2

(6) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimationand NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.

(7) This parameter is specified by design and is not tested in production.(8) This parameter is specified by design, characterization, or both and is not tested in production.



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TA= 25C.(1)(2)


DC to 2 GHz 1.2

2 GHz to 4 GHz 3.8Gain flatness dB

DC to 2 GHz calibration = BG 1.5

2 GHz to 4 GHz calibration = BG 4.5

ANALOG OUTPUT CHA RACTERISTICS (VCMO, VBG)

I(VCMO)= 100 A, TA= 25C 1.225Common-mode outputV(VCMO) Vvoltage I(VCMO)= 100 A, TA= TMINto TMAX 1.185 1.265

Common-mode output-TCVO(VCMO) volt age temperature TA= TMIN to TMAX -21 ppm/C

coefficient

Maximum VCMO output loadC(LOAD_VCMO) 80 pFcapacitance

I(BG)= 100 A, TA= 25C 1.248Bandgap reference outputVO(BG) Vvoltage I(BG)= 100 A, TA= TMINto TMAX 1.195 1.3

Bandgap reference voltage TA= TMIN to TMAX,

TCVref(BG) 0 ppm/Ctempe ra tu re coe fficie nt I(BG)= 100 A

Maximum bandgap referenceC(LOAD_BG) 80 pFoutput load capacitance

TEMPERATURE DIODE CHARACTERISTICS

Offset voltage (approx. 0.77 V) varies with 100-A forward current1.6 mV/C

process and must be measured for each Device activeTemperature diode voltage

V(TDIODE) part. Offset measurement should be doneslope 100-A forward currentwith PowerDown=1 to minimize device self- 1.6 mV/CDevice in power-downheating.

CLOCK INPUT CHARACTERISTICS (DEVCLK, SYSREF, SYNC~/TMST)

Sine wave clock, TA= TMIN to TMAX 0.4 0.6 2 VPPVID(CLK) Differential clock input level

Square wave clock, TA= TMINto TMAX 0.4 0.6 2 VPP

II(CLK) Input current VI = 0 or VI = VA 1 A

Differential 0.02 pFCI(CLK) Input capacitance

(9)

Each input to ground 1 pF

TA= 25C 95

RID(CLK) Differential input resistanceTA= TMIN to TMAX 80 110

CML OUTPUT CHARACTERISTICS (DS0DS7)

Assumes ideal 100-loadVOD Differential output voltage Measured differentially 280 305 330 mV peak

Default pre-emphasis setting

VO(ofs) Output offset voltage 0.6 V

Output+ and output shorted together 6IOS Output short-circuit current mA

Output+ or output shorted to 0 V 12

ZOD Differential output impedance 100

LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)

VIH Logic high input voltage See (10) 0.83 V

VIL L og ic l ow i np ut vol ta ge S ee (10) 0.4 V

CI Input capacitance(9)(11) Each input to ground 1 pF

LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)

VOH CMOS H level output IOH= 400 A (10) 1.65 1.9 V

VOL CMOS L level output IOH= 400 A(10) 0.01 0.15 V

(9) This parameter is specified by design and is not tested in production.(10) This parameter is specified by design, characterization, or both and is not tested in production.(11) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately

0.4 pF.



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TA= 25C.(1)(2)


POWER SUPPLY CHARACTERISTICS

PD = 0, calibration = FG, bypass DDC 461 500

I(VA19) Analog 1.9-V supply current PD = 0, calibration = BG, bypass DDC 560 600 mA

PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 560 607


I(VA12) Analog 1.2-V supply current PD = 0, calibration = BG, bypass DDC 364 420 mA



I(VD12) Digital 1.2-V supply current PD = 0, calibration = BG, bypass DDC 458 732 mA


PD = 0, calibration = FG, bypass DDC 1.8 2.26

PD = 0, calibration = BG, bypass DDC 2.05 2.52 WPC Power consumption

PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 2.17 2.66

PD = 1 < 50 mW

6.6 Timing RequirementsMIN NOM MAX UNIT

DEVICE (SAMPLING) CLOCK

(DEVCLK) Input DEVCLK frequency Sampling rate is equal to clock input 1 4 GHz

td(A) Sampling (aperture) delay Input CLK transition to sampling instant 0.64 ns

t(AJ) Aperture jitter 0.1 ps RMS

t(LAT) ADC core latency(1) Decimation = 1, DDR = 1, P54 = 0 64 t(DEVCLK)

Decimation = 4, DDR = 1, P54 = 0 292

Decimation = 4, DDR = 1, P54 = 1 284

Decimation = 8, DDR = 0, P54 = 0 384

Decimation = 8, DDR = 0, P54 = 1 368

Decimation = 8, DDR = 1, P54 = 0 392

Decimation = 8, DDR = 1, P54 = 1 368

Decimation = 10, DDR = 0, P54 = 0 386

Decimation = 10, DDR = 1, P54 = 0 386

t(LAT_DDC) ADC core and DDC latency(1) Decimation = 16, DDR = 0, P54 = 0 608 t(DEVCLK)

Decimation = 16, DDR = 0, P54 = 1 560

Decimation = 16, DDR = 1, P54 = 0 608

Decimation = 16, DDR = 1, P54 = 1 560

Decimation = 20, DDR = 0, P54 = 0 568

Decimation = 20, DDR = 1, P54 = 0 568

Decimation = 32, DDR = 0, P54 = 0 1044

Decimation = 32, DDR = 0, P54 = 1 948

Decimation = 32, DDR = 1, P54 = 0 1044CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION)

227 Calibration = FG, T_AUTO=1

106

t(CAL) Calibration cycle time t(DEVCLK)102

Calibration = FG, T_AUTO=0106

(1) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).



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Timing Requirements (continued)

MIN NOM MAX UNIT

JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)

SYSREF to LMFC delayFunctional delay between SYSREF

td(LMFC) All decimation modes 40 t(DEVCLK)assertion latched and LMFC frameboundary(2)

LMFC to frame boundary delay - DDCbypass mode

td(TX) Functional delay from LMFC frame boundary Decimation = 1, DDR = 1, P54 = 0 52.7 t(DEVCLK)to beginning of next multi-frame intransmitted data.(3)

Decimation = 4, DDR = 1, P54 = 0 52.7

Decimation = 4, DDR = 1, P54 = 1 43.9

Decimation = 8, DDR = 0, P54 = 0 60.7

Decimation = 8, DDR = 0, P54 = 1 51.5

Decimation = 8, DDR = 1, P54 = 0 52.7

Decimation = 8, DDR = 1, P54 = 1 43.9

Decimation = 10, DDR = 0, P54 = 0 60.7

LMFC to frame boundary delay - decimationDecimation = 10, DDR = 1, P54 = 0 52.7

modestd(TX) Functional delay from LMFC frame boundary Decimation = 16, DDR = 0, P54 = 0 60.7 t(DEVCLK)

to beginning of next multi-frame inDecimation = 16, DDR = 0, P54 = 1 51.5

transmitted data (3)

Decimation = 16, DDR = 1, P54 = 0 52.7

Decimation = 16, DDR = 1, P54 = 1 43.9

Decimation = 20, DDR = 0, P54 = 0 60.7

Decimation = 20, DDR = 1, P54 = 0 52.7

Decimation = 32, DDR = 0, P54 = 0 60.7

Decimation = 32, DDR = 0, P54 = 1 51.5

Decimation = 32, DDR = 1, P54 = 0 52.7

tsu(SYNC~- SYNC~ to LMFC setup time(4)

40F) Required SYNC~ setup time relative to the internal LMFC boundary.

t(DEVCLK)th(SYNC~- SYNC~ to LMFC hold time

(4)

8F) Required SYNC~ hold time relative to the internal LMFC boundary.

SYNC~ assertion time Frame clockt

(SYNC~) 4

Required SYNC~ assertion time before de-assertion to initiate a link re-synchronization. cycles

td(LMFC) Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary 40 t(DEVCLK)

Multi-framet(ILA) Duration of initial lane alignment sequence 4 clock cycles

SYSREF

tsu(SYS) Setup time SYSREF relative to DEVCLK rising edge(5) 40 ps

th(SYS) Hold time SYSREF relative to DEVCLK rising edge(5) 40 ps

t(PH_SYS) SYSREF assertion duration after rising edge event. 8 t(DEVCLK)

t(PL_SYS) SYSREF de-assertion duration after falling edge event. 8 t(DEVCLK)

K F DDR = 0, P54 = 0

10

K F DDR = 0, P54 = 1

8t(SYS) Period SYSREF t(DEVCLK)

K F

DDR = 1, P54 = 0 5

K F DDR = 1, P54 = 1

4

(2) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).(3) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.(4) This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this

parameter is not met the device will still function correctly but will not be aligned to other devices.(5) This parameter is specified by design, characterization, or both and is not tested in production.



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Timing Requirements (continued)

MIN NOM MAX UNIT

SERIAL INTERFACE (REFER TOFigure 2)

(SCK) Serial clock frequency(6) 20 MHz

t(PH) Serial clock high time 20 ns

t(PL) Serial clock low time 20 ns

tsu Serial-data to serial-clock rising setup time(6) 10 ns

th Serial-data to serial clock rising hold time(6) 10 ns

t(CSS) SCS-to-serial clock rising setup time 10 ns

t(CSH) SCS-to-serial clock falling hold time 10 ns

t(IAG) Inter-access gap 10 ns

(6) This parameter is specified by design and is not tested in production.

6.7 Internal CharacteristicsPARAMETER TEST CONDITIONS MIN NOM MAX UNIT

DEVICE (SAMPLING) CLOCK

td(A) Sampling (aperture) delay Input CLK transition to sampling instant 0.64 ns

t(AJ) Aperture jitter 0.1 ps RMS

t(LAT) ADC core latency. See (1) Decimation = 1, DDR = 1, P54 = 0 64 t(DEVCLK)

CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION)

227 Calibration = FG, T_AUTO=1

106

t(CAL) Calibration cycle time t(DEVCLK)102

Calibration = FG, T_AUTO=0106

JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)

SYSREF to LMFC delaytd(LMFC) Functional delay between SYSREF assertion All decimation modes 40 t(DEVCLK)

latched and LMFC frame boundary (1)

LMFC to Frame Boundary delay - DDCBypass Mode

td(TX) Functional delay from LMFC frame boundary Decimation = 1, DDR = 1, P54 = 0 52.7 t(DEVCLK)to beginning of next multi-frame in transmitteddata (2)

Decimation = 4, DDR = 1, P54 = 0 52.7

Decimation = 4, DDR = 1, P54 = 1 43.9

Decimation = 8, DDR = 0, P54 = 0 60.7

Decimation = 8, DDR = 0, P54 = 1 51.5

Decimation = 8, DDR = 1, P54 = 0 52.7

Decimation = 8, DDR = 1, P54 = 1 43.9

Decimation = 10, DDR = 0, P54 = 0 60.7

LMFC to frame boundary delay - decimationDecimation = 10, DDR = 1, P54 = 0 52.7

modestd(TX) Functional delay from LMFC frame boundary Decimation = 16, DDR = 0, P54 = 0 60.7 t(DEVCLK)

to beginning of next multi-frame in transmittedDecimation = 16, DDR = 0, P54 = 1 51.5

data (2)

Decimation = 16, DDR = 1, P54 = 0 52.7

Decimation = 16, DDR = 1, P54 = 1 43.9

Decimation = 20, DDR = 0, P54 = 0 60.7

Decimation = 20, DDR = 1, P54 = 0 52.7

Decimation = 32, DDR = 0, P54 = 0 60.7

Decimation = 32, DDR = 0, P54 = 1 51.5

Decimation = 32, DDR = 1, P54 = 0 52.7

td(LMFC) Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary 40 t(DEVCLK)

Multi-framet(ILA) Duration of initial lane alignment sequence 4 clock cycles

(1) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).(2) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.



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t(CSH)

1st

clock

SCLK

16th

clock 24th

clock

SCS

t(CSS) t(CSH)

t(CSS)

t(ODZ)

SDI

t(OZD)

D7 D0D1

t(IAG)

COMMAND FIELDt(OD)

D7 D0D1SDO

Write Command

Read Command

tsu th

t(PH) t(PL)

t(PH)+ t(PL)= t(P)= 1 / (SCK)

Hi-Z Hi-Z

tsu th

SYNC~

K28.5Serial Data ILA

DEVCLK

SYSREFTx Frame Clk

K28.5XXX

Tx LMFC Boundary

tsu(SYNC~-F)

SYNC~ de-assertion

latched

SYNC~ assertion

latched

XXX ILA Valid Data

SYSREF assertion

latched

Frame ClockAlignment

Code GroupSynchronization

Initial Frame and LaneSynchronization

DataTransmission

th(SYS)tsu(SYS)

td(LMFC)

th(-SYNC~-F)

t(ILA)

td(TX)

t(SYNC~)

td(TX)

t(PH-SYS)t(PL-SYS)


6.8 Switching Characteristics

Unless otherwise noted, these specifications apply for V(VA12)= V(VD12)= 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =

Default setting, differential AC-coupled sinewave input clock, (DEVCLK)= 4 GHz at 0.5 VPPwith 50% duty cycle, R(RBIAS)= 3.3

k0.1%, after a foreground mode calibration with timing calibration enabled. Typical values are at TA = 25C.


SERIAL DATA OUTPUTS

Serialized output bit rate 1 10

DDR = 0, P54 = 0 S

1.25 DDR = 0, P54 = 1

S GbpsSerialized output bit rate

DDR = 1, P54 = 0 2 S

2.5 DDR = 1, P54 = 1

S

tTLH LH transition time differential 10% to 90%, 8 Gbps 35 ps

tTHL HL transition time differential 10% to 90%, 8 Gbps 35 ps

UI Unit interval 8 Gbps serial rate 125 ps

DDJ Data dependent jitter 8 Gbps serial rate 11.3 ps

RJ Random Jitter 8 Gbps serial rate 1.4 ps

SERIAL INTERFACE

t(OZD) SDO tri-state to driven 5 nst(ODZ) SDO driven to tri-state SeeFigure 2 2.5 5 ns

t(OD) SDO output delay 20 ns

Figure 1. JESD204 Synchron ization

Figure 2. Serial Interface Timing



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All Supply Voltage Variation from Nominal (%)

Ma

gnitude(dBFS)

-10 -5 0 5 1045

50

55

60

65

70

75

D027

SNR (dBFS)SINAD (dBFS)SFDR (dBFS)

Ambient Temperature (C)

Ma

gnitude(dBFS)

-50 -25 0 25 50 75 10045

50

55

60

65

70

75

D030


Decimation Factor

Magnitude(dBFS)

0 4 8 12 16 20 24 28 3240

50

60

70

80

90

D011


Decimation Factor

Magnitude(dBFS)

0 4 8 12 16 20 24 28 3240

50

60

70

80

90

D016


Input Frequency (MHz)

Magnitude(dBFS)

0 300 600 900 1200 1500 1800 2100 2400 2700 300045

50

55

60

65

70

75

80

D002


Sampling Rate (MSPS)

Magnitude(dBFS)

1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 520045

50

55

60

65

70

75

D001



6.9 Typical Characteristics



k0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA= 25C. VI= 1 dBFS.

DDC bypass mode FIN= 608 MHzDDC bypass mode Sampling rate = 4000 MSPS

Figure 4. SNR, SINAD, SFDR vs Sampling rateFigure 3. SNR, SINAD, SFDR vs Input Frequency

DDC bypass mode FIN= 608 MHz DDC bypass mode FIN= 2483 MHz

Figure 5. SNR, SINAD, SFDR vs Decimation Setting Figure 6. SNR, SINAD, SFDR vs Decimation Setting


Figure 7. SNR, SINAD, SFDR vs Supply Voltage Figure 8. SNR, SINAD, SFDR vs Temperature



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Decimation Factor

ENOB

(Bits)

0 4 8 12 16 20 24 28 32

8

9

10

D013 Decimation Factor

ENOB

(Bits)

0 4 8 12 16 20 24 28 32

7

8

9

D018


ENOB(Bits)

0 300 600 900 1200 1500 1800 2100 2400 2700 30005

6

7

8

9

D009Sampling Rate (MSPS)

ENOB

(Bits)

1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 52005

6

7

8

9

D008


Magnitude(dBFS)

-50 -25 0 25 50 75 10045

50

55

60

D067

SNR - Foreground at 25C (dBFS)SNR - Background (dBFS)SNR - Foreground at Each Temp (dBFS)


Magnitude(dBFS)

-50 -25 0 25 50 75 10055

60

65

70

75

80

85

D068

SFDR - Foreground at 25C (dBFS)SFDR - Background (dBFS)SFDR - Foreground at Each Temp (dBFS)


Typical Characteristics (continued)




DDC bypass mode FIN= 351 MHz DDC bypass mode Input frequency = 351 MHz

Figure 9. SNR vs Temperature and Calibration Mode Figure 10. SFDR vs Temperature and Calibration Mode

DDC bypass mode FIN= 608 MHzDDC bypass mode Sampling rate = 4000 MSPS

Figure 12. ENOB vs Sampling RateFigure 11. ENOB vs Input Frequency

FIN= 608 MHz FIN = 2483 MHz

Fi gu re 13. ENOB v s Dec im ati on Set ti ng Fi gu re 14. ENOB v s Dec imati on Set ti ng



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Magnitude(dBFS)

1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200-100

-90

-80

-70

-60

-

D001

THD (dBFS)HD2 (dBFS)HD3 (dBFS)

All Supply Variation from Nominal (%)

Magnitude(dBFS)

-10 -5 0 5 10-100

-90

-80

-70

-60

-

D029



Magnitude(dBFS)

0 300 600 900 1200 1500 1800 2100 2400 2700 3000-100

-90

-80

-70

-60

-

D003


Temperature (C)

ENOB

(Bits)

-50 -25 0 25 50 75 1007

8

9

D127

ENOB - Foreground at 25C (Bits)ENOB - Background Calibration (Bits)ENOB - Foreground at Each Temp (Bits)

All Supply Variation from Nominal (%)

ENOB

(Bits)

-10 -5 0 5 105

6

7

8

9

10

D028 Temperature (C)

ENOB

(Bits)

-50 -25 0 25 50 75 1005

6

7

8

9

D031D031







Figure 15. ENOB vs Supply Voltage Figure 16. ENOB vs Temperature

DDC bypass mode FIN= 351 MHz DDC bypass mode Sampling rate = 4000 MSPS

Figure 17. ENOB vs Temperature and Calibration Mode Figure 18. THD, HD2, HD3 vs Input Frequency


Figure 19. THD, HD2, HD3 vs Sampling Rate Figure 20. THD, H2, H3 vs Supply Voltage - FIN = 607.77MHz



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Decimation Factor

PowerConsumption(W)

0 4 8 12 16 20 24 28 32

1.6

1.7

1.8

1.9

D014All Supply Voltage Variation from Nominal (%)

PowerConsumption(W)

-10 -5 0 5 101.5

1.6

1.7

1.8

1.9

D039


Magnitude(dBFS)

-50 -25 0 25 50 75 100-50

-60

-70

-80

-90

-100

-

D126

H3 - Foreground at 25C (dBFS)H3 - Background (dBFS)H3 - Foreground at Each Temp (dBFS)


PowerConsumption(W)

1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 52001

1.2

1.4

1.6

1.8

2

D001

Temperature (C)

Magnitude(dBFS)

-50 -25 0 25 50 75 100-100

-90

-80

-70

-60

-

D032



Magnitude(dBFS)

-50 -25 0 25 50 75 100-50

-60

-70

-80

-90

-100

-

D125

H2 - Foreground at 25C (dBFS)H2 - Background (dBFS)H2 - Foreground at Each Temp (dBFS)







Figure 21. THD, H2, H3 vs Temperature - FIN= 607.77MHz Figure 22. H2 vs Temperature and Calibration Mode


Figure 23. H3 vs Temperature and Calibration Mode Figure 24. Power Consumption vs Sampling Rate

DDC bypass modeFIN = 608 MHz

Figure 26. Power Consumption vs Supply VoltageFigure 25. Power Consumption vs Decimation Setting



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Insertion

Loss

(dB)

0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000-15

-12

-9

-6

-3

0

3

D037

Corrected for Setup LossesRaw Insertion LossCurve Fit


SupplyCurrent(A)

-50 -25 0 25 50 75 1000.1

0.2

0.3

0.4

0.5

.

D042

VA19VA12VD12

Decimation Factor

SupplyCurrent(A)

0 4 8 12 16 20 24 28 320.1

0.2

0.3

0.4

0.5

.

D015

VA19

VA12

VD12

All Supply Voltage Variation from Nominal (%)

SupplyCurrent(A)

-10 -5 0 5 100.1

0.2

0.3

0.4

0.5

.

D040

VA19VA12VD12


PowerConsumption(W)

-50 -25 0 25 50 75 1001.6

1.7

1.8

.

D041 Sampling Rate (MSPS)

SupplyCurrent(A)

1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 52000.1

0.2

0.3

0.4

0.5

.

D001

VA19VA12VD12






DDC bypass mode DDC bypass mode FIN= 608 MHz

Fi gu re 27. Po wer Co ns um pt io n v s Tem per at ur e Fi gu re 28. Su pp ly c ur ren t v s Sam pl i ng Rat e

DDC bypass mode Foreground calibration modeForeground calibrationmode

Figure 30. Supply Current vs Supply VoltageFigure 29. Supply Current vs Decimation Setting

DDC bypass mode Foreground calibration mode Foreground calibration mode

Figure 31. Supply Current vs Temperature Figure 32. Insertion Loss vs Input Frequency



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Normalized to Filter Input Sample Rate

Magnitude(dB)

0 0.006 0.012 0.018 0.024 0.03-0.01

-0.0075

-0.005

-0.0025

0

.

D062Normalized to Filter Input Sample Rate

Magnitude(dB)

0 0.1 0.2 0.3 0.4 0.5-180

-150

-120

-90

-60

-30

0

D063

Filter Response-80dB


Magnitude(dB)

0 0.01 0.02 0.03 0.04 0.05-0.01

-0.0075

-0.005

-0.0025

0

.


Magnitude(dB)

0 0.1 0.2 0.3 0.4 0.5-180

-150

-120

-90

-60

-30

0

30

D061



Magnitude(dB)

0 0.01 0.02 0.03 0.04 0.05 0.06-0.01

-0.0075

-0.005

-0.0025

0

.


Magnitude(dB)

0 0.1 0.2 0.3 0.4 0.5-180

-150

-120

-90

-60

-30

0

D059







Figure 39. Decimate by 8 - Passband Response Figure 40. Decimate by 10 - Stopband Response





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Magnitude(dB)

0 0.003 0.006 0.009 0.012 0.015-0.01

-0.0075

-0.005

-0.0025

0

.

D066


Magnitude(dB)

0 0.005 0.01 0.015 0.02 0.025-0.01

-0.0075

-0.005

-0.0025

0

.


Magnitude(dB)

0 0.1 0.2 0.3 0.4 0.5-180

-150

-120

-90

-60

-30

0

D065

Filter Response







Figure 47. Decimate by 32 - Passband Response



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J

ESD204B

Interface

DDC

DDCBypass

ADC

VCM

VCM CLK

VCMO

RBIAS

REF

DEVCLK+

DEVCLK

SYSREF+

SYSREF

SYNC~/TMST+

SYNC~/TMST

SYNC~

SPIInterface

ConfigurationRegisters

OverrangeDetection

OR_T0

OR_T1

SCLKSDI

SDO

RBIAS+

VBG

TDIODE+

TDIODE

Buffer

ClockSync

DS7+/NCO_2

DS7/NCO_2

DS6+/NCO_1

DS6/NCO_1

DS5+/NCO_0

DS5/NCO_0

DS4+

DS4

DS3+

DS3

DS2+

DS2

DS1+

DS1

DS0+

DS0

SCS

VIN+

VIN


7 Detailed Description

7.1 Overview

The ADC12J4000 device is an ultra-wideband sampling and digital tuning subsystem. The device combines avery-wideband and high sampling-rate ADC front-end with a configurable digital-down conversion block. Thiscombination provides the necessary features to facilitate the development of flexible software-defined radioproducts for a wide range of communications applications.

The ADC12J4000 device is based on an ultra high-speed ADC core. The core uses an interleaved calibratedfolding and interpolating architecture that results in very high sampling rate, very good dynamic performance, andrelatively low-power consumption. This ADC core is followed by a configurable DDC block which is implementedon a small geometry CMOS. The DDC block provides a range of decimation settings that allow the product towork in ultra-wideband, wideband, and more-narrow-band receive systems. The output data from the DDC blockis transmitted through a JESD204B-compatible multi-lane serial-output system. This system minimizes thenumber of data pairs required to convey the output data to the downstream processing circuitry.

7.2 Functional Block Diagram



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VIN+50-

ource

VIN1:2 Balun

C(couple)

C(couple)

R(VIN)

VIN+

VIN

VCMO

C(couple)

C(couple)


Feature Descrip tion (continued)

Figure 49. Differential Analog Input Connection

Performance is good in both DC-coupled mode and AC coupled mode, provided the common-mode voltage atthe analog input is within specifications.

7.3.2.1 Input Clamp

The ADC12J4000 maximum DC input voltage is limited to the range 0 to 2 V to prevent damage to the device.To help maintain these limits, an active input clamping circuit is incorporated which sources or sinks inputcurrents up to 50 mA. The clamping circuit is enabled by default and is controlled via the Input_Clamp_EN bit(register 0x034, bit 5). The protection provided by this circuit is limited as follows:

Shunt current-clamping is only effective for non-zero source impedances.

At frequencies above 3 GHz the clamping is ineffective because of the finite turn-on and turn-off time of theswitch.

With these limitations in mind, analysis has been done to determine the allowable input signal levels as afunction of input frequency when the Input Clamp is enabled, assuming the source impedance matches the inputimpedance of the device (100- differential). This information is incorporated in the Absolute Maximum Ratingstable.

7.3.2.2 AC Coupled Input Usage

The easiest way to accomplish SE-to-differential conversion for AC-coupled signals is with an appropriate balun.

Figure 50. Single-Ended-to-Differential Signal Conversion With a Balun

Figure 50shows a generic depiction of a SE-to-differential signal conversion using a balun. The circuitry specificto the balun depends on the type of balun selected and the overall board layout. TI recommends that the systemdesigner contact the manufacturer of the selected balun to aid in designing the best performing single-ended todifferential conversion circuit using that particular balun.

When selecting a balun, understanding the input architecture of the ADC is important. Specific balun parametersmust be considered. The balun must match the impedance of the analog source to the on-chip 100- differentialinput termination of the ADC12J4000 device. The range of this input termination resistor is described in theElectrical Characteristicstable as the specification RID.



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Feature Descrip tion (continued)

Also, as a result of the ADC architecture, the phase and amplitude balance are important. The lowest possiblephase and amplitude imbalance is desired when selecting a balun. The phase imbalance must be no more than2.5 and the amplitude imbalance must be limited to less than 1 dB at the desired input frequency range.

Finally, when selecting a balun, the voltage standing-wave ratio (VSWR), bandwidth, and insertion loss of the

balun must also be considered. The VSWR aids in determining the overall transmission line terminationcapability of the balun when interfacing to the ADC input. The insertion loss must be considered so that thesignal at the balun output is within the specified input range of the ADC as described in the ElectricalCharacteristicstable as the specification VID.

Table 1lists the recommended baluns for specific signal frequency ranges.

Table 1. Balun Recommendations

MINIMUM MAXIMUMIMPEDANCE RATIO PART NUMBER MANUFACTURER

FREQUENCY (MHz) FREQUENCY (MHz)

4.5 3000 1:1 TC1-1-13MA+ Mini-Circuits

400 3000 1:2 B0430J50100AHF Anaren

30 1800 1:2 ADTL2-18+ Mini-Circuits

10 4000 1:2 TCM2-43X+ Mini-Circuits

7.3.2.3 DC Coupled Input Usage

When a DC-coupled signal source is used, the common mode voltage of the applied signal must be within aspecified range (VCMI). To achieve this range, the common mode of the driver should be based on the VCMOoutput provided for this purpose.

Full-scale distortion performance degrades as the input common-mode voltage deviates from VCMO. Therefore,maintaining the input common-mode voltage within the VCMI range is important.

Table 2lists the recommended amplifiers for DC-coupled usage or if AC-coupling with gain is required.

Table 2. Amplifier Recommendations

3-dB BANDWIDTH (MHz) MIN GA IN (dB) MAX GAIN (dB) GAIN TYPE PART NUMBER

7000 16 16 Fixed LMH3401

2800 0 17 Resistor set LMH6554

2400 6 26 Digital programmable LMH6881

900 1.16 38.8 Digital programmable LMH6518

7.3.2.4 Handling Single-Ended Input Signals

The ADC12J4000 device has no provision to adequately process single-ended input signals. The best way tohandle single-ended signals is to convert these signals to balanced differential signals before presenting thesignals to the ADC.

7.3.3 Clocking

The ADC12J4000 device has a differential clock input, DEVCLK+ and DEVCLK, that must be driven with an

AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signalmust be capacitively coupled to the clock pins as shown in Figure 51.



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FSR

tot(J) (n 1)I(PP) IN

V 1RMS

V 2 F

CLK+

CLK

C(couple)

C(couple)


Figure 51. Differential Sample-Clock Connection

The differential sample-clock line pair must have a characteristic impedance of 100 and must be terminated atthe clock source of that 100- characteristic impedance. The input clock line must be as short and direct aspossible. The ADC12J4000 clock input is internally terminated with an untrimmed 100- resistance.

Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can causea change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the rangespecified in the Electrical Characteristics table.

The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J4000device features a duty-cycle clock-correction circuit which maintains performance over temperature. The ADCmeets the performance specification when the input clock high times and low times are maintained as specifiedin theElectrical Characteristics table.

High-speed high-performance ADCs such as the ADC12J4000 device require a very-stable input clock-signalwith minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effectivenumber of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed toprevent a jitter-induced reduction in SNR.

where

RMStot(J)is the RMS total of all jitter sources in seconds

VI(PP)is the peak-to-peak analog input signal

VFSRis the full-scale range of the ADC

n is the ADC resolution in bits

FIN is the maximum input frequency, in Hertz, at the ADC analog input (1)

Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources,including that from the clock source, the jitter added by noise coupling at board level and that added internally bythe ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the

ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of theexternally-added input clock jitter and the jitter added by any circuitry to the analog signal.

Input clock amplitudes above those specified in the Recommended Operating Conditions table can result inincreased input-offset voltage. Increased input-offset voltage causes the converter to produce an output codeother than the expected 2048 when both input pins are at the same potential.



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7.3.4 Over-Range Function

To ensure that system-gain management has the quickest-possible response time, a low-latency configurableover-range function is included. The over-range function works by monitoring the raw 12-bit samples exiting the

ADC module. The upper 8 bits of the magnitude of the ADC data are checked against two programmablethresholds, OVR_T0 and OVR_T1. The following table lists how a raw ADC value is converted to an absolutevalue for a comparison of the thresholds.

ADC SAMPLE ADC SAMPLE UPPER 8 BITS USED FORABSOL UTE VALUE

(OFFSET BINARY) (2's COMPLEMENT) COMPARISON

1111 1111 1111 (4095) 0111 1111 1111 (+2047) 111 1111 1111 (2047) 1111 1111 (255)

1111 1111 0000 (4080) 0111 1111 0000 (+2032) 111 1111 0000 (2032) 1111 1110 (254)

1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0)

0000 0001 0000 (16) 1000 0001 0000 (-2032) 111 1111 0000 (2032) 1111 1110 (254)

0000 0000 0000 (0) 1000 0000 0000 (-2048) 111 1111 1111 (2047) 1111 1111 (255)

If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 threshold during the monitoringperiod, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. Theresulting over-range bits are embedded into the complex output data samples and output on OR_T0 and OR_T1.Table 3lists the outputs, related data samples, threshold settings and the monitoring period equation.

Table 3. Threshold and Monitor Period for Embedded OR Bits

EMBEDDED OVER-RANGE MONITORING PERIODASSOCIATED THRESHOLD ASSOCIATED SAMPLES

OUTPUTS (ADC SAMPLES)

OR_T0 OVR_T0 In-Phase (I) samples2OVR_N(1)

OR_T1 OVR_T1 Quadrature (Q) samples

(1) OVR_N is the monitoring period register setting.

Table 4. Over-Range Monitoring Period

OVR_N MONITORING PERIOD

0 1

1 2

2 43 8

4 16

5 32

6 64

7 128

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold istriggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be setmuch lower. For example, the OVR_T1 threshold can be set to 64 (12 dBFS). If the input signal is strong, theOVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. Thedownstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then thesystem gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is

above12 dBFS).The OR_T0 threshold is embedded as the LSB along with the upper 15 bits of every complex I sample. TheOR_T1 threshold is embedded as the LSB along with the upper 15 bits of every complex Q sample.



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7.3.5 ADC Core Features

7.3.5.1 The Reference Voltage

The reference voltage for the ADC12J4000 device is derived from an internal bandgap reference. A bufferedversion of the reference voltage is available at the VBG pin for user convenience. This output has an output-current capability of 100 A. The VBG output must be buffered if more current is required. No provision exists

for the use of an external reference voltage, but the full-sc

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