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AB26 FET Amplifier

Operating Manual Ver.1.1

An ISO 9001 : 2000 company

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Scientech Technologies Pvt. Ltd. 2

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RoHS Compliance

Scientech Products are RoHS Complied. RoHS Directive concerns with the restrictive use of Hazardous substances (Pb, Cd, Cr, Hg, Br compounds) in electric and electronic equipments. Scientech products are “Lead Free” and “Environment Friendly”. It is mandatory that service engineers use lead free solder wire and use the soldering irons upto (25 W) that reach a temperature of 450°C at the tip as the melting temperature of the unleaded solder is higher than the leaded solder.

AB26 FET Amplifier

Table of Contents

1. Introduction 4 2. Theory 6

3. Experiments

• Experiment 1 10 Study of the Theoretical Analysis of FET Amplifier

• Experiment 2 14 Study of and Measure the Frequency Response of FET Amplifier

• Experiment 3 17 To Measure Various Parameters of FET Amplifier and compare it theoretically

• Experiment 4 20 To observe the output of FET Amplifier in ohmic and Cutoff Region

4. Data Sheet 22 5. Warranty 24

6. List of Accessories 24 7. Result 25

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Introduction AB26 is a compact, ready to use FET Amplifier experiment board. This board is useful for students to understand the working and operation of FET amplifier. It can be used as stand alone unit with external DC power supply or can be used with Scientech Analog Lab ST2612, which has built in DC power supply, AC power supply, function generator, modulation generator, continuity tester, toggle switches, and potentiometer.

List of Boards : Model Name AB01 Diode characteristics (Si, Zener, LED) AB02 Transistor characteristics (CB NPN) AB03 Transistor characteristics (CB PNP) AB04 Transistor characteristics (CE NPN) AB05 Transistor characteristics (CE PNP) AB06 Transistor characteristics (CC NPN) AB07 Transistor characteristics (CC PNP) AB08 FET characteristics AB09 Rectifier Circuits AB10 Wheatstone bridge AB11 Maxwell’s Bridge AB12 De Sauty’s Bridge AB13 Schering Bridge AB14 Darlington Pair AB15 Common Emitter Amplifier AB16 Common Collector Amplifier AB17 Common Base Amplifier AB18 RC-Coupled Amplifier AB19 Cascode Amplifier AB20 Direct Coupled Amplifier AB21 Class A Amplifier AB22 Class B Amplifier (push pull emitter follower) AB23 Class C Tuned Amplifier AB24 Transformer Coupled Amplifier AB25 Phase Locked Loop (FM Demodulator & Frequency Divider / Multiplier) AB27 Voltage Controlled Oscillator AB28 Multivibrator (Monostable / Astable) AB29 F-V and V-F Converter AB30 V-I and I-V Converter AB31 Zener Voltage Regulator AB32 Transistor Series Voltage Regulator AB33 Transistor Shunt Voltage Regulator AB35 DC Ammeter AB37 DC Ammeter (0-2mA) AB39 Instrumentation Amplifier

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AB41 Differential Amplifier (Transistorized) AB42 Operational Amplifier (Inverting / Non-inverting / Differentiator) AB43 Operational Amplifier (Adder/Scalar) AB44 Operational Amplifier (Integrator/ Differentiator) AB45 Schmitt Trigger and Comparator AB49 K Derived Filter AB51 Active filters (Low Pass and High Pass) AB52 Active Band Pass Filter AB54 Tschebyscheff Filter AB56 Fiber Optic Analog Link AB57 Owen’s Bridge AB58 Anderson’s Bridge AB59 Maxwell’s Inductance Bridge AB64 RC – Coupled Amplifier with Feedback AB66 Wien Bridge Oscillators AB67 Colpitt Oscillator AB68 Hartley Oscillator AB80 RLC Series and RLC Parallel Resonance AB82 Thevenin’s and Maximum Power Transfer Theorem AB83 Reciprocity and Superposition Theorem AB84 Tellegen’s Theorem AB85 Norton’s theorem AB88 Diode Clipper AB89 Diode Clampers AB90 Two port network parameter AB91 Optical Transducer (Photovoltaic cell) AB92 Optical Transducer (Photoconductive cell/LDR) AB93 Optical Transducer (Phototransistor) AB96 Temperature Transducer (RTD & IC335) AB97 Temperature Transducer (Thermocouple) AB101 DSB Modulator and Demodulator AB102 SSB Modulator and Demodulator AB106 FM Modulator and Demodulator

and many more…………

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Theory Fundamentally an amplifier is a device that takes in a low power signal and outputs a magnified (power boosted) version of the input signal. In an analog amplifier using FET ,the signal is applied to the gate terminal of the FET and this causes a proportional output drive current to flow out of the output terminal. The output drive current is obtained from the power supply. The voltage signal at the output is thus a larger version of the input, but has been changed in sign (inverted) by the amplification.

The field effect transistor (FET) is a three terminal device used for the purpose of amplification, chopping, commutating, switching and multiplexing. The primary difference between the bipolar junction transistor (BJT) and field effect transistor (FET) is that the BJT is a current controlled device while FET is voltage controlled device.That is in BJT output current is a function of input current while in FET,output current is a function of input voltage.Also Bjt is a bipolar device (i.e. conduction level is a function of two charge carriers, holes and electrons) and FET is an unipolar device(i.e. conduction level is a function of only single charge carriers, either holes or electrons). The term field effct in FET resembles it’s working with that of a permanent magnet.The magnetic field of permanent magnet has ability to draw metal fillings towards it self through magnetic flux lines without actual contact between them.In FET,electric field is established by charges present that will control the conduction path of output circuit without the need for direct contact between controlling (input voltage) and controlled (output current)quantity. Before knowing how FET amplifier in our experiment works ,we must know some detail about it’s construction. Like BJT, FET is also of two types 1. n-channel FET

2. p-chaneel FET The terms n-channel and p- channel refer to the material with which the drain and source are connected. A simplified n-channel JFET construction is shown below in figure 1. Shown in figure1 that the drain and source connections are made to the n-channel and the gate is connected to the p material.

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P PNGate

P-type Semiconductors

N-type Channel

Drain

Source

JFET with n type material Figure 1

An n-type channel is formed between two p-type layers which are connected to the gate. Majority carrier electrons flow from the source and exit the drain, forming the drain current. The pn junction is reverse biased during normal operation, and increasing the reverse bias widens the depletion layers which extend into the n channel only (since the doping of the p regions is much larger than that of the n channel). As the depletion layers widen, the channel narrows, restricting current flow. Figure 1 illustrates a JFET with the two gate areas electrically connected together, as are the source and the drain. Application of forward bias voltage at drain-source terminal and zero bias or reverse bias voltage on the gate-source terminals results in the formation of depletion regions at the PN junction as shown in figure 2. Increasing the voltage causes the depletion regions to reach further into the channel and effectively reduces its cross-sectional area. Depletion region formed increases as the reverse gate source voltage is increased. This depletion region, being devoid of majority carriers, reduces the channel drain-source current.

P P

N

Gate

Wide Depletion Region with larger VoltageVGS

Drain

Source

VDS

VGS

CurrentFlow

+

I = 0G

N-type JFET with depletion layer

Figure 2

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As a result, the drain-source current is controlled by the gate voltage. A typical JFET characteristic curve is given below in figure 3; which indicates the effect of the gate-source voltage on the drain-source current, IDS. As the gate-source voltage is increased, the drain-source current increases. When VGS = 0 and VDS is increased then at certain value of VDS drain current becomes almost constant as shown in figure 3.This value of VDS is called as pinch off voltage VP and constant value of current as saturation current IDSS (drain to source current with gate short with source). As VGS is decreased the saturation current also decreases, at VGS = -VP gate to source voltage becomes sufficiently negative to establish a current level of 0 mA, and turns off.

Transfer & Drain Characteristics for n type JFET

Figure 3 The relationship between ID (output current) and VGS (input voltage) is nonlinear and defined by Shockley’s equation:

ID = IDSS (1-VGS/VP) 2 (1) Where

IDSS and VP are constants and VGS is control variables. The curve plotted between ID and VGS is known as transfer curve shown in figure 3. It is same as transconductance curve of BJT. It shows that when VGS = 0, ID = IDSS and when ID = 0, VGS = VP .The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is employed.

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Ohmic and Cutoff region : As shown in figure 3 the region of operation of JFET before pinch off value of drain to source voltage VDS is called ohmic region as drain current increases with the increase in drain to source voltage VDS. This region is responsible for broadening of lower half of input sine wave signal as resistance becomes almost constant in ohmic region, amplification of lower half of signal stops but upper half of signal still amplifies before reaching to cut off region. The cutoff region is defined as the region at which gate to source voltage VGS becomes equal to pinch off voltage i.e. -VGS = VP. At this value of gate to source voltage, drain current almost drops to zero and drain to source voltage reaches near to input bias voltage i.e. Q point of JFET shifts and hence swing of input sinusoidal signal clips off from top.

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Experiment 1 Objective : Study of the Theoretical Analysis of FET Amplifier Calculations and Analysis : DC Analysis of Voltage divider bias configuration : In our experiment we have used voltage divider bias configuration due to its stability. How theoretical analysis of this configuration is done is given in following section. In experiment 3 we will compare these results with the results obtained practically.

+12V

20MR1

Cc

Rs200E

R22M7

InputSignal

G

D

S

0.47uF

22uFCS

e RL10K

C0.01uF

G

RD1K

SignalOutput

FET J211

VG

ID

VDSQ

VGSQ

Circuit diagram of FET amplifier

Figure 4 In circuit diagram of FET amplifier as shown in figure 4 we have used FET J211. It’s specification as per data sheet are as follows. VGS (off) = - VP = 2.45 volts

IDSS = 8.6 mA YOS (common source output conductance) = 200 uS or

rd =1/ YOS = 5K (required in gain calculation). Now with these constant values we start our DC analysis as

We have R1= 20M, R2 = 2.7M, RD = 1K, RS = 0.2K, RL = 10K

CG=0.01MFD, CS = 22MFD, CC = 0.47MFD VG= (VDD X R2)/(R1+R2)

= (12V X 2.7M)/ (20M+2.7M) = 1.43V

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Now we have IDQ = IDSS (1-VGS/VP) 2 (1)

Also we have VGSQ = VGQ - VSQ

VGSQ = 1.43 - ISRS

But in JFET IS = ID because IG = 0

So VGSQ = 1.43 – IDQ X 0.2K (2) Putting in Equation1 we get

IDQ = 8.6mA {1-(1.43 – ID X 0.2K)/(- 2.45V)}2 Solving for ID we get quadratic equation as

0.056 I2DQ - 3.20 IDQ + 21.5 = 0

I2DQ – 57.14 IDQ + 383.93 = 0

Solution of above equation yields

IDQ1= 7.78 mA IDQ2= 49.36 mA (impossible because IDQ2 can not be greater than IDSS )

Value of VGSQ (from equation 2) :

VGSQ = - 0.126Volts (for IDQ= 7.94 mA) We also have

VD = 12 – IDQ X RD VD = 12 – 7.78 mA X 1K

VD = 4.22V And VS = IDQ X RS

VS = 1.556 V Hence

VDSQ = VD –Vs

VDSQ = 4.22 – 1.556 V

VDSQ = 2.66 V Note that this value of VDSQ is not for VGSQ = 0 but for VGSQ = 0.158 volts.

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Gain calculation : We have

gmo (transconductance at VGS = 0) = 2 X IDSS / VP = 2 X 8.6 mA / 2.45 V

= 7.02mS

Also gm(at other value of VGSQ) = gm0 (1- VGSQ /VP)

gm = 7.02 (1 – (- 0.126 V/-2.45) = 7.02 X (1- 0.051)

gm = 6.66 mS Hence

Gain (AV) = gm X (RD || RL || rD) = 6.66 X (1K||10K ||5K)

Gain (AV) = 5.1 (approximately) Lower cutoff frequency calculations : Cutoff frequency with input coupling capacitor CG fLG = 1/{2 X ∏ X (Rsig + Ri) X CG} (3)

Where Rsig = 50 ohm (output resistance of function generator )

Ri = R1 X R2/( R1 + R2) Ri = 20M X 2.7M/20M + 2.7M

Ri = 2.37M So Rsig + Ri = Ri (Rsig neglected)

Also CG = 0.01 MFD So we have from Eq (3)

fLG = 6 Hz.

Again

Cutoff frequency with output coupling capacitor CC. fLC = 1/{2 X ∏ X (RO + RL) X CC} (4)

Where RO = RD || rd

RO = 1K || 5K RO = 0.83 K

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Also CG = 0.47 MFD So we have from Eq (4)

fLC = 31.28 Hz Cutoff frequency with bypass capacitor Cs.

fLS= 1/{2 X ∏ X (Req) X CC (5) Where

Req = RS / [1+ {RD (1+ gm X rd)}/ (rd + RD || RL) ] Req= 0.10K

Also CS = 22 MFD So we have from Eq (4)

fLC = 72.37 Hz Since fLC is the largest of three cutoff frequencies, it defines the low cutoff frequency for the network shown in figure 4

Note : Above parameters are calculated by considering specific value of various parameters of JFET. The value of these parameters is different in each JFET and hence the difference in error of all parameters may vary accordingly. Higher cutoff frequency can not be calculated because of variation in wiring capacitances due to transportation and other reasons. Hence it is calculated practically.

Result : The theoretical value of various parameters has been determined which are as follows. 1. VDSQ = 2.66 V

2. VGSQ = 0.126 volts 3. IDQ1= 7.78 mA

4. AV = 5.1 (approximately) 5. gm = 6.66 mS

6. fLC (lower cutoff frequency ) = 72.37 Hz

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Experiment 2 Objective : To study and Measure the Frequency Response of FET Amplifier Equipments Needed : 1. Analog board, AB26 2. DC power supply +12V from external source or ST2612 Analog Lab.

3. Function Generator. 4. Oscilloscope.

5. 2mm patch cords.

Circuit diagram : Circuit used to study the frequency response of FET amplifier is shown in figure 5 below :

Figure 5

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Procedure : 1. Connect +12V variable DC power supply at the indicated position from external

source or ST2612 Analog Lab. 2. Switch ‘On’ the power supply. 3. Connect maximum 200 mVp-p, 50 Hz sine wave signal at the signal input of

AB26 board and observe the same on oscilloscope CH I. 4. Connect socket ‘a’ with socket ‘b’. 5. Observe the output waveform from “output signal” on oscilloscope CHI or CH

II and note down output voltage (VOUT) peak to peak. 6. Vary the frequency of input signal from function generator with a margin of 100

Hz initially. After 1 KHz vary the frequency with a margin of 1 KHz. 7. After 10 KHz, vary the frequency of input signal with a margin of 10 KHz.

After 100 KHz vary the frequency with a margin of 100 KHz till output does not become equal to input.

8. Note down the output voltage corresponding the input frequency in the observation table given below.

9. Calculate the voltage gain of amplifier at each frequency by the formula given Voltage gain AV = VOUT (peak to peak) / VIN (peak to peak)

10. Find out the value of gain in db by formula Gain (in db) =20 log (AV)

11. Plot the graph between gain (in db) and frequency (in Hz) on log paper and calculate the bandwidth given by equation :

Bandwidth = (fH – fL ) Where

fL = lower 3dB cutoff frequency

fH = higher 3dB cutoff frequency

12. Observe the output waveform from “output signal” on oscilloscope CH I or CH II for the different values of input voltages less than 200 mVp-p.

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Observation Table : For input voltage VIN :

S. No. Input signal frequency

(KHz)

Output voltage (VOUT )

Gain (AV=VOUT /VIN )

Gain (db) 20 log (AV)

Result : fL (lower 3dB cutoff frequency) = ……………………

fH (higher 3dB cutoff frequency) = ……………………

Bandwidth (fH – fL) = ……………………

Conclusion : The Bandwidth of FET Amplifier is found to be …...

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Experiment 3 Objective : To Measure Various Parameters of FET Amplifier and compare it theoretically Equipments Needed : 1. Analog board, AB26. 2. DC power supply +12V from external source or ST2612 Analog Lab. 3. Function Generator. 4. Oscilloscope. 5. 2mm patch cords. 6. Digital Multimeter.

Circuit diagram : Circuit used to measure various parameters of FET amplifier and compare it theoretically.

Figure 6

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source or ST2612 Analog Lab. 2. Switch ‘On’ the power supply. 3. Connect maximum 200 mVp-p, 10 KHz sine wave signal at the signal input of

AB26 board and observe the same on oscilloscope CH I. 4. Connect socket ‘a’ with socket ‘b’. 5. Observe the output waveform from “output signal” on oscilloscope CHI or CH

II and note down output voltage (VOUT) peak to peak 6. Note down the value of gain (AV=VOUT /VIN) in the observation table given

below. 7. Pull out patch cord from socket ‘a’ and ‘b' and insert red probe of multimeter in

socket ‘a’ and black probe in socket ‘b’ and position its dial at DC current measurement.

8. Note down the value of drain current IDQ in the observation table given below. 9. Again connect socket ‘a’ with socket ‘b’. Now keep red probe of multimeter at

test point ‘d’ and black probe at test point ‘e’ and position multimeter dial at DC voltage measurement

10. Note down the value of gate–source voltage VGSQ in the observation table given below. Mark that the value of VGS is negative.

11. Again keep red probe of multimeter at test point ‘c’ and black probe at test point ‘e’ and position multimeter dial at DC voltage measurement

12. Note down the value of drain–source voltage VDSQ in the observation table given below.

13. Compare it with the value calculated theoretically. 14. Calculate the error value given by the formula :

Error in value = Theoretical value – Practical value

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Observation Table :

S. No. Parameter Theoretical Value Practical Value Error in value (Th

Val. –Pr.Val)

1 IDQ

2 VGSQ

3 VDSQ

4 AV

Result : Error in value of IDQ = …………………

Error in value of VGSQ = …………………… Error in value of VDSQ = …………………….

Error in value of A = …………………….

Conclusion : The various parameters of FET amplifier have been calculated theoretically and practically.

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Experiment 4 Objective : To observe the output of FET amplifier in ohmic and cutoff region Equipments Needed : 1. Analog board, AB26 2. DC power supply +12V from external source or ST2612 Analog Lab.

3. Function Generator. 4. Oscilloscope.

5. 2mm patch cords.

Circuit diagram : Circuit used to observe the output of FET amplifier in saturation and cutoff region is shown below :

Figure 7

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source or ST2612 Analog Lab. 2. Switch ‘On’ the power supply. 3. Connect 200 mVp-p, 10KHz sine wave signal at the signal input of AB26 board

and observe the same on oscilloscope CH I. 4. Connect socket ‘a’ with socket ‘b’. 5. Observe the output waveform from “output signal” on oscilloscope CHI or CH

II and note down output voltage (VOUT) peak to peak. 6. Vary the amplitude of input signal from function generator. 7. Observe the output on CRO. 8. Note down the value of input voltage at which the lower half of signal starts

distorting i.e. it starts widening. The signal is in ohmic region. 9. Also note down the value of input voltage at which the upper half of signal

starts distorting i.e. it starts flattening. The signal is in cutoff region.

Observation Table :

S. No. Region Input Signal Voltage

1 Cutoff 2 Ohmic

Result : The value of input signal voltage in

Cutoff region = ……….. Ohmic region = ……….

Conclusion : The behavior of output signal of FET amplifier in ohmic and cutoff region has been observed. On CRO.

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Data Sheet

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Warranty 1. We guarantee the product against all manufacturing defects for 24 months from

the date of sale by us or through our dealers. Consumables like dry cell etc. are not covered under warranty.

2. The guarantee will become void, if

a) The product is not operated as per the instruction given in the operating manual.

b) The agreed payment terms and other conditions of sale are not followed.

c) The customer resells the instrument to another party. d) Any attempt is made to service and modify the instrument.

3. The non-working of the product is to be communicated to us immediately giving full details of the complaints and defects noticed specifically mentioning the type, serial number of the product and date of purchase etc.

4. The repair work will be carried out, provided the product is dispatched securely packed and insured. The transportation charges shall be borne by the customer.

For any Technical Problem Please Contact us at [email protected]

List of Accessories

1. 2 mm Patch Cords (Red) ...................................................................... 3 Nos. 2. 2 mm Patch Cord (Blue) .........................................................................1 No. 3. 2 mm Patch Cord (Black) ..................................................................... 3 Nos. 4. e-Manual.................................................................................................1 No.

Updated 18-02-2009

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Note : Teachers are requested to take out the result pages from manual for verifying result obtained by students.

Result Input Experiment 2 Frequency Response of FET Amplifier.

Keep input signal voltage maximum at=200mVp-p and input signal frequency = 50Hz With variation in frequency output increases initially then Experiment 3 Calculate various parameters of FET Amplifier Keep input signal voltage maximum at = 200 Vp-p

Output becomes constant (with in some limit) and then it decreases. Output at certain frequency are : At 100Hz = 750mvolts (sinusoidal)

Vary the Frequency with margin of 1KHz

At 5KHz = 950mvolts (sinusoidal) At 50KHz = 950mvolts (sinusoidal) At 1MHz = 750mvolts (sinusoidal) and input signal frequency = 10KHz VDSQ = 2.70+ 0.40 V

VGSQ = 0.125 +0.05 volts IDQ1= 7.75 + 0.30 m

Experiment 4 Observe the output of FET amplifier in ohmic and cutoff region. Keep input signal voltage maximum at = 200m Vp-p and input signal frequency = 10 KHz

Increase the amplitude of input signal.

With variation in amplitude output should distortes in upper and lower region.

In upper part it starts flattening and in lower part it starts broadening

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