FET Amplifier Design

Microelectronic Circuits, 7th Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

FET Amplifier Design

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Characterizing Amplifiers

iv v

vA 0≡

sigv v

vG 0≡

Amplifier Gain:

Overall Voltage Gain:


Three Basic MOSFET Amplifier Configurations


The Common-Source Amplifier

)||)(( 00 rRvgv Dgsm−=

)||( 00 rRgA Dmv −=


Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.


The CS amplifier with a source resistance Rs: (a) Circuit without bias details; (b) Equivalent circuit with the MOSFET represented by its T model.

sm

Dmv Rg

RgA

+−=

10

Sm

LDmv

sm

LDv

RgRRgA

Rg

RRA

+−=

+−=

1)||(

1||

0

0

The Common-Source Amplifier with a source resistance


Figure 7.39 (a) Common-gate (CG) amplifier with bias arrangement omitted. (b) Equivalent circuit of the CG amplifier with the MOSFET replaced with its T model.

The Common-Gate (CG) Amplifier

Dmi

v RgvvA == 0

0


Figure 7.41 Illustrating the need for a unity-gain buffer amplifier.

The Common-Drain Amplifier or Source Follower


The Common-Drain Amplifier or Source Follower

mL

L

iv

gR

RvvA 1

00

+==

1, 0 =∞= vL AR

mgR 1

0 =


The Source Follower

mo

mLLiov

gRgRRvvA

/1)/1/(/

=+==

Summary and Comparison


Biasing in MOS Amplifier



Figure 7.47 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among

units of the same type.

Biasing by Fixing VGS


Figure 7.48 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b) reduced

variability in ID

Biasing by Fixing VG and Connecting of Resistance in the Source

DSGSG IRVV +=


Figure 7.48 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation

using two supplies.

Biasing by Fixing VG and Connecting of Resistance in the Source


Example 7.11Design to have ID=0.5mA, Vt=1V, kn=1mA/V2

VOV=1V

VGS=VOV+Vt=2V

VG=VGS+VS=7V

VG=7V, R1=8M, R2=7M


Example 7.11What is new ID if Vt=1.5V, kn=1mA/V2

ID=1/2(1)(VGS-1.5)2

VG=VGS+10ID=7V

Solve, ID=0.455mA

Change from 0.5mA to 0.455mA(-9% for Vt increases from 1V to 1.5V)


Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

DDGSDD

DDDDDSGS

IRVVIRVVV

+=−==


(a) Biasing the MOSFET using a constant-current source. (b) Implementation of the constant-current source using a current mirror.

Biasing Using a Constant-Current Source

21

'1 )()(

21

tGSnREFD VVL

WkII −==

22

'2 )()(

21

tGSnD VVL

WkII −==

RVVVII GSSSDD

REFD−+

==1

1

22)/()/(

LWLWII REFD =

Current Mirror Circuit


Basic structure of the circuit used to realize single-stage, discrete-circuit MOS amplifier configurations.

Basic Structure

Discrete-Circuit MOS Amplifier

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.(a) Common-source amplifier based on the circuit of Fig. 5.56. (b) Equivalent circuit of

the amplifier for small-signal analysis.

Common Source (CS) Amplifier

Gin RR =)||||( 0rRRg

RRR

G LDmsigG

Gv +

−=


Common Source (CS) Amplifier with Resistance Rs

(a) Common-source amplifier with a resistance

RS in the source lead


(b) Small-signal equivalent circuit with ro neglected.

Common Source (CS) Amplifier with Resistance Rs


CG amplifier

Common Gate (CG) Amplifier

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.(a) A source-follower amplifier. (b) Small-

signal, equivalent-circuit model.

The Source Follower

mL

L

sigG

Gv

grR

rRRR

RG

1)||(

||

0

0

++=


Figure 5.61 A sketch of the frequency response of a CS amplifier delineating the three frequency bands of interest.

BW=fH-fL

GB=|AM|BW


Figure 5.62 Small-signal, equivalent-circuit model of a MOSFET in which the source is not connected to the body.

The role of the Substrate – The Body Effect


Figure 13.17 The CMOS inverter.

The Inverter


Figure 13.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.


Figure 13.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through

QN.

FET Amplifier Design

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