Experiment EB1: FET Amplifier Frequency Response - …foe.mmu.edu.my/lab/lab...

EEE1026 Electronics II Experiment EB

Experiment EB1: FET Amplifier Frequency Response

Learning Outcome

LO1: Explain the principles and operation of amplifiers and switching circuits.

LO2: Analyse low and high frequency response of amplifiers.

LO4: Analyze the operation of JFET, MOSFET and BJT amplifiers and switching

circuits

1.0 Apparatus

Equipment required Components required Power Supply – 1 N-channel JFET 2N5457 – 1

Oscilloscope – 1 Resistor 10k (1/4W) – 2

Digital Multimeter – 1 Resistor 3.3k (1/4W) – 1

Breadboard – 1 Resistor 3.9k (1/4W) – 1

Function Generator – 1 Resistor 22k (1/4W) – 1

Mylar Capacitor 0.47F – 2



50 k potentiometer -- 1

Objectives:

1. Construct and test a voltage amplifier using N-channel JFET device in a common source

configuration

2. Apply the voltage divider biasing method to set the DC operating point (VGSq ,IDSq) .

Verify the estimated DC operating point with the measured data.

3. Investigate the effect of frequency changes on the voltage gain of the amplifier, measure

its frequency response and obtain its operating bandwidth.

4. Investigate the capacitance effect on the frequency response of the common source JFET

amplifier

Important Notes

All related calculation questions that does not require experimental data must be

answered before coming to the lab. You are required to show all the calculation steps when

requested by the lab instructor. During the evaluation session, your lab instructor may request

you to demonstrate how the measurement data is obtained and explain your experimental

results.

Report Submission

You must obtain the signature of the Instructor after completing each section of

the experiment. Submit your report to the Lab Supervisor, latest by 5.00pm the next day, after

the experiment.


2.0 Background Theory

An amplifier is a circuit that increases/decrease the input signal value and in this experiment

the signal to be amplified is the voltage. In this experiment you are going to investigate

frequency response characteristic of a voltage amplifier circuit using the N-channel JFET

device

Most amplifiers have relatively constant gain over a certain range of frequencies. This range

of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier

depends on the circuit component values, the type of active components and the dc operating

point of the active component. When an amplifier is operated within its bandwidth, the

current gain iA , voltage gain vA , and power gain pA values are referred to as midband

gain values. A simplified frequency-response curve that represents the relationship between

amplifier gain and operating frequency is shown in Figure 1.

Figure 1: A simplified frequency response curve

As the frequency-response curve shows, the power gain of an amplifier remains

relatively constant across a band of frequencies. When the operating frequency starts to go

outside this frequency range, the gain begins to drop. Two frequencies of interest, 1cf and 2cf

, are the frequencies at which power gain decreases to approximately 50% of )(midpA . The

frequencies labeled 1cf and 2cf are called the lower and upper cutoff frequencies of an

amplifier, respectively. These frequencies are considered to be the bandwidth limits for the

amplifier and thus bandwidth BW is given by

12 cc ffBW .

The geometric average of 1cf and 2cf is called the geometric center frequency foof an

amplifier, given by

210 cc fff .

When the operating frequency is equal to 0f , the power gain of the amplifier is at its

maximum value.

Frequency response curves and specification sheets often list gain values that are

measured in decibels (dB). The dB power gain of an amplifier is given by

Apdrops at

lowerfrequencies Apdrops at higher

frequencies

fc1 fc2

Bandwidth 0.5Ap(mid)

Ap(mid)

Frequency

Power Gain Mid-band


in

outpdBp

P

PAA log10log10)( .

Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A

+3dB gain caused power to double while a –3dB gain caused power to be cut in half.

Using the basic power relationships, L

out

outR

vP

2

and in

inin

R

vP

2

, the power gain may be

rewritten as

inin

Lout

in

out

dBpRv

Rv

P

PA

2

2

)( log10log10 L

in

in

out

R

R

v

vlog10log20

The voltage component of the equation is referred to as dB voltage gain. When the amplifier

input and out resistances are equal

)()( log20 dBvin

outdBp A

v

vA . (

Lin RR )

Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the amplifier

also changes by –3dB.

Low Frequency Response of FET Amplifier

In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the

RC combinations formed by the network capacitors and the network resistive parameters that

determine the cutoff frequency. There are three capacitors – two coupling capacitor GC and

DC , and one bypass capacitor, SC . Let us assume that GC , DC and SC are arbitrarily large

and can be represented by short-circuit. The total resistance in series with GC is given by

inGCG RRR

where 21 || RRRin is the input impedance of the amplifier circuit. The power supplied by the

signal generator is )/(2

inGgenin RRVP . However, the reactance XCG of capacitance GC is not

negligible at very low frequencies. The frequency at which Pin is cut in half is when

inGCG RRX . Thus the lower half-power point for gate circuit occurs at frequency

GinGGCG

LGCRRCR

f

2

1

2

1

Figure 2(a): Schematic diagram of a JFET amplifier

R1 RS

R2

RL

RD CD

CS

CG RG

+VDD

Vgen

D

S

G

Vin


Figure 2(b): JFET amplifier low-frequency ac equivalent circuit

Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of

the JFET drain terminal, rd, is much larger than RD).

When GC and SC are arbitrarily large and can be represented by short-circuit, the drain

circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also

be represented by a short-circuit, the output power to load resistor RLisLDout RVP /2 . At low

frequencies where the reactance XCD of capacitance DC is not negligible, Pout is cut in half

when LCD RX . Thus the lower half-power point for drain circuit occurs at frequency

DL

LDCR

f2

1

At the half-power point, the output voltage reduces to 0.707 times its midband value. The

actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD

(determined by CD).

High Frequency Response of FET Amplifier

The high frequency response of the FET is limited by values of internal capacitance,

as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal

pair of the FET. These capacitances each have a reactance that decreases as frequency

increases. As the reactance of a given terminal capacitance decreases, more and more of the

signal at the terminal is bypassed through the capacitance.

R1||R2 RS

RL RD

CD

CS

CG RG

Vgen

VG D

S

G

Vin

RL RD

CD

gmVgs

D

S

VD


Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency

response.

Figure 3(b): FET amplifier high frequency ac equivalent circuit.

The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure

3(b), including all the terminal capacitance values. gdC is replaced with the Miller equivalent

input and output capacitance values given as

1)( vgdMin ACC and v

vgdMout

A

ACC

1)(

Figure 4: Miller equivalent circuit for a feedback capacitor.

R1||R2

Cout(M)

RG

Vgen Cin(M) Cgs

Cds CL RL||RD

R1 RS

R2

RL

RD CD

CS

CG RG

Cgd

Cgs

Cds

Vgen

+VDD

CL

AV

Cgd

AV

Cin(M) G D

G D

Cout(M)


Note the absence of capacitorsGC , DC and SC in Figure 3(b), which are all assumed to be

short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are

given by

)(MingsG CCC and LdsMoutD CCCC )(

where LC is the input capacitance of the following stage. In general the capacitance gsC is

the largest of the parasitic capacitances, with dsC the smallest. The high cutoff frequencies

for the gate and drain circuits are then given by

Gin

HGCR

f

2

1 and

DL

HDCR

f

'2

1

where inGin RRR || and LDL RRR ||' . At very high frequencies, the effect of GC is to

reduce the total impedance of the parallel combination of 1R , 2R and GC in Figure 3(b). The

result is a reduced level of voltage across the gate-source terminals. Similarly, for the drain

circuit, the capacitive reactance of DC will decrease with frequency and consequently

reduces the total impedance of the output parallel branches of Figure 3(b). It causes the

output voltage to decrease as the reactance becomes smaller.

3.0 Procedures

1. Before connecting the circuit of Figure 5, write down the resistance values and the

tolerance using the color code scheme and then measure the actual resistance of R1, R2,

RD, RS and RL as accurate as possible with a digital multimeter (set it to the best resistance

range) and record the measured values.

2. Connect the common source JFET amplifier circuit as shown in Figure 5 using a

breadboard (refer to Appendix B). Do not connect the power supply and the function

generator to the circuit yet. Keep the connecting wires on the breadboard as short as

possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit. 3. Set the power supply output to +12V. Connect its output to the circuit and measure its

voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC

voltage VG(cal) using the voltage-divider rule.

4. Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as

possible. Note that the measured VG should be closed to the calculated VG(cal), and VS

should be >VG since VGS must be < 0 V for N-channel JFET.

5. Before connecting the function generator to the circuit, use an oscilloscope to

measure the output voltage of the generator and set it to 200 kHz sine-wave with a

peak-to-peakvoltage of 0.1V. Press the attenuation button (ATT) of the generator for

easy adjustment of its output voltage.

6. Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope

(set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the

oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the

oscilloscope to CH2. Adjust the trigger level on the oscilloscope to obtain stable

waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the

calibrated (CAL’D) positions.


Figure 5: A Common source JFET amplifier

7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope

screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and

the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used.

Note that the input and output waveforms should be approximately 180o out of

phase. 8. From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages ofvL and

vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200

kHz.Ask the instructor to check all of your results. You must show the oscilloscope

waveforms to the instructor. 9. Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller

frequency steps near the half-power point while larger steps can be used at mid-band

frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate

the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of

the function generator for frequency adjustment.

10. Plot a curve of Av versus frequency.

11. Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the

frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator

frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value

in the mid-band.

12. Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the

generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).

13. Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier

from the above measurements. Ask the instructor to check all of your results. You

must show the oscilloscope waveforms at 550 kHz to the instructor. 14. Design or modify the circuit in Figure 5 in order to measure the parameter of the device,

namely Gate-Source Cutoff Voltage (VGS(off) or Vp) and Zero-Gate Voltage Current (IDSS).

These two values can be used in the Shockley equation ID = IDSS(1 – VGS/Vp)2 . Hint: You

can use a potentiometer and/or negative power source in the circuit. By solving the

simultaneous equation of the Shockley equation and the load line equation, you can

+VDD=12V

R1=22k

CG=0.47F

50

Vgen R2 =10k

RD=3.3k

CD=0.01F

CS=0.47F

RL=10k

RS=3.9k

Function Generator

G

D

S

0.1F

CH2

(vL)

CH1

(vin)

D

S G


obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the

measured value.

APPENDIX A

Log Scale The distance in a decade of the log scale in the figure below is x mm. Since log101 = 0, it is

used as a refernce point (0 mm) in the linear scale. Then, the reading 10 is located at x mm

and the reading 0.1 is located at –x mm. For a reading F, it is located at [1og10(F)]*x mm.

E.g.:

Reading 0.25 is located at [1og10(0.25)]*x mm = -0.602x mm

Reading 2.5 is loacted at [1og10(2.5)]*x mm = 0.398x mm

Reading 25 is located at [1og10(25)]*x mm = 1.398x mm (not shown in the figure)

Reading 250 is located at [1og10(250)]*x mm = 2.398x mm (not shown)

Conversely, a point at z mm location is read as xz /10 .

E.g.:

-0.3x mm is read as 10(-0.3x/x)

= 0.501

0.6x mm is read as 10(0.6x/x)

= 3.98


= 31.6 (not shown)


= 501 (not shown)

9 0.1 0.2 0.3 0.5 1 2 3 5 10

-x 0 x

Linear scale

(mm)

Log scale

(unit)

0.25 2.5

0.398x -0.602x 0.6x

3.98 0.501

-0.3x

0.4 0.6 0.7

0.8 0.9

4 6 7 8

The Resistor color code chart

ABC

AB x 10C pF

.abc

0.abcF

Capacitance

Potentiometer

A Var B


Appendix B: Breadboard Internal Connections

General mistakes: The legs of the resistors and the transistor are shorted

by the breadboard internal connections.

MultimediaUniversity FOE

EEE1026 Electronics II

Experiment EB1: FET Amplifier Frequency Response Lab Report

(Submit your report on the same day immediately after the experiment)

Name: ________________________Student ID.: _______________Date: _____________

Majoring: ____________________ Group: ____________ Table No.: ____________

1. Table E1: Resistance values

1R 2R DR SR LR

Value (color code)

Tolerance

Measured

[7.5 marks]

3. VDD(meas) = ________ V, VG(cal) = ________ V [2 marks]

4. Table E3: Measured DC voltages

GV DV SV

[3 marks]

7. Graph E1: vin and vL waveforms at 200 kHz

Time base : ______ s/div, CH1 (vin) : ______ V/div, CH2 (vL) : ______ V/div

[5 marks]

8. )(

)(

ppin

ppL

vV

VA ________ at 200 kHz [0.5 mark]

CH1 & CH2

ground

EEE1026 Electronics II Experiment EB1

Page:2

9. Table E3: Measure VL(pp) and Vin(pp), and calculated AV

f /kHz 1 2 5 10 20 40 60 80 100 200 500 550

VL(pp) /V

Vin(pp) /V

Av(dB)

[6 marks]

10. Graph E2: Av versus frequency

[5 marks]

11. DDL

calLDCRR

f

2

1)(

= _________ Hz

)(measLDf = _________ Hz

12. )(measHDf = _________ kHz

13. BW = fHD – fLD = _________ kHz

HDLDo fff = _________ kHz

[5 marks]


Page:3

Questions (All the calculation steps must be shown clearly)

1. Fill the following table showing the colors of the resistors according to the color code and

the reads of the capacitor also.

Resistance

Resistance value Colors

23 KΩ

1.9 Ω

3.3 KΩ

3.9 KΩ

Capacitor

Capacitor value Code

0.5 µF

0.01 µF

0.47 µF

1000 pF

2. Explain why the calculated Gate volage, VG(cal) is difference from the measured Gate

voltage, VG(meas).

________________________________________________________________________

________________________________________________________________________

3. Calculate the actual DC currents flowing through RD (IRD) and RS (IRS). Comment on the

answer obtained.

________________________________________________________________________

________________________________________________________________________

4. Estimate the total output capacitance which determines the upper cutoff frequency fHD

________________________________________________________________________

________________________________________________________________________

5. State the measured value for Gate-Source Cutoff Voltage (VGS(off) or Vp) and Zero-Gate

Voltage Current (IDSS) obtained from Procedure Step No. 14,.

________________________________________________________________________

[16 marks]


Page:4

6. Junction field effect transistors (JFET) contain how many diodes?

a. 1 b. 2 c. 3 d. 4

7. When VGS = 0 V, a JFET is:

a. Analogue device. c. Cutoff.

b. Saturated. d. An open switch

8. The common-source JFET amplifier has:

a. A very high input impedance and a relatively low voltage gain.

b. A high input impedance and a very high voltage gain.

c. A high input impedance and a voltage gain less than 1.

d. No voltage gain.

9. Pinch-off voltage in a JFET is

a. The drain voltage that gives zero drain current.

b. The gate to source voltage that gives unity drain current.

c. The gate to source voltage that gives zero drain current.

d. The drain voltage that gives infinite drain current.

10. Which of following is the point of reference JFET?

a. Drain.

b. Gate.

c. Source.

d. None of above.

11. The gate controls:

a. The width of the channel.

b. The drain current.

c. The gate voltage.

d. All of them.

12. In the constant-current region, how will the IDS change in an n-channel JFET?

a. As VGS decreases ID decreases.

b. As VGS increases ID increases.

c. As VGS decreases ID remains constant.

d. As VGS increases ID remains constant.

[7 marks]

http://www.electrical4u.com/voltage-or-electric-potential-difference/










Page:5

Discussion

1. Identify how the vin and vL waveforms in Step 7 are related in terms of positive and

negative peak voltages, waveform shapes and phase shift.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

2. Describe the Av versus frequency characteristic.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

3. Propose why fHD cannot be calculated and as to what factor determines this fHD.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

4. Discuss the working of JFET amplifiers.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

5. State at least one disadvantage of JFET amplifiers.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

[10 marks]


Page:6

Explain what is the pinch-off voltage and the explain the behavior of the drain electric

current when varying VDS of a JFET amplifier.

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

[6 marks]

Conclude your work by explaining why the frequency response analysis is important for

amplifiers.

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

__________________________________________________________________________

___________________________________________________________________________

[7 marks]


STUDENT'S NAME:

ID NO:

SUBJECT CODE AND TITLE: EEN1026 ELECTRONICS 2

EXPERIMENT TITLE: EB1 - FET Amplifier Frequency Response

EXPERIMENT DATE: TIME:

Criteria 1 2 3 4

Rating Awarded

by Assessor

Data Collection and Setting up the Experiment

1 Ability to construct the

amplifier circuit on the

breadboard

Unable to construct the

amplifier circuit, and not

asking for help.

Able to construct the

amplifier circuit

partially.

Able to construct the

amplifier circuit.

Able to construct the amplifier

circuit correctly, with neat and

tidy placement of components

and jumper wires

2 Ability to set-up the power

supply for the circuit, the

function generator to the

amplifier and to connect the

oscilloscope to display the

waveform

Unable to setup the DC

or AC input to the

amplifier, and not asking

for help.

Able to setup the DC and

AC input to the amplifier

partially.

DC and AC input to the

amplifier is correctly

setup.

DC and AC input to the

amplifier is correctly setup and

the waveforms are visible in the

oscilloscope.

Analysis and Conclusions

3 Ability to extract the

midband amplifier's

characteristics.

No voltage gain is

observed, and not asking

for help.

No voltage gain is

observed, but the

waveforms are

approximately at

opposite phase.

Voltage gain is more than

unity, with the input and

output at approximately

opposite phase.

The voltage gain is fair, with

the input and output at opposite

phase.

4 Ability to extract the

amplifier's complete

frequency response.

There is no difference

between the low-, mid-

and high-frequency

response of the

amplifier.

Minor differences

between the low-, mid-

and high-frequency

response of the

amplifier.

Low-, mid- and high-

frequency response of the

amplifier shows some

difference.

Low-, mid- and high-frequency

response of the amplifier is

clearly seen on a graph.

5 Ability to answer the

questions in by Oral

Assessment

Not able to answer the

question, no attempt was

made to answer

Able to answer questions

with some basics

answers and

demonstrate some

attempts to refer to the

text books, notes, lab

sheet

Able to answer most part

of the questions, with

some explanations and

elaborations and

demonstrate some

attempts to refer to text

books, notes or lab sheet

Answered all correctly with

proper explanations and

elaborations, without a need to

refer to any references.

Note: This form is to be attached together with the Lab results

Experiment EB1: FET Amplifier Frequency Response - …foe.mmu.edu.my/lab/lab...

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